Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is in response to amendment filed on 5/28/2026. Claim 1 is cancelled, claims 2-21 are pending for examination.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 2-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cline et al., US 2010/0185810 A1.
Regarding claim 2, Cline teaches a system (Fig.1; a DRAM system 100) comprising:
a set of memory dies (Fig.1; it is taught as a plurality of memory devices such as DRAM devices); and
a multi-portion interface (Fig.1; it is taught as data bus 108 and section 0020-0021) coupled to the set of memory dies (Fig.1), the multi-portion interface comprising:
a first bus portion (claim 1 of Cline; it is taught as a first portion of the data bus) assigned to process a command associated with the set of memory dies (claim 1 of Cline); and
a second bus portion (claim 1 of Cline; it is taught as a second portion of the data bus) assigned to process a data burst associated with the set of memory dies (claim 1 of cline; sections 0084 and 0107), wherein the multi-portion interface concurrently processes the command via the first bus portion and the data burst via the second bus portion (section 0107 and claims 1 and 31; the additive write-latency configuration mechanism concurrently sends a write command and one or more data bursts to the memory device, thereby allowing the memory device to measure its native write latency based on a value of the data burst received in response to the write command).
Regarding claim 3, Cline teaches the first bus portion is configured to process one or more status polling communications associated with the set of memory dies (section 0072; command/address bus 1122 is routed from the controller to RANK 0 and RANK 1 in a fly-by topology. In a rank, a respective DRAM device couples to a respective lane of data bus 1124. For example, DRAM devices 1110, 1112, 1114, and 1116 in RANK 0 are coupled to LANE 0, LANE 1, LANE 2, and LANE 3 respectively).
Regarding claim 4, Cline teaches further comprising processing logic coupled to the multi- portion interface (Fig.1; memory controller coupled to the data bus 108).
Regarding claim 5, Cline teaches the processing logic manages a queue comprising the command and the data burst (Fig.1; it is taught as command/address bus 104 and data bus 108).
Regarding claim 6, Cline teaches the processing logic determines the command is associated with a first memory die of the set of memory dies (Fig.1).
Regarding claim 7, Cline teaches the processing logic causes a first communication of the command via the first bus portion to the first memory die (Fig.1).
Regarding claim 8, Cline teaches the processing logic determines the data burst is associated with a second memory die of the set of memory dies (section 0032; For the first two W.sub.1 commands, controller 202 places the corresponding data bursts on data bus 206 at the same time as the transmission of the W.sub.1 commands, because both DRAM devices in RANK 1 have zero native write latency (see FIG. 3). For the third write operation W.sub.0, controller 202 places the data burst on LANE 0 at clock cycle 8, and the data burst on LANE 1 at clock cycle 9).
Regarding claim 9, Cline teaches the processing logic causes a second communication of the data burst via the second bus portion to the second memory die (section 0072; command/address bus 1122 is routed from the controller to RANK 0 and RANK 1 in a fly-by topology. In a rank, a respective DRAM device couples to a respective lane of data bus 1124. For example, DRAM devices 1110, 1112, 1114, and 1116 in RANK 0 are coupled to LANE 0, LANE 1, LANE 2, and LANE 3 respectively).
Regarding claim 10, Cline teaches the first bus portion comprises a first set of one or more interface pins of the multi-portion interface (Fig.1; The data bus 108, on the other hand, includes multiple lanes (e.g., LANE 0 to LANE 5). A lane can carry a group of signals with matched timings).
Regarding claim 11, Cline teaches the second bus portion comprises a second set of one or more interface pins of the multi-portion interface (Fig.1; The data bus 108, on the other hand, includes multiple lanes (e.g., LANE 0 to LANE 5). A lane can carry a group of signals with matched timings).
Regarding claim 12, Cline teaches the second bus portion processes a further data burst transmitted by a memory die of the set of memory dies (Fig.1).
Regarding claim 13, Cline teaches the multi-portion interface concurrently processes a status polling communication via the first bus portion and a further data burst via the second bus portion (section 0072; command/address bus 1122 is routed from the controller to RANK 0 and RANK 1 in a fly-by topology. In a rank, a respective DRAM device couples to a respective lane of data bus 1124. For example, DRAM devices 1110, 1112, 1114, and 1116 in RANK 0 are coupled to LANE 0, LANE 1, LANE 2, and LANE 3 respectively).
Regarding claim 14, Cline teaches a system comprising:
a set of memory dies (Fig.1; it is taught as a plurality of memory devices such as DRAM devices);
a multi-portion interface (Fig.1; it is taught as data bus 108 and section 0020-0021) coupled to the set of memory dies (Fig.1); and
a processing device (Fig.1, memory controller 102), operatively coupled with the multi-portion interface (Fig.1), to perform operations comprising:
causing a processing of a first data burst by the multi-portion interface (claim 1 and section 0107);
determining the processing of the first data burst by the multi-portion interface is complete; and transmitting a command to a first memory die of the set of memory dies via the multi-portion interface, wherein the command causes the first memory die to transmit a second data burst via the multi-portion interface (section 0053; During the third read operation, controller 202 switches from RANK 0 to RANK 1 and issues an R.sub.1 command. Controller 202 places R.sub.1 in clock cycle 8 to ensure the data burst from DRAM device D.sub.10 properly follows the data burst from DRAM device D.sub.00).
Regarding claim 15, Cline teaches the multi-portion interface comprises:
a first portion assigned to process one or more commands associated with the set of memory dies (claim 1 of Cline; it is taught as a first portion of the data bus); and
a second portion assigned to process one or more data bursts associated with the set of memory dies (claim 1 of cline; sections 0084 and 0107).
Regarding claim 16, Cline teaches the processing device manages a queue comprising an ordered list comprising the first data burst and the second data burst (section 0064; Timing diagram 1002 illustrates the read commands on command/address bus 204 as well as the data bursts placed by the DRAM devices on data bus 206).
Regarding claim 17, Cline teaches the second data burst is associated with a read operation associated with the first memory die (section 0064; Timing diagrams 1004, 1006, and 1008 illustrate the data bursts transmitted by the DRAM devices in RANK 0, RANK 1, and RANK 2, respectively).
Regarding claim 18, Cline teaches a method comprising:
processing, via a first portion of a multi-portion interface, a command associated with a first target memory die of a set of memory dies (Fig.1; claim 1 of Cline; it is taught as a first portion of the data bus); and
processing, via a second portion of the multi-portion interface, a data burst associated with a second target memory die of the set of memory dies (claim 1 of Cline; it is taught as a second portion of the data bus).
Regarding claim 19, Cline teaches the multi-portion interface concurrently processes the command via the first portion and the data burst via the second portion (section 0107 and claims 1 and 31; the additive write-latency configuration mechanism concurrently sends a write command and one or more data bursts to the memory device, thereby allowing the memory device to measure its native write latency based on a value of the data burst received in response to the write command).
Regarding claim 20, Cline teaches further comprising processing, via the first portion of the multi-portion interface, a further data burst associated with the command (section 0051; a read command is denoted as R.sub.i, wherein i is the rank index. The second and third rows illustrate the data bursts placed by the DRAM devices on LANE 0 and LANE 1 of data bus 206, respectively. Each data burst is assumed to occupy four clock cycles).
Regarding claim 21, Cline teaches further comprising processing a status polling communication via the first portion and a further data burst via the second portion (section 0072; command/address bus 1122 is routed from the controller to RANK 0 and RANK 1 in a fly-by topology. In a rank, a respective DRAM device couples to a respective lane of data bus 1124. For example, DRAM devices 1110, 1112, 1114, and 1116 in RANK 0 are coupled to LANE 0, LANE 1, LANE 2, and LANE 3 respectively).
When responding to the office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111 (c).
When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist examiner to locate the appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUA JASMINE SONG whose telephone number is (571)272-4213. The examiner can normally be reached on 9:00am to 5:30pm.
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/HUA J SONG/Primary Examiner, Art Unit 2133
