Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application is a continuation of U.S. Patent Application No. 18/144,957, filed May 9, 2023, which in turn claims the benefit of U.S. Provisional Application No. 63/340,762, filed May 11, 2022. Claim 1 is cancelled, claims 2-21 are pending for examination.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/23/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 2-21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pilolli., US 2022/0129396 A1.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 2, Pilolli teaches a system (Fig.1; computing system 100) comprising:
a set of memory dies (Fig.1 and section 0011; a non-volatile memory device is a package of one or more memory dies. Each die can consist of one or more planes); and
a multi-portion interface (Fig.2; it is taught as the command interface portion and the data burst interface portion; section 0041) coupled to the set of memory dies (Fig.2; section 0040-0041; a command is communicated to a memory device via a portion of an interface. For example, the processing logic of a controller of a memory sub-system communicates a set of memory device commands associated with one or more memory dies of a memory device via a first portion of an interface to the memory device; a data burst is communicated to the memory device via another portion of the interface. For example, the processing logic of a controller can cause communication of a set of data bursts corresponding to the set of memory device commands to the one or more memory dies via a second portion of the interface), the multi-portion interface comprising:
a first bus portion assigned to process a command associated with the set of memory dies (Fig.2 and section 0040; a command is communicated to a memory device via a portion of an interface. For example, the processing logic of a controller of a memory sub-system communicates a set of memory device commands associated with one or more memory dies of a memory device via a first portion of an interface to the memory device); and
a second bus portion assigned to process a data burst associated with the set of memory dies (Fig.2 and section 0041; a data burst is communicated to the memory device via another portion of the interface. For example, the processing logic of a controller can cause communication of a set of data bursts corresponding to the set of memory device commands to the one or more memory dies via a second portion of the interface), wherein the multi-portion interface concurrently processes the command via the first bus portion and the data burst via the second bus portion (section 0041-0042; wherein one or more of the set of memory commands is communicated via the first interface concurrently with one or more of the set of data bursts).
Regarding claim 3, Pilolli teaches the first bus portion is configured to process one or more status polling communications associated with the set of memory dies (section 0040; the command interface portion can further be used to transmit status polling communications to the one or more memory devices).
Regarding claim 4, Pilolli teaches further comprising processing logic coupled to the multi- portion interface (section 0047-0048; the processing logic of a controller assigns a first portion of an interface communicatively coupled to a memory device including a set of memory dies to process one or more commands from the controller; the processing logic of the controller assigns a second portion of the interface to process one or more data communications associated with the memory device).
Regarding claim 5, Pilolli teaches the processing logic manages a queue comprising the command and the data burst (according to applicant’s specification section 0005 and Fig.3; a queue comprising the command and the data burst is taught by Pilolli in Fig.5 as memory device interface).
Regarding claim 6, Pilolli teaches the processing logic determines the command is associated with a first memory die of the set of memory dies (section 0015; a controller of the memory sub-system identifies a memory device command associated with a memory die of the memory device).
Regarding claim 7, Pilolli teaches the processing logic causes a first communication of the command via the first bus portion to the first memory die (section 0015; the controller processes the memory device command using the first portion of the memory device interface (also referred to a “command interface” or “command interface portion”)).
Regarding claim 8, Pilolli teaches the processing logic determines the data burst is associated with a second memory die of the set of memory dies (section 0016 and Fig.5).
Regarding claim 9, Pilolli teaches the processing logic causes a second communication of the data burst via the second bus portion to the second memory die (section 0016 and Fig.5).
Regarding claim 10, Pilolli teaches the first bus portion comprises a first set of one or more interface pins of the multi-portion interface (Fig.3 and section 0043).
Regarding claim 11, Pilolli teaches the second bus portion comprise a second set of one or more interface pins of the multi-portion interface (Fig.3 and section 0043).
Regarding claim 12, Pilolli teaches the second bus portion processes a further data burst transmitted by a memory die of the set of memory dies (section 0041; a data burst is communicated to the memory device via another portion of the interface. For example, the processing logic of a controller can cause communication of a set of data bursts corresponding to the set of memory device commands to the one or more memory dies via a second portion of the interface).
Regarding claim 13, Pilolli teaches the multi-portion interface concurrently processes a status polling communication via the first bus portion and a further data burst via the second bus portion (section 0045; the command interface 322 can further be used to transmit status polling communications to the memory device 340. This enables the concurrent processing of status polling communications and data burst communications).
Regarding claim 14, Pilolli teaches a system comprising:
a set of memory dies (Fig.1 and section 0011; a non-volatile memory device is a package of one or more memory dies. Each die can consist of one or more planes); a multi-portion interface (Fig.2; it is taught as the command interface portion and the data burst interface portion; section 0041) coupled to the set of memory dies (Fig.2; section 0040-0041; a command is communicated to a memory device via a portion of an interface. For example, the processing logic of a controller of a memory sub-system communicates a set of memory device commands associated with one or more memory dies of a memory device via a first portion of an interface to the memory device; a data burst is communicated to the memory device via another portion of the interface. For example, the processing logic of a controller can cause communication of a set of data bursts corresponding to the set of memory device commands to the one or more memory dies via a second portion of the interface); and a processing device (section n0021 and 0030), operatively coupled with the multi-portion interface (Fig.1), to perform operations comprising:
causing a processing of a first data burst by the multi-portion interface (section 0041); determining the processing of the first data burst by the multi-portion interface is complete; and transmitting a command to a first memory die of the set of memory dies via the multi-portion interface (section 0013; when processing a command via the interface, the command/address cycle needs to complete before a data burst communication can be processed by the interface. Furthermore, when the interface is issuing a data burst to the memory device via the interface, the interface can not concurrently process a memory access command), wherein the command causes the first memory die to transmit a second data burst via the multi-portion interface (Fig.5).
Regarding claim 15, Pilolli teaches the multi-portion interface comprises: a first portion assigned to process one or more commands associated with the set of memory dies (Fig.2 and section 0040; a command is communicated to a memory device via a portion of an interface. For example, the processing logic of a controller of a memory sub-system communicates a set of memory device commands associated with one or more memory dies of a memory device via a first portion of an interface to the memory device); and a second portion assigned to process one or more data bursts associated with the set of memory dies (Fig.2 and section 0041; a data burst is communicated to the memory device via another portion of the interface. For example, the processing logic of a controller can cause communication of a set of data bursts corresponding to the set of memory device commands to the one or more memory dies via a second portion of the interface).
Regarding claim 16, Pilolli teaches the processing device manages a queue comprising an ordered list comprising the first data burst and the second data burst (Fig.5 and section 0055).
Regarding claim 17, Pilolli teaches the second data burst is associated with a read operation associated with the first memory die (see Fig.5; data output burst 2 with read of die 1).
Regarding claim 18, Pilolli teaches a method comprising: processing, via a first portion of a multi-portion interface, a command associated with a first target memory die of a set of memory dies (Fig.2 and section 0040; a command is communicated to a memory device via a portion of an interface. For example, the processing logic of a controller of a memory sub-system communicates a set of memory device commands associated with one or more memory dies of a memory device via a first portion of an interface to the memory device); and processing, via a second portion of the multi-portion interface, a data burst associated with a second target memory die of the set of memory dies (Fig.2 and section 0041; a data burst is communicated to the memory device via another portion of the interface. For example, the processing logic of a controller can cause communication of a set of data bursts corresponding to the set of memory device commands to the one or more memory dies via a second portion of the interface).
Regarding claim 19, Pilolli teaches the multi-portion interface concurrently processes the command via the first portion and the data burst via the second portion (section 0041-0042; wherein one or more of the set of memory commands is communicated via the first interface concurrently with one or more of the set of data bursts).
Regarding claim 20, Pilolli teaches further comprising processing, via the first portion of the multi-portion interface, a further data burst associated with the command (section 0041; data burst is communicated to the memory device via another portion of the interface).
Regarding claim 21, Pilolli teaches further comprising processing a status polling communication via the first portion and a further data burst via the second portion (section 0045; the command interface 322 can further be used to transmit status polling communications to the memory device 340. This enables the concurrent processing of status polling communications and data burst communications).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Cline et al., US 2010/0185810 A1 teaches Systems and methods are provided for in-DRAM cycle-based levelization for write and/or read operations in a multi-rank, multi-lane DRAM system. With in-DRAM cycle-based levelization, the system can individually program an additive write and/or read latency for a respective lane in a respective rank, thereby allowing the data bus to reach full utilization.
When responding to the office action, Applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111 (c).
When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist examiner to locate the appropriate paragraphs.
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/HUA J SONG/Primary Examiner, Art Unit 2133