DETAILED ACTION
This Office Action is a response to an application filed on 01/31/2025, in which claims 1-4 are pending and ready for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim interpretation
Claim 3’s recitation of a “non-transitory computer readable storage medium storing a bitstream generated by the encoding apparatus of claim 2” is a product by process claim limitation where the product is the bitstream and the process is the method steps to generate the bitstream. MPEP §2113 recites “Product-by-Process claims are not limited to the manipulations of the recited steps, only the structure implied by the steps”. Thus, the scope of the claim is the computer readable storage medium storing the bitstream (with the structure implied by the method steps). The structure includes the memory and processor, the target block and other information manipulated by the steps.
To be given patentable weight, the computer readable storage medium (a recording medium) and the bitstream (i.e. descriptive material) must be in a functional relationship. A functional relationship can be found where the descriptive material performs some function with respect to the storage medium to which it is associated. See MPEP §2111.05(I)(A). When a claimed “computer-readable medium merely serves as a support for information or data, no functional relationship exists”. MPEP §2111.05(III). The storage medium storing the claimed bitstream in claim 3 merely services as a support for the storage of the bitstream and provides no functional relationship between the stored bitstream and storage medium. Therefor the structure of the bitstream, which scope is implied by the method steps, is non-functional descriptive material and given no patentable weight. MPEP §2111.05(III). Thus, the claim scope is just a storage medium storing data.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 3 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhao (US 2017/0094313 A1).
Regarding claim 3, Zhao discloses a non-transitory computer readable storage medium storing the bitstream generated by the encoding apparatus of claim 2 (see Zhao, paragraph 48-49 and Fig. 1).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1, 2, and 4 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 9, and 20 of U.S. Patent No. 11,218,731 in view of Zhao (US 2017/0094313 A1).
Instant # 19/043,120
Patent # 11,218,731
A decoding apparatus for image decoding, the decoding apparatus comprising:
An image decoding method performed by a decoding apparatus, the method comprising:
a memory; and
at least one processor connected to the memory, the at least one processor configured to:
obtaining information on quantized transform coefficients from a bitstream;
deriving quantized transform coefficients for a target block based on the information on the quantized transform coefficients;
deriving, from a bitstream, quantized transform coefficients for a target block;
deriving transform coefficients by performing dequantization for the quantized transform coefficients for the target block;
deriving transform coefficients by performing dequantization for the quantized transform coefficients for the target block;
perform a non-separable transform on the transform coefficients based on an inverse transform matrix;
wherein the inverse transform is performed based on an inverse transform matrix,
perform a separable transform based on a result of the non-separable transform;
deriving residual samples for the target block based on the separable transform;
deriving residual samples for the target block based on inverse transform for the transform coefficients; and
generating a reconstructed picture based on the residual samples for the target block and prediction samples for the target block,
generating a reconstructed picture based on (1) the residual samples for the target block and (ii) prediction samples for the target block, wherein the inverse transform is performed based on an inverse transform matrix, wherein the inverse transform matrix is a non-square matrix,
wherein a size of the target block is KxK, where K is a positive integer,
wherein an area to which the inverse transform is applied is included in a region of size MxM, where M is a positive integer less than K, and
wherein based on a number of input elements of the non-separable transform being R and a number of output elements of the non-separable transform being N, a size of the inverse transform matrix is NxR, where each of N and R is a positive integer, and R is less than N, and
wherein based on a number of elements in the area to which the inverse transform is applied being R, a size of the inverse transform matrix is NxR, where each of N and R is a positive integer, and R is less than N.
wherein for the target block of which size is larger than 8x8, R is predetermined to be 16.
Patent No. 11,218,731 does not disclose “a memory; and at least one processor connected to the memory, the at least one processor configured to: perform a non-separable transform; perform a separable transform based on a result of the non-separable transform, and wherein for the target block of which size is larger than 8x8, R is predetermined to be 16.”
However, Zhao from the same or similar endeavor discloses: a memory (see Zhao, paragraph 57); and
at least one processor connected to the memory (see Zhao, paragraph 57), the at least one processor configured to:
perform a non-separable transform (see Zhao, paragraph 44, the first inverse transform being a non-separable transform);
perform a separable transform based on a result of the non-separable transform (see Zhao, paragraph 46, the video encoder uses a separable transform and a non-separable transform, also see paragraph 44, the first inverse transform being a non-separable transform), and
wherein for the target block of which size is larger than 8x8, R is predetermined to be 16 (see Zhao, paragraph 103).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have “a memory; and at least one processor connected to the memory, the at least one processor configured to: perform a separable transform based on a result of the non-separable transform, and wherein for the target block of which size is larger than 8x8, R is predetermined to be 16” as taught by Zhao in the system taught by the US Patent No. 11,218,731 to reduce an amount of data used to represent the residual blocks such that an amount of data transmitted from the video encoder to the video decoder is reduced (see Zhao, paragraph 42).
Claims 1, 2, and 4 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 11, and 19-20 of U.S. Patent No. 11,601,679 in view of Zhao (US 2017/0094313 A1).
Instant # 19/043,120
Patent # 11,601,679
A decoding apparatus for image decoding, the decoding apparatus comprising:
An image decoding method performed by a decoding apparatus, the method comprising:
a memory; and
at least one processor connected to the memory, the at least one processor configured to:
obtaining information on quantized transform coefficients from a bitstream;
obtaining information on quantized transform coefficients from a bitstream;
deriving quantized transform coefficients for a target block based on the information on the quantized transform coefficients;
deriving quantized transform coefficients for a target block based on the information on the quantized transform coefficients;
deriving transform coefficients by performing dequantization for the quantized transform coefficients for the target block;
deriving transform coefficients by performing dequantization for the quantized transform coefficients for the target block;
perform a non-separable transform on the transform coefficients based on an inverse transform matrix;
performing an inverse transform for the transform coefficients based on an inverse transform matrix;
perform a separable transform based on a result of the non-separable transform;
deriving residual samples for the target block based on the separable transform;
deriving residual samples for the target block based on a result of the inverse transform; and
generating a reconstructed picture based on the residual samples for the target block and prediction samples for the target block,
generating a reconstructed picture based on (i) the residual samples for the target block and (ii) prediction samples for the target block,
wherein a size of the target block is KxK, where K 1s a positive integer
wherein an area to which the inverse transform is applied is included in a region of size MxM, where M is a positive integer less than K, and
wherein based on a number of input elements of the non-separable transform being R and a number of output elements of the non-separable transform being N, a size of the inverse transform matrix is NxR, where each of N and R is a positive integer, and R is less than N, and
wherein based on a number of input elements of the inverse transform being R, a size of the inverse transform matrix is NxR, where each of N and R is a positive integer, and R is less than N.
wherein for the target block of which size is larger than 8x8, R is predetermined to be 16.
Patent No. 11,601,679 does not disclose “a memory; and at least one processor connected to the memory, the at least one processor configured to: perform a non-separable transform; perform a separable transform based on a result of the non-separable transform, and wherein for the target block of which size is larger than 8x8, R is predetermined to be 16.”
However, Zhao from the same or similar endeavor discloses: a memory (see Zhao, paragraph 57); and
at least one processor connected to the memory (see Zhao, paragraph 57), the at least one processor configured to:
perform a non-separable transform (see Zhao, paragraph 44, the first inverse transform being a non-separable transform);
perform a separable transform based on a result of the non-separable transform (see Zhao, paragraph 46, the video encoder uses a separable transform and a non-separable transform, also see paragraph 44, the first inverse transform being a non-separable transform), and
wherein for the target block of which size is larger than 8x8, R is predetermined to be 16 (see Zhao, paragraph 103).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have “a memory; and at least one processor connected to the memory, the at least one processor configured to: perform a non-separable transform; perform a separable transform based on a result of the non-separable transform, and wherein for the target block of which size is larger than 8x8, R is predetermined to be 16” as taught by Zhao in the system taught by the US Patent No. 11,601,679 to reduce an amount of data used to represent the residual blocks such that an amount of data transmitted from the video encoder to the video decoder is reduced (see Zhao, paragraph 42).
Claims 1, 2, and 4 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, and 6 of U.S. Patent No. 11,895,334 in view of Zhao (US 2017/0094313 A1).
Instant # 19/043,120
Patent # 11,895,334
A decoding apparatus for image decoding, the decoding apparatus comprising:
A decoding apparatus for image decoding, the decoding apparatus comprising:
a memory; and
a memory; and
at least one processor connected to the memory, the at least one processor configured to:
at least one processor connected to the memory, the at least one processor configured to:
obtaining information on quantized transform coefficients from a bitstream;
obtaining information on quantized transform coefficients from a bitstream;
deriving quantized transform coefficients for a target block based on the information on the quantized transform coefficients;
deriving quantized transform coefficients for a target block based on the information on the quantized transform coefficients;
deriving transform coefficients by performing dequantization for the quantized transform coefficients for the target block;
deriving transform coefficients by performing dequantization for the quantized transform coefficients for the target block;
perform a non-separable transform on the transform coefficients based on an inverse transform matrix;
performing an inverse transform for the transform coefficients based on an inverse transform matrix;
perform a separable transform based on a result of the non-separable transform;
deriving residual samples for the target block based on the separable transform;
deriving residual samples for the target block based on a result of the inverse transform; and
generating a reconstructed picture based on the residual samples for the target block and prediction samples for the target block,
generating a reconstructed picture based on the residual samples for the target block and prediction samples for the target block,
wherein based on a number of input elements of the non-separable transform being R and a number of output elements of the non-separable transform being N, a size of the inverse transform matrix is NxR, where each of N and R is a positive integer, and R is less than N, and
wherein based on a number of input elements of the inverse transform being R, a size of the inverse transform matrix is NxR, where each of N and R is a positive integer, and R is less than N.
wherein for the target block of which size is larger than 8x8, R is predetermined to be 16.
Patent No. 11,895,334 does not disclose “perform a non-separable transform; perform a separable transform based on a result of the non-separable transform, and wherein for the target block of which size is larger than 8x8, R is predetermined to be 16.”
However, Zhao from the same or similar endeavor discloses: perform a non-separable transform (see Zhao, paragraph 44, the first inverse transform being a non-separable transform);
perform a separable transform based on a result of the non-separable transform (see Zhao, paragraph 46, the video encoder uses a separable transform and a non-separable transform, also see paragraph 44, the first inverse transform being a non-separable transform), and
wherein for the target block of which size is larger than 8x8, R is predetermined to be 16 (see Zhao, paragraph 103).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to “perform a non-separable transform; perform a separable transform based on a result of the non-separable transform, and wherein for the target block of which size is larger than 8x8, R is predetermined to be 16” as taught by Zhao in the system taught by the US Patent No. 11,895,334 to reduce an amount of data used to represent the residual blocks such that an amount of data transmitted from the video encoder to the video decoder is reduced (see Zhao, paragraph 42).
Claims 1, 2, and 4 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3, and 6 of U.S. Patent No. 12,244,861 in view of Zhao (US 2017/0094313 A1).
Instant # 19/043,120
Patent # 12,244,861
A decoding apparatus for image decoding, the decoding apparatus comprising:
A decoding apparatus for image decoding, the decoding apparatus comprising:
a memory; and
a memory; and
at least one processor connected to the memory, the at least one processor configured to:
at least one processor connected to the memory, the at least one processor configured to:
obtaining information on quantized transform coefficients from a bitstream;
obtaining information on quantized transform coefficients from a bitstream;
deriving quantized transform coefficients for a target block based on the information on the quantized transform coefficients;
deriving quantized transform coefficients for a target block based on the information on the quantized transform coefficients;
deriving transform coefficients by performing dequantization for the quantized transform coefficients for the target block;
deriving transform coefficients by performing dequantization for the quantized transform coefficients for the target block;
perform a non-separable transform on the transform coefficients based on an inverse transform matrix;
deriving residual samples for the target block by performing an inverse transform for the transform coefficients based on an inverse transform matrix;
perform a separable transform based on a result of the non-separable transform;
deriving residual samples for the target block based on the separable transform;
deriving residual samples for the target block by performing an inverse transform for the transform coefficients based on an inverse transform matrix;
generating a reconstructed picture based on the residual samples for the target block and prediction samples for the target block,
generating a reconstructed picture based on the residual samples for the target block and prediction samples for the target block,
wherein based on a number of input elements of the non-separable transform being R and a number of output elements of the non-separable transform being N, a size of the inverse transform matrix is NxR, where each of N and R is a positive integer, and R is less than N, and
wherein based on a number of input elements of the inverse transform being R, a size of the inverse transform matrix is NxR, where each of N and R is a positive integer, and R is less than N,
wherein for the target block of which size is larger than 8x8, R is predetermined to be 16.
wherein for the target block of which size is larger than 8x8, R is predetermined to be 16.
Patent No. 11,244,861 does not disclose “perform a non-separable transform; perform a separable transform based on a result of the non-separable transform”
However, Zhao from the same or similar endeavor discloses: perform a non-separable transform (see Zhao, paragraph 44, the first inverse transform being a non-separable transform);
perform a separable transform based on a result of the non-separable transform (see Zhao, paragraph 46, the video encoder uses a separable transform and a non-separable transform, also see paragraph 44, the first inverse transform being a non-separable transform).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to “perform a non-separable transform; perform a separable transform based on a result of the non-separable transform” as taught by Zhao in the system taught by the US Patent No. 12,244,861 to reduce an amount of data used to represent the residual blocks such that an amount of data transmitted from the video encoder to the video decoder is reduced (see Zhao, paragraph 42).
Allowable Subject Matter
Claims 1, 2, and 4 would be allowed upon overcoming the double patenting rejection mentioned above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Wu (US 2017/0230677 A1).
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/MARYAM A NASRI/Primary Examiner, Art Unit 2483