Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1 and 15.
b. Claims 1-15 are pending on the application.
Drawings
2. The drawings were received on 02/03/2025. These drawings are review and accepted by examiner.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgment is made of applicant’s Information Disclosure Statement
(IDS) Form PTO-1449; filed 02/03/2025. The information disclosed therein was considered.
Specification
5. Applicant is reminded of the proper language and format for an abstract of the disclosure. The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words. It is important that the abstract not exceed 150 words in length since the space provided for the abstract on the computer tape used by the printer is limited. The form and legal phraseology often used in patent claims, such as "means" and "said," should be avoided. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, "The disclosure concerns," "The disclosure defined by this invention," "The disclosure describes," etc.
The abstract of the disclosure is objected to because it uses the phrase “OF THE DICLOSURE” in page 1, line 1, which is implied. Correction is required. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
6. Claims 1-3, 9-10, 14 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Negishi et al. (Pub. No.: US 2020/0207089 A1; “Negishi et al”).
Regarding to independent claim 1, Negishi et al in Figures 1-10 are directly discloses a semiconductor device (a semiconductor device such as a memory module 206 as show in Figures 1-3) comprising:
a semiconductor substrate (a substrate element 400, Figs. 1-3);
an anti-fuse element (an anti-fuse element Ca, Figs. 1-3) arranged on the semiconductor substrate (the substrate 400) and connected to a first terminal (a terminal A, Fig. 3) with a first potential (a voltage VID, Figs. 1-3);
a first transistor (a transistor MD2, Figs. 1-3) arranged on the semiconductor substrate (the substrate 400) and connected between the anti-fuse element (the anti-fuse Ca) and a second terminal (a terminal B) with a second potential different (a ground GNDH) from the first potential;
a logic circuit (a logic circuit AND2, Figs. 1-3) connected to a gate of the first transistor (the transistor MD2, the output of AND2 coupled to the gate of the transistor MD2, Figs. 1-2); and
a long-pulse detection circuit (an ejection module 204, Figs. 1-2) connected to the logic circuit (the logic circuit AND2), wherein the long-pulse detection circuit is connected to a third terminal into which a write signal (a write signal CLK, DATA, LT, HE) for the anti-fuse element is inputted (a signal line 202, 203, 205 coupled to the logic circuit AND2, Figs. 1-2), and drive of the first transistor (the transistor MD2) is stopped based on a long-pulse detection signal (an ejection module 204) outputted from the long-pulse detection circuit (the control data supply circuit 201 generate the signal line 202, 203 and 205 are input to the control data supply circuit 201 from the outside of the recording element substrate via the terminal of the recording element substrate, see at least in Figures 1-3, paragraph 0020 to paragraph 0038 and the related disclosures).
Regarding dependent claim 2, Negishi et al in Figures 1-10 are directly discloses a semiconductor device (a semiconductor device such as a memory module 206 as show in Figures 1-3), wherein the logic circuit outputs (a logic circuit AND2, Figs. 1-3) a signal to the gate of the first transistor (the transistor MD1) based on the long-pulse detection signal (an ejection module circuit 204) and the write signal (clock signal CLK)(an ejection module circuit 204 includes the logic circuit AND1, which is coupled to the gate of transistor MD1, Fig. 2)..
Regarding dependent claim 3, Negishi et al in Figures 1-10 are directly discloses a semiconductor device (a semiconductor device such as a memory module 206 as show in Figures 1-3), wherein the logic circuit outputs a signal (a logic circuit AND2, Figs. 1-3) of turning off the first transistor (the transistor MD1) in a case where the long-pulse detection signal (an ejection module circuit 204) is a signal of detection of a long pulse (an ejection module circuit 204 includes the logic circuit AND1, which is coupled to the gate of transistor MD1, Fig. 2).
Regarding dependent claim 9, Negishi et al in Figures 1-10 are directly discloses a semiconductor device (a semiconductor device such as a memory module 206 as show in Figures 1-3), wherein the first terminal (the TERMINAL A) supplies a write voltage (a voltage VID) for the anti-fuse element (an anti-fuse Ca), and the second terminal is a ground (the TERMINAL B is coupled to the ground GNDH, Fig. 3).
Regarding dependent claim 10, Negishi et al in Figures 1-10 are directly discloses a semiconductor device (a semiconductor device such as a memory module 206 as show in Figures 1-3), wherein the first transistor (the transistor MD2) is an N-type high-voltage-tolerant transistor (the transistor MD2 is the type of nmos transistor, Fig. 2).
Regarding dependent claim 14, Negishi et al in Figures 1-10 are directly discloses a semiconductor device (a semiconductor device such as a memory module 206 as show in Figures 1-3), wherein one of the long-pulse detection circuit (an ejection circuit 204) is connected to a plurality of the anti-fuse elements (an ejection circuit 204 include anti-fuse element Ca, Fig. 2).
Regarding to independent claim 15, Negishi et al in Figures 1-10 are directly discloses a liquid ejection head substrate comprising a semiconductor device (a semiconductor device such as a memory module 206 as show in Figures 1-3) comprising:
a semiconductor substrate (a substrate element 400, Figs. 1-3);
an anti-fuse element (an anti-fuse element Ca, Figs. 1-3) arranged on the semiconductor substrate (the substrate 400) and connected to a first terminal (a terminal A, Fig. 3) with a first potential (a voltage VID, Figs. 1-3);
a first transistor (a transistor MD2, Figs. 1-3) arranged on the semiconductor substrate (the substrate 400) and connected between the anti-fuse element (the anti-fuse Ca) and a second terminal (a terminal B) with a second potential different (a ground GNDH) from the first potential;
a logic circuit (a logic circuit AND2, Figs. 1-3) connected to a gate of the first transistor (the transistor MD2, the output of AND2 coupled to the gate of the transistor MD2, Figs. 1-2); and
a long-pulse detection circuit (an ejection module 204, Figs. 1-2) connected to the logic circuit (the logic circuit AND2), wherein the long-pulse detection circuit is connected to a third terminal into which a write signal (a write signal CLK, DATA, LT, HE) for the anti-fuse element is inputted (a signal line 202, 203, 205 coupled to the logic circuit AND2, Figs. 1-2), and
drive of the first transistor (the transistor MD2) is stopped based on a long-pulse detection signal (an ejection module 204) outputted from the long-pulse detection circuit (the control data supply circuit 201 generate the signal line 202, 203 and 205 are input to the control data supply circuit 201 from the outside of the recording element substrate via the terminal of the recording element substrate, see at least in Figures 1-3, paragraph 0020 to paragraph 0038 and the related disclosures).
Allowable Subject Matter
7. Claims 4-8 and 11-13, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claims 4 and 6-8, the prior art fails to tech or suggest the claimed limitations, namely, the long-pulse detection circuit includes a resistance element, a capacitance, a second transistor, and an inverter, and a gate of the second transistor is connected to the third terminal, a drain of the second transistor is connected to the resistance element, the capacitance, and the inverter, a source of the second transistor is connected to a logic ground, in the resistance element, a terminal on an opposite side to a terminal connected to the drain of the second transistor is connected to a logic power supply, in the capacitance, a tenninal on an opposite side to a terminal connected to the drain of the second transistor is connected to the logic ground, and the inverter is connected to the logic circuit.
With respected to dependent claim 5, the prior art fails to tech or suggest the claimed limitations, namely, the long-pulse detection circuit includes a resistance element, a capacitance, a second transistor, and an inverter,a gate of the second transistor is connected to the third terminal,a source of the second transistor is connected to the resistance element, the capacitance, and the inverter,a drain of the second transistor is connected to a logic power supply,in the resistance element, a terminal on an opposite side to a terminal connected to the source of the second transistor is connected to a logic ground,in the capacitance, a terminal on an opposite side to a terminal connected to the source of the second transistor is connected to the logic power supply, andthe inverter is connected to the logic circuit.
With respected to dependent claims 11-13, the prior art fails to tech or suggest the claimed limitations, namely, a second resistance element arranged on the semiconductor substrate and connected between the first terminal and the first transistor in parallel to the anti-fuse element, wherein the resistance element included in the long-pulse detection circuit and the second resistance element are made of a common material, wherein the common material is a diffusion resistance.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dono (US. 2010/0124139 A1) discloses semiconductor device including an anti-fuse element.
Candelier et al (US. 2013/0294142 A1) discloses method for controlling the breakdown of an antifuse memory cell.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see
http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov
Prosecution Insights