DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
3. The information disclosure statements (IDS) submitted on February 3, 2025, February 13, 2025, and April 30, 2025 are considered by the examiner.
Claim Objections
4. Claim 3 is objected to because of the following informalities: Line 1 states “The method according to claim 3”. Per MPEP 608.01(n)(III), “In accordance with 35 U.S.C. 112(d), or pre-AIA 35 U.S.C. 112, fourth paragraph, a claim in dependent form shall contain: (i) a reference to a claim previously set forth.” Claim 3 cannot depend on itself. The Examiner will interpret claims 3 and 4 to be dependent on claim 1 instead. Appropriate correction is required.
5. Claim 10 objected to because of the following informalities: Line 6, "a successful allocation" should be "the successful allocation" because already mentioned in Line 3. Appropriate correction is required.
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claim(s) 1-2, 5-6, 8, 14-15, and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goudie (U.S. Patent Application Publication No. 2022/0114013 A1) in view of Zhao et al. (U.S. Patent Application Publication No. 2016/0035128 A1), hereinafter referred to as Zhao.
9. Regarding claim 1, Goudie teaches a method of managing resources in a graphics processing unit (GPU) (Paragraph 94 teaches the processor executes the methods described by Goudie and Paragraph 96 teaches the processor can be a GPU), the method comprising: allocating a region of off-chip storage to a geometry task on creation of the geometry task (Paragraph 63 teaches a task can implement a shader program. This teaches a geometry task; Paragraph 64 and Figure 3 step 302 teach the GPU allocating a block of memory in off-chip memory for a primary task. The primary task is a geometry task as taught in Paragraph 63. This teaches allocating a region of off-chip storage on creation of the geometry task);
receiving, at an on-chip store in the GPU, a memory allocation request for the geometry task from a shader core in the GPU, wherein the memory allocation request is received after generation of geometry data for the geometry task (Paragraph 46 teaches "when a shader recursion instruction is executed, the intermediate data for the parent task is written to memory… it may be possible to store the intermediate data in on-chip resources". The intermediate data teaches geometry data and the parent task teaches a geometry task since it is executing shader programs as taught in Paragraph 45. Storing geometry data on-chip requires allocation of space to the on-chip storage and thus also teaches a memory allocation request for a geometry task from a shader core in the GPU. Paragraph 2 teaches a shader program is executed by a processor which teaches a shader core exists in the GPU; Paragraph 64 teaches "the principles described herein are also applicable to the allocation of memory in on-chip memory." This teaches a memory allocation request can also be performed on the on-chip memory or on-chip store);
in response to receiving the memory allocation request, determining, by the on-chip store, whether to allocate a region of the on-chip store to the geometry task (Paragraph 46 teaches "it may be possible to store the intermediate data in on-chip resources …. The amount of this on-chip resource may need to be greater than that which is normally implemented." It also teaches that if the on-chip storage capability is insufficient, then "the intermediate data will tend to be stored in off-chip memory." This teaches determining whether to allocate a region of the on-chip store to the geometry task's intermediate data or whether to allocate it off-chip);
However, Goudie is not relied upon for the below claim language: in response to determining to allocate the region of the on-chip store to the geometry task, allocating the region, wherein in response to allocating the region of the on-chip store, geometry data for the geometry task is written to the on-chip store and in response to determining not to allocate the region of the on-chip store, the geometry data is written to the allocated region of off- chip storage.
Zhao teaches in response to receiving the memory allocation request, determining, by the on-chip store, whether to allocate a region of the on-chip store to the geometry task (Paragraph 35 teaches "The vertex attribute shading results of in-tile vertices are not kept in the VVB 306, but may be kept in the second storage device 110 (if the overflow condition is not met) or the COV buffer 310 (if the overflow condition is met)". This teaches determining by the on-chip store whether to allocate a region of the on-chip store to the geometry task based on the overflow condition);
and in response to determining to allocate the region of the on-chip store to the geometry task, allocating the region, wherein in response to allocating the region of the on-chip store, geometry data for the geometry task is written to the on-chip store (Paragraph 35 teaches "the vertex attribute shading results of in-tile vertices are not kept in the VVB 306, but may be kept in the second storage device 110 (if the overflow condition is not met)". This teaches determining to allocating and storing the results of vertex attribute shading to a region of the on-chip store 110. Storing the results teaches writing the geometry data for the geometry task to the on-chip store. Paragraph 35 also teaches the second storage device 110 is an on-chip cache)
and in response to determining not to allocate the region of the on-chip store, the geometry data is written to the allocated region of off- chip storage (Paragraph 35 teaches "the COV buffer 310 … is a fixed-size buffer … and is used to buffer varying data (i.e. vertex attribute shading results) of in-tile vertices generated from the vertex attribute shader 114 when an overflow condition of the second storage device 110 is met." It also teaches that the second storage device 110 "the second storage device 110 may be implemented using an on-chip cache" and that the "COV buffer 310 is allocated in the off-chip bin memory". Thus, the second storage device teaches the on-chip store and the COV buffer teaches the off-chip storage. This teaches determining not to allocate the region of the on-chip store to the geometry data when the on-chip store is in overflow and writing it to off-chip storage instead).
Goudie and Zhao are considered analogous to the claimed invention as because both are in the same field of allocating and storing data for graphic processing tasks. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the method of allocating memory for a geometry task taught by Goudie with the determining to allocate and writing the geometry data for a geometry task on the on-chip store or off-chip storage taught by Zhao in order to reduce memory traffic of an off-chip memory (Zhao Paragraph 55).
10. Regarding claim 2, Goudie in view of Zhao teaches the limitations of claim 1. However, Goudie is not relied upon for the below claim language: the method further comprising: in response to allocating the region of the on-chip store, directing a subsequent write instruction for the geometry task received at the on-chip store to the allocated region; and in response to determining not to allocate the region of the on-chip store, directing a subsequent write instruction for the geometry task received at the on-chip store to the allocated region of the off-chip storage.
Zhao teaches the method further comprising: in response to allocating the region of the on-chip store, directing a subsequent write instruction for the geometry task received at the on-chip store to the allocated region; and in response to determining not to allocate the region of the on-chip store, directing a subsequent write instruction for the geometry task received at the on-chip store to the allocated region of the off-chip storage (Paragraph 35 teaches "The vertex attribute shading results of in-tile vertices are not kept in the VVB 306, but may be kept in the second storage device 110 (if the overflow condition is not met) or the COV buffer 310 (if the overflow condition is met). In other words, the priority of writing vertex attribute shading results of in-tile vertices into the on-chip cache is higher than the priority of writing vertex attribute shading results of in-tile vertices into a fixed-size buffer allocated in an off-chip bin memory." The writing results for a geometry task being kept in the second storage device 110 if the overflow condition is not met teaches allocating and directing a subsequent write instruction for the geometry task to the second storage device 110, or on-chip store, to the allocated region. On the other hand, if the overflow condition is met, Zhao teaches determining not to allocate the region of the on-chip store and directing the subsequent write instruction to the allocated region of the off-chip storage, the COV buffer).
Goudie and Zhao are considered analogous to the claimed invention as because both are in the same field of allocating and storing data for graphic processing tasks. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the method of allocating memory for a geometry task taught by Goudie with the determining to direct writes of the geometry data for a geometry task on the on-chip store or off-chip storage taught by Zhao in order to reduce memory traffic of an off-chip memory (Zhao Paragraph 55).
11. Regarding claim 5, Goudie in view of Zhao teaches the limitations of claim 1. However, Goudie is not relied upon for the below claim language: the method wherein determining, by the on-chip store, whether to allocate a region of the on-chip store to the geometry task comprises: in response to determining that space is available in the on-chip store, allocating the region of the on-chip store to the geometry task.
Zhao teaches the method wherein determining, by the on-chip store, whether to allocate a region of the on-chip store to the geometry task comprises: in response to determining that space is available in the on-chip store, allocating the region of the on-chip store to the geometry task (Paragraph 35 teaches "the vertex attribute shading results of in-tile vertices are not kept in the VVB 306, but may be kept in the second storage device 110 (if the overflow condition is not met)". The overflow condition not being met teaches there is space in the on-chip store or second storage device. This teaches determining to allocate a region of the on-chip store 110 to the geometry task of vertex attribute shading when there is space).
Goudie and Zhao are considered analogous to the claimed invention as because both are in the same field of allocating and storing data for graphic processing tasks. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the method of allocating memory for a geometry task taught by Goudie with the determining the available space in the on-chip store taught by Zhao in order to reduce memory traffic of an off-chip memory (Zhao Paragraph 55).
123. Regarding claim 6, Goudie in view of Zhao teaches the limitations of claim 5. However, Goudie is not relied upon for the below claim language: the method wherein determining, by the on-chip store, whether to allocate a region of the on-chip store to the geometry task further comprises: in response to determining that space is not available in the on-chip store, determining whether a geometry pipeline in the GPU is in an out-of-memory state; in response to determining that the geometry pipeline is in an out-of-memory state, determining not to allocate the region of the on-chip store.
Zhao teaches the method wherein determining, by the on-chip store, whether to allocate a region of the on-chip store to the geometry task further comprises: in response to determining that space is not available in the on-chip store, determining whether a geometry pipeline in the GPU is in an out-of-memory state (Paragraph 35 teaches allocating space in the COV buffer when an overflow condition of the second storage device 110 is met. The second storage device 110 is taught to be an on-chip cache or on-chip store. The overflow condition being met teaches that space is not available in the on-chip store which teaches a geometry pipeline in the GPU is in an out-of-memory state under broadest reasonable interpretation. The on-chip store 110 is part of the geometry pipeline as seen in Figure 1); in response to determining that the geometry pipeline is in an out-of-memory state, determining not to allocate the region of the on-chip store (Paragraph 35 teaches allocating space to the COV buffer which is off-chip instead of the on-chip second storage device 110 when the overflow condition is met. The second storage device 110 is taught to be an on-chip cache or on-chip store. This teaches determining to not allocate the region of the on-chip store to the geometry task).
Goudie and Zhao are considered analogous to the claimed invention as because both are in the same field of allocating and storing data for graphic processing tasks. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the method of allocating memory for a geometry task taught by Goudie with the determining the available space in the on-chip store taught by Zhao in order to reduce memory traffic of an off-chip memory (Zhao Paragraph 55).
134. Regarding claim 8, Goudie in view of Zhao teaches the limitations of claim 1. However, Goudie is not relied upon for the below claim language: the method further comprising: in response to receiving, at the on-chip store, a memory read request for the geometry data for the geometry task from a geometry pipeline in the GPU, determining, by the on-chip store, whether a region of the on-chip store was allocated to the geometry task; in response to determining that a region of the on-chip store was allocated, directing the read request to the on-chip store; and in response to determining that a region of the on-chip store was not allocated, directing the read request to the off-chip storage.
Zhao teaches the method further comprising: in response to receiving, at the on-chip store, a memory read request for the geometry data for the geometry task from a geometry pipeline in the GPU, determining, by the on-chip store, whether a region of the on-chip store was allocated to the geometry task; in response to determining that a region of the on-chip store was allocated, directing the read request to the on-chip store (Paragraph 43 teaches sending a read request for a vertex attribute shading results. It teaches sending the read request to the on-chip cache. If a cache hit occurs, "a cache hit occurs, the requested vertex attribute shading result of the specific vertex can be read from the on-chip cache 802". This teaches receiving at the cache a read request and determining whether a region of the on-chip store was allocated through a cache hit or miss. If there was a cache hit, then it is determined that a region of the on-chip store was allocated and the read request is directed to the on-chip store.);
and in response to determining that a region of the on-chip store was not allocated, directing the read request to the off-chip storage (Paragraph 43 also teaches when "a cache miss occurs, the request vertex attribute shading result of the specific vertex is not available in the on-chip cache 802, and memory traffic of the bin memory 300 is needed to obtain the request vertex attribute shading result of the specific vertex". This teaches receiving at the cache a read request for the geometry data for the geometry task from a geometry pipeline and determining that the region of the on-chip store was not allocated in the on-chip store and the read request is directed to off-chip storage which is the bin memory. Paragraph 35 teaches the overflow COV buffer is "allocated in the off-chip bin memory" which teaches an off-chip storage).
Goudie and Zhao are considered analogous to the claimed invention as because both are in the same field of allocating and storing data for graphic processing tasks. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the method of allocating memory for a geometry task taught by Goudie with directing read requests on-chip or off-chip taught by Zhao in order to reduce memory traffic of an off-chip memory (Zhao Paragraph 55).
14. Regarding claim 14, Goudie teaches a graphics processing unit (GPU) (Paragraph 96 teaches a GPU can run the method taught by Goudie), comprising: a resource scheduler (Paragraph 94 teaches a processor executes the tasks and methods described in Goudie. Thus, the processor allocating a block of memory in Figure 3 step 302 teaches a resource scheduler); a shader core (Paragraph 2 teaches a shader program is executed and Paragraph 96 teaches a GPU and processor to execute the instructions. This teaches the GPU has a processor to execute the shader program and can be considered a shader core); a geometry pipeline (Figure 2 teaches processing logic 210 which executes shader programs. This can be considered to teach a geometry pipeline since shader tasks are considered geometry tasks per the Applicant’s description of geometry tasks in the Applicant’s specification Paragraph 29); and an on-chip store (Paragraph 46 teaches on-chip memory resources that can store intermediate data from the geometry tasks);
wherein the resource scheduler is arranged to allocate a region of off-chip storage to a geometry task on creation of the geometry task (Paragraph 63 teaches a task can implement a shader program. This teaches a geometry task; Paragraph 64 and Figure 3 step 302 teaches allocating a block of memory in off-chip memory for a primary task. The primary task is a geometry task as taught in Paragraph 63. This teaches allocating a region of off-chip storage on creation of the geometry task since the task has not been executed yet; Paragraph 94 teaches a processor executes the tasks and methods described in Goudie. Thus, the processor allocating a block of memory in Figure 3 step 302 teaches a resource scheduler),
and wherein the on-chip store is arranged, in response to receiving a memory allocation request for the geometry task from the shader core in the GPU, to determine whether to allocate a region of the on-chip store to the geometry task (Paragraph 46 teaches "it may be possible to store the intermediate data in on-chip resources …. The amount of this on-chip resource may need to be greater than that which is normally implemented." It also teaches that if the on-chip storage capability is insufficient, then "the intermediate data will tend to be stored in off-chip memory." This teaches determining whether to allocate a region of the on-chip store to the geometry task's intermediate data or whether to allocate it off-chip) (Paragraph 46 teaches determining whether to allocate a region of on-chip store to the geometry task’s intermediate data. Thus, the memory allocation request is received after generation of the geometry data of the geometry task).
However, Goudie is not relied upon for the below claim language: in response to determining to allocate the region of the on-chip store to the geometry task, to allocate the region, wherein in response to allocating the region of the on-chip store, geometry data for the geometry task is written to the on- chip store and in response to determining not to allocate the region of the on-chip store, the geometry data is written to the allocated region of off-chip storage.
Zhao teaches wherein the on-chip store is arranged, in response to receiving a memory allocation request for the geometry task from the shader core in the GPU, to determine whether to allocate a region of the on-chip store to the geometry task (Paragraph 35 teaches "The vertex attribute shading results of in-tile vertices are not kept in the VVB 306, but may be kept in the second storage device 110 (if the overflow condition is not met) or the COV buffer 310 (if the overflow condition is met)". This teaches determining by the on-chip store whether to allocate a region of the on-chip store to the geometry task based on the overflow condition)
and in response to determining to allocate the region of the on-chip store to the geometry task, to allocate the region, wherein in response to allocating the region of the on-chip store, geometry data for the geometry task is written to the on- chip store (Paragraph 35 teaches "the vertex attribute shading results of in-tile vertices are not kept in the VVB 306, but may be kept in the second storage device 110 (if the overflow condition is not met)". This teaches determining to allocating and storing the results of vertex attribute shading to a region of the on-chip store 110. Storing the results teaches writing the geometry data for the geometry task to the on-chip store. Paragraph 35 also teaches the second storage device 110 is an on-chip cache)
and in response to determining not to allocate the region of the on-chip store, the geometry data is written to the allocated region of off-chip storage (Paragraph 35 teaches "the COV buffer 310 … is a fixed-size buffer … and is used to buffer varying data (i.e. vertex attribute shading results) of in-tile vertices generated from the vertex attribute shader 114 when an overflow condition of the second storage device 110 is met." It also teaches that the second storage device 110 "the second storage device 110 may be implemented using an on-chip cache" and that the "COV buffer 310 is allocated in the off-chip bin memory". Thus, the second storage device teaches the on-chip store and the COV buffer teaches the off-chip storage. This teaches determining not to allocate the region of the on-chip store to the geometry data when the on-chip store is in overflow and writing it to off-chip storage instead).
Goudie and Zhao are considered analogous to the claimed invention as because both are in the same field of allocating and storing data for graphic processing tasks. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the graphics processing unit with the method of allocating memory for a geometry task taught by Goudie with allocating memory on-chip or off-chip for a geometry task taught by Zhao in order to reduce memory traffic of an off-chip memory (Zhao Paragraph 55).
156. Regarding claim 15, Goudie in view of Zhao teaches the limitations of claim 14. However, Goudie is not relied upon for the below claim language: the graphics processing unit wherein the on-chip store is further arranged, in response to allocating the region of the on-chip store, to direct a subsequent write instruction for the geometry task received at the on-chip store to the allocated region; and in response to determining not to allocate the region of the on-chip store, to direct a subsequent write instruction for the geometry task received at the on-chip store to the allocated region of the off-chip storage.
Zhao teaches the graphics processing unit wherein the on-chip store is further arranged, in response to allocating the region of the on-chip store, to direct a subsequent write instruction for the geometry task received at the on-chip store to the allocated region; and in response to determining not to allocate the region of the on-chip store, to direct a subsequent write instruction for the geometry task received at the on-chip store to the allocated region of the off-chip storage (Paragraph 35 teaches "The vertex attribute shading results of in-tile vertices are not kept in the VVB 306, but may be kept in the second storage device 110 (if the overflow condition is not met) or the COV buffer 310 (if the overflow condition is met). In other words, the priority of writing vertex attribute shading results of in-tile vertices into the on-chip cache is higher than the priority of writing vertex attribute shading results of in-tile vertices into a fixed-size buffer allocated in an off-chip bin memory." The writing results for a geometry task being kept in the second storage device 110 if the overflow condition is not met teaches allocating and directing a subsequent write instruction for the geometry task to the second storage device 110, or on-chip store, to the allocated region. On the other hand, if the overflow condition is met, Zhao teaches determining not to allocate the region of the on-chip store and directing the subsequent write instruction to the allocated region of the off-chip storage, the COV buffer).
Goudie and Zhao are considered analogous to the claimed invention as because both are in the same field of allocating and storing data for graphic processing tasks. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the graphics unit processing unit with the method of allocating memory for a geometry task taught by Goudie with the determining to direct writes of the geometry data for a geometry task on the on-chip store or off-chip storage taught by Zhao in order to reduce memory traffic of an off-chip memory (Zhao Paragraph 55).
16. Regarding claim 19, Goudie teaches a non-transitory computer readable storage medium having stored thereon computer readable code (Paragraph 32 teaches a non-transitory computer readable storage medium with computer readable instructions to execute the method) configured to cause the method as set forth in claim 1 to be performed when the code is run (See claim 1 rejection above).
17. Regarding claim 20, Goudie teaches a non-transitory computer readable storage medium having stored thereon an integrated circuit definition dataset that, when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture a graphics processing unit (Paragraphs 30-31 teach a non-transitory computer readable storage medium having stored thereon the description of a ray tracing system or integrated circuit definition dataset that “when processed in an integrated circuit manufacturing system, causes the integrated circuit manufacturing system to manufacture an integrated circuit embodying a ray tracing system”; Paragraph 94 and 96 teach the ray tracing system implemented on an integrated circuit can have its tasks executed by a processor which can be a GPU) as set forth in claim 14 (See Claim 14 rejection above).
18. Claim(s) 3-4 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goudie (U.S. Patent Application Publication No. 2022/0114013 A1) in view of Zhao et al. (U.S. Patent Application Publication No. 2016/0035128 A1), hereinafter referred to as Zhao, as applied to claim 1 and 15 above, and further in view of Ray et al. (U.S. Patent Application Publication No. 2022/0309731 A1), hereinafter referred to as Ray, and Wienand (“Computer Science from the Bottom Up” - https://web.archive.org/web/20231216205710/https://www.bottomupcs.com/csbu.pdf).
19. Regarding claim 3, Goudie in view of Zhao teaches the limitations of claim 1. However, Goudie and Zhao are not relied upon for the below claim language: the method further comprising: calculating an on-chip storage address for the geometry task; and in response to determining not to allocate the region of the on-chip store, calculating an updated storage address by adding an offset to the calculated address, wherein the on-chip storage address is used when directing a subsequent write to the on-chip store and the updated storage address is used when directing a subsequent write to the off-chip storage.
Ray teaches the method further comprising: calculating an on-chip storage address for the geometry task; and in response to determining not to allocate the region of the on-chip store, calculating an updated storage address (Paragraph 195 teaches "upon receiving a request for data stored in the tile cache 2012, the tile cache allocation module 2002 may determine whether the requested data is in the tile cache 2012 or in the tile cache region 2041 in system memory 2040. If in system memory 2040, it may perform a virtual to physical address translation to locate the physical address in system memory 2040 (or hand off the memory request to the memory controller)" The tile cache 2012 teaches the on-chip store and the tile cache memory region 2041 teaches the off-chip storage. A request sent to the on-chip store teaches an address for the geometry task being calculated in order to send the request for the data. This teaches using the calculated on-chip storage address for the request when the data is stored in the tile cache and using an updated calculated address through the translation to access the off-chip storage. Paragraph 306 teaches the GPU attached memories can have writes. Thus, the request sent to the tile cache can be a subsequent write and uses either the calculated on-chip storage address or updated storage address depending on where the data is located).
Goudie, Zhao, and Ray are considered analogous to the claimed invention as because both are in the same field of allocating memory for a graphics processing task. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the method of allocating memory for geometry tasks taught by Goudie in view of Zhao with calculating an updated address taught by Ray in order to implement the spill-over memory process transparently to the end user (Ray Paragraph 195) and enable an efficient execution environment (Ray Paragraph 79).
However, Goudie, Zhao, and Ray are not relied upon for the below claim language: calculating an updated storage address by adding an offset to the calculated address.
Wienand teaches calculating an updated storage address by adding an offset to the calculated address (Pages 159-161, Section 6.3 teaches using an offset during address translation to get the updated storage address which points to an address in system memory).
Goudie, Zhao, and Ray are considered analogous to the claimed invention as because all are in the same field of allocating memory for a graphics processing task. Wienand is considered analogous to the claimed invention as because both are in the same field of memory allocation for a program. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the method of allocating memory for a geometry task taught by Goudie in view of Zhao and Ray with the offset calculation taught by Wienand in order to allow the program to not need to care where the actual physical memory is and have the operating system and hardware work together to locate the right address instead (Wienand Page 159, Section 6 Paragraph 1).
20. Regarding claim 4, Goudie in view of Zhao, Ray, and Wienand teach the limitations of claim 3. However, Goudie and Zhao are not relied upon for the below claim language: the method further comprising: calculating an on-chip storage address for the geometry task; and in response to determining not to allocate the region of the on-chip store, tagging the address with a first value; and
in response to determining to allocate the region of the on-chip store, tagging the address with a second value; wherein the value of the tag is used to determine whether to direct a subsequent write to the on- chip store or to the off-chip storage.
Ray teaches the method further comprising: calculating an on-chip storage address for the geometry task (Paragraph 195 teaches "upon receiving a request for data stored in the tile cache 2012, the tile cache allocation module 2002 may determine whether the requested data is in the tile cache 2012 or in the tile cache region 2041 in system memory 2040. If in system memory 2040, it may perform a virtual to physical address translation to locate the physical address in system memory 2040 (or hand off the memory request to the memory controller)". The tile cache 2012 teaches the on-chip store and the tile cache memory region 2041 teaches the off-chip storage. A request sent to the on-chip store teaches an address for the geometry task being calculated in order to send the request for the data. This teaches using the calculated address for the request when the data is stored in the tile cache);
Goudie, Zhao, and Ray are considered analogous to the claimed invention as because both are in the same field of allocating memory for a graphics processing task. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the method of allocating memory for geometry tasks taught by Goudie in view of Zhao with calculating an address taught by Ray in order to implement the spill-over memory process transparently to the end user (Ray Paragraph 195) and enable an efficient execution environment (Ray Paragraph 79).
However, Goudie, Zhao, and Ray are not relied upon for the below claim language: in response to determining not to allocate the region of the on-chip store, tagging the address with a first value; and in response to determining to allocate the region of the on-chip store, tagging the address with a second value; wherein the value of the tag is used to determine whether to direct a subsequent write to the on- chip store or to the off-chip storage.
Wienand teaches in response to determining not to allocate the region of the on-chip store, tagging the address with a first value; and in response to determining to allocate the region of the on-chip store, tagging the address with a second value (Pages 72-78, Section 2.1 teaches an on-chip memory the cache and an off-chip memory the RAM and disk. Section 2.2.1 teaches cache tags which are an address tag that is compared to a cache. A hit teaches that the tag matches an entry in the cache and that the address was tagged with a second value, meaning it was on-chip or in the on-core cache. A miss teaches the tag does not match an entry in the tag and that the address was tagged with a first value, meaning it is off-chip or off-core);
wherein the value of the tag is used to determine whether to direct a subsequent write to the on- chip store or to the off-chip storage (Pages 72-78, Section 2.2.1 teaches if the request can go to the cache, on-chip memory, or if it must go to off-chip storage).
Goudie, Zhao, and Ray are considered analogous to the claimed invention as because all are in the same field of allocating memory for a graphics processing task. Wienand is considered analogous to the claimed invention as because both are in the same field of memory allocation for a program. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the method of allocating memory for a geometry task taught by Goudie in view of Zhao and Ray with the offset calculation taught by Wienand in order to allow the program to not need to care where the actual physical memory is and have the operating system and hardware work together to locate the right address instead (Wienand Page 159, Section 6 Paragraph 1).
21. Regarding claim 16, Goudie in view of Zhao teaches the limitations of claim 15. However, Goudie and Zhao are not relied upon for the below claim language: the graphics processing unit wherein the on-chip store is further arranged to: calculate an on-chip storage address for the geometry task; and in response to determining not to allocate the region of the on-chip store, calculate an updated storage address by adding an offset to the calculated address, wherein the on-chip storage address is used when directing a subsequent write to the on-chip store and the updated storage address is used when directing a subsequent write to the off-chip storage.
Ray teaches the graphics processing unit wherein the on-chip store is further arranged to: calculate an on-chip storage address for the geometry task; and in response to determining not to allocate the region of the on-chip store, calculate an updated storage address (Paragraph 195 teaches "upon receiving a request for data stored in the tile cache 2012, the tile cache allocation module 2002 may determine whether the requested data is in the tile cache 2012 or in the tile cache region 2041 in system memory 2040. If in system memory 2040, it may perform a virtual to physical address translation to locate the physical address in system memory 2040 (or hand off the memory request to the memory controller)" The tile cache 2012 teaches the on-chip store and the tile cache memory region 2041 teaches the off-chip storage. A request sent to the on-chip store teaches an address for the geometry task being calculated in order to send the request for the data. This teaches using the calculated on-chip storage address for the request when the data is stored in the tile cache and using an updated calculated address through the translation to access the off-chip storage. Paragraph 306 teaches the GPU attached memories can have writes. Thus, the request sent to the tile cache can be a subsequent write and uses either the calculated on-chip storage address or updated storage address depending on where the data is located).
Goudie, Zhao, and Ray are considered analogous to the claimed invention as because both are in the same field of allocating memory for a graphics processing task. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the graphics processing unit with the method of allocating memory for geometry tasks taught by Goudie in view of Zhao with calculating an updated address taught by Ray in order to implement the spill-over memory process transparently to the end user (Ray Paragraph 195) and enable an efficient execution environment (Ray Paragraph 79).
However, Goudie, Zhao, and Ray are not relied upon for the below claim language: calculating an updated storage address by adding an offset to the calculated address.
Wienand teaches calculating an updated storage address by adding an offset to the calculated address (Pages 159-161, Section 6.3 teaches using an offset during address translation to get the updated storage address which points to an address in system memory).
Goudie, Zhao, and Ray are considered analogous to the claimed invention as because all are in the same field of allocating memory for a graphics processing task. Wienand is considered analogous to the claimed invention as because both are in the same field of memory allocation for a program. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the graphics processing unit with the method of allocating memory for a geometry task taught by Goudie in view of Zhao and Ray with the offset calculation taught by Wienand in order to allow the program to not need to care where the actual physical memory is and have the operating system and hardware work together to locate the right address instead (Wienand Page 159, Section 6 Paragraph 1).
22. Claim(s) 7, 11, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goudie (U.S. Patent Application Publication No. 2022/0114013 A1) in view of Zhao et al. (U.S. Patent Application Publication No. 2016/0035128 A1), hereinafter referred to as Zhao, as applied to claim 1 and 14 above, and further in view of Livesley et al. (UK Patent Application Publication No. 2605665 A), hereinafter referred to as Livesley.
23. Regarding claim 7, Goudie in view of Zhao teaches the limitations of claim 1. Goudie further teaches proceeding to determine whether to allocate a region of the on-chip store to the geometry task (Paragraph 46 teaches "it may be possible to store the intermediate data in on-chip resources …. The amount of this on-chip resource may need to be greater than that which is normally implemented." This teaches that if there is enough space, the geometry data for the geometry task can be allocated and written to the on-chip store. Else if the on-chip storage capability is insufficient, then "the intermediate data will tend to be stored in off-chip memory." This teaches determining whether to allocate a region of the on-chip store to the geometry task).
However, Goudie and Zhao are not relied upon for the below claim language: the method further comprising: on creation of the geometry task, sending an identifier for the geometry task to the on-chip store and adding the identifier to a FIFO in the on-chip store; and in response to receiving the memory allocation request at the on-chip store and prior to determining, by the on-chip store, whether to allocate a region of the on-chip store to the geometry task: setting a bit in a mask corresponding to the identifier for the geometry task, wherein the memory allocation request comprises the identifier for the geometry task; determining whether the identifier for the geometry task is in a first position in the FIFO; and in response to determining that the identifier for the geometry task is in a first position in the FIFO, popping the task from the FIFO.
Livesley teaches the method further comprising: on creation of the geometry task, sending an identifier for the geometry task to the on-chip store and adding the identifier to a FIFO in the on-chip store (Page 1 line 29-Page 2 line 7 teaches the “processor comprises a register bank to which the software can write a descriptor of a task”. The descriptor of a task teaches the identifier for the geometry task. Thus, this teaches sending the identifier for the geometry task to an on-chip store which is the register bank; Page 28, lines 1-11 teach a register bank that holds the descriptors of at least two tasks and the register bank is implemented as a "buffer-type structure such as a circular buffer for queueing task descriptors". This teaches that descriptors of a geometry task are stored in a queue which is a FIFO; Page 37, lines 7-22 teach jobs can be queued up which teaches entering tasks into a queue or FIFO);
and in response to receiving the memory allocation request at the on-chip store and prior to determining, by the on-chip store, whether to allocate a region of the on-chip store to the geometry task (Page 2 lines 9-21 teach a task is executed through the geometry and fragment pipeline only after a kick flag is set. The kick flag “triggers the hardware pipeline to start processing the task based on the descriptor found in the register bank”. Page 2 line 23-Page 3 line 14 teach when geometry and fragment processing for a task occurs, the memory management circuit allocates pages of memory to write the tile data or geometry data. Thus, the process to set the kick flag or mask signals explained below in Page 36 line 19 – Page 37 line 5 occur prior to determining whether to allocate any memory to the geometry task):
setting a bit in a mask corresponding to the identifier for the geometry task, wherein the memory allocation request comprises the identifier for the geometry task (Page 36 line 19 – Page 37 line 5 teach that “each mask signal indicates which task is currently active … or more precisely, from which of the task register sets 309a, 390b the pipeline section is currently processing a task”. This teaches mask signals whose bits correspond to the identifier for the geometry task since they decide which task will be processed);
determining whether the identifier for the geometry task is in a first position in the FIFO (Figure 8 and Page 37 lines 7-22 teach the mask 01 determines the first geometry task is issued and active. The task issued is the task in the first position. If the task is not issued, then the task is in the second position. This teaches determining whether the identifier for the geometry task is in a first or second position.);
and in response to determining that the identifier for the geometry task is in a first position in the FIFO, popping the task from the FIFO (Page 30 line 25-Page 31 line 4 teach the first task is processed through the pipeline. This corresponds to the mask signal value of 01 as taught in Page 37 lines 7-22. The task processed through the pipeline teaches the identifier for the geometry task was in the first position in the FIFO and has been popped from the FIFO to be executed through the pipeline; Page 2 line 32 – Page 3 line 14 teaches when a task is going through the pipeline, a memory management circuit allocates pages of memory for the task).
Goudie, Zhao, and Livesley are considered analogous to the claimed invention as because both are in the same field of memory allocation to geometry tasks. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the method of allocating memory for a geometry task taught by Goudie in view of Zhao with the geometry tasks in a FIFO taught by Livesley in order to create performance improvements like reduced latency, increased throughput, and reduced power consumption (Livesley Page 56 line 32 – Page 57 line 14).
24. Regarding claim 11, Goudie in view of Zhao teaches the limitations of claim 1. However, Goudie and Zhao are not relied upon for the below claim language: the method further comprising: in response to completion of the geometry task, freeing the allocated region of off-chip storage and any allocated region of the on-chip store.
Livesley teaches the method further comprising: in response to completion of the geometry task, freeing the allocated region of off-chip storage and any allocated region of the on-chip store (Abstract teaches “once the fragment processing logic has finished processing the tile data of a subdivision, it sends an identifier of that subdivision to the memory manager for deallocation. This teaches freeing the region wherever it is stored, on-chip or off-chip, at the completion of a task. Goudie and Zhao teach on-chip and off-chip memory regions so combined with Livesley, they teach freeing regions off-chip and on-chip at the completion of a task; Page 45 lines 1-17 teach deallocating memory pages or regions when no longer needed. This teaches freeing regions in memory).
Zhao, Goudie, and Livesley are considered analogous to the claimed invention as because both are in the same field of memory allocation to geometry tasks. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the method of allocating memory for a geometry task taught by Goudie in view of Zhao with the freeing of allocated space taught by Livesley in order to create performance improvements like reduced latency, increased throughput, and reduced power consumption (Livesley Page 56 line 32 – Page 57 line 14).
25. Regarding claim 17, Goudie in view of Zhao teaches the limitations for claim 14. Goudie further teaches proceed to determine whether to allocate a region of the on-chip store to the geometry task (Paragraph 46 teaches "it may be possible to store the intermediate data in on-chip resources …. The amount of this on-chip resource may need to be greater than that which is normally implemented." This teaches that if there is enough space, the geometry data for the geometry task can be allocated and written to the on-chip store. Else if the on-chip storage capability is insufficient, then "the intermediate data will tend to be stored in off-chip memory." This teaches determining whether to allocate a region of the on-chip store to the geometry task).
However, Goudie and Zhao are not relied upon for the below claim language: the graphics processing unit wherein the resource scheduler is further arranged, on creation of the geometry task, to send an identifier for the geometry task to the on-chip store, and wherein the on-chip store is further arranged to: adding the identifier to a FIFO in the on-chip store; and in response to receiving the memory allocation request and prior to determining whether to allocate a region of the on-chip store to the geometry task: set a bit in a mask corresponding to the identifier for the geometry task, wherein the memory allocation request comprises the identifier for the geometry task, determine whether the identifier for the geometry task is in a first position in the FIFO, and in response to determining that the identifier for the geometry task is in a first position in the FIFO, pop the task from the FIFO and proceed to determine whether to allocate a region of the on-chip store to the geometry task.
Livesley teaches the graphics processing unit wherein the resource scheduler is further arranged, on creation of the geometry task, to send an identifier for the geometry task to the on-chip store, and wherein the on-chip store is further arranged to: adding the identifier to a FIFO in the on-chip store (Page 1 line 29-Page 2 line 7 teaches the “processor comprises a register bank to which the software can write a descriptor of a task”. The descriptor of a task teaches the identifier for the geometry task. Thus, this teaches sending the identifier for the geometry task to an on-chip store which is the register bank; Page 28, lines 1-11 teach a register bank that holds the descriptors of at least two tasks and the register bank is implemented as a "buffer-type structure such as a circular buffer for queueing task descriptors". This teaches that descriptors of a geometry task are stored in a queue which is a FIFO; Page 37, lines 7-22 teach jobs can be queued up which teaches entering tasks into a queue or FIFO);
and in response to receiving the memory allocation request and prior to determining whether to allocate a region of the on-chip store to the geometry task (Page 2 lines 9-21 teach a task is executed through the geometry and fragment pipeline only after a kick flag is set. The kick flag “triggers the hardware pipeline to start processing the task based on the descriptor found in the register bank”. Page 2 line 23-Page 3 line 14 teach when geometry and fragment processing for a task occurs, the memory management circuit allocates pages of memory to write the tile data or geometry data. Thus, the process to set the kick flag or mask signals explained below in Page 36 line 19 – Page 37 line 5 occur prior to determining whether to allocate any memory to the geometry task):
set a bit in a mask corresponding to the identifier for the geometry task, wherein the memory allocation request comprises the identifier for the geometry task (Page 36 line 19 – Page 37 line 5 teach that “each mask signal indicates which task is currently active … or more precisely, from which of the task register sets 309a, 390b the pipeline section is currently processing a task”. This teaches mask signals whose bits correspond to the identifier for the geometry task since they decide which task will be processed),
determine whether the identifier for the geometry task is in a first position in the FIFO (Figure 8 and Page 37 lines 7-22 teach the mask 01 determines the first geometry task is issued and active. The task issued is the task in the first position. If the task is not issued, then the task is in the second position. This teaches determining whether the identifier for the geometry task is in a first or second position.),
and in response to determining that the identifier for the geometry task is in a first position in the FIFO, pop the task from the FIFO (Page 30 line 25-Page 31 line 4 teach the first task is processed through the pipeline. This corresponds to the mask signal value of 01 as taught in Page 37 lines 7-22. The task processed through the pipeline teaches the identifier for the geometry task was in the first position in the FIFO and has been popped from the FIFO to be executed through the pipeline; Page 2 line 32 – Page 3 line 14 teaches when a task is going through the pipeline, a memory management circuit allocates pages of memory for the task).
Goudie, Zhao, and Livesley are considered analogous to the claimed invention as because both are in the same field of memory allocation to geometry tasks. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the graphics processing unit with the method of allocating memory for a geometry task taught by Goudie in view of Zhao with the geometry tasks in a FIFO taught by Livesley in order to create performance improvements like reduced latency, increased throughput, and reduced power consumption (Livesley Page 56 line 32 – Page 57 line 14).
26. Claim(s) 9 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goudie (U.S. Patent Application Publication No. 2022/0114013 A1) in view of Zhao et al. (U.S. Patent Application Publication No. 2016/0035128 A1), hereinafter referred to as Zhao, as applied to claim 1 and 14 above, and further in view of Greicar et al. (U.S. Patent Application Publication No. 2004/0117582 A1), hereinafter referred to as Greicar.
27. Regarding claim 9, Goudie in view of Zhao teaches the limitations of claim 1. Goudie further teaches the method further comprising, in response to the GPU exiting an out-of-memory state: identifying a previously received memory allocation request for a geometry task where the geometry data for the geometry task was previously written to the off-chip storage (Paragraph 46 teaches if the on-chip storage capability is insufficient, then "the intermediate data will tend to be stored in off-chip memory." Insufficient memory can be considered to teach an out-of-memory state under broadest reasonable interpretation. This teaches determining not to allocate the region of the on-chip store and to write or store the geometry data to the off-chip storage instead. Knowing where the intermediate data is stored teaches identifying a previously received memory allocation request for a geometry task where the geometry data was written to off-chip storage);
However, Goudie and Zhao are not relied upon for the below claim language: determining whether space for the previously written geometry data is available in the on- chip store; and in response to determining that space is available, loading the geometry data from the off- chip store into the on-chip store.
Greicar teaches determining whether space for the previously written geometry data is available in the on- chip store; and in response to determining that space is available, loading the geometry data from the off- chip store into the on-chip store (Paragraph 25 teaches when a slot of local memory becomes available, the data transfer routine can be called to "transfer another block of code or data from external memory to the available slot in local memory". This teaches determining space is available on the on-chip store and loading data from the off-chip store to the on-chip store. Combined with Goudie and Zhao which teach the data are geometry data stored in memory, Goudie and Zhao in view of Greicar teach loading geometry data from the off-chip store into the on-chip store).
Goudie, Zhao, and Greicar are considered analogous to the claimed invention as because both are in the same field of managing memory for programs. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the method of allocating memory for a geometry task taught by Goudie in view of Zhao with loading data from an off-chip store to an on-chip store taught by Greicar in order to improve access times since the access time to local or on-chip stores is significantly faster (Greicar Paragraph 16).
28. Regarding claim 18, Goudie in view of Zhao teaches the limitations of claim 14. Goudie further teaches the graphics processing unit wherein the on-chip store is further arranged, in response to the GPU exiting an out-of-memory state, to: identify a previously received memory allocation request for a geometry task where the geometry data for the geometry task was previously written to the off-chip storage (Paragraph 46 teaches if the on-chip storage capability is insufficient, then "the intermediate data will tend to be stored in off-chip memory." Insufficient memory can be considered to teach an out-of-memory state under broadest reasonable interpretation. This teaches determining not to allocate the region of the on-chip store and to write or store the geometry data to the off-chip storage instead. Knowing where the intermediate data is stored teaches identifying a previously received memory allocation request for a geometry task where the geometry data was written to off-chip storage);
However, Goudie and Zhao are not relied upon for the below claim language: determining whether space for the previously written geometry data is available in the on- chip store; and in response to determining that space is available, load the geometry data from the off-chip store into the on-chip store.
Greicar teaches determining whether space for the previously written geometry data is available in the on- chip store; and in response to determining that space is available, loading the geometry data from the off- chip store into the on-chip store (Paragraph 25 teaches when a slot of local memory becomes available, the data transfer routine can be called to "transfer another block of code or data from external memory to the available slot in local memory". This teaches determining space is available on the on-chip store and loading data from the off-chip store to the on-chip store. Combined with Goudie and Zhao which teach the data are geometry data stored in memory, Goudie and Zhao in view of Greicar teach loading geometry data from the off-chip store into the on-chip store).
Goudie, Zhao, and Greicar are considered analogous to the claimed invention as because both are in the same field of managing memory for programs. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the graphics processing unit with the method of allocating memory for a geometry task taught by Goudie in view of Zhao with loading data from an off-chip store to an on-chip store taught by Greicar in order to improve access times since the access time to local or on-chip stores is significantly faster (Greicar Paragraph 16).
29. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goudie (U.S. Patent Application Publication No. 2022/0114013 A1) in view of Zhao et al. (U.S. Patent Application Publication No. 2016/0035128 A1), hereinafter referred to as Zhao, as applied to claim 1 above, and further in view of Zhang et al. (Chinese Patent Application Publication No. 101158927 A), hereinafter referred to as Zhang.
Regarding claim 10, Goudie in view of Zhao teaches the limitations of claim 1. However, Goudie is not relied upon for the below claim language: the method further comprising: in response to allocating the region of the on-chip store, sending a message to the shader core to indicate a successful allocation; and in response to determining not to allocate the region of the on-chip store, sending a message to the shader core to indicate allocation failure, wherein the message indicating a successful allocation causes the shader core to write the geometry data for the geometry task to the on-chip store and the message indicating allocation failure causes the shader core to write the geometry data to the allocated region of off-chip storage.
Zhao teaches the message indicating allocation failure causes the shader core to write the geometry data to the allocated region of off-chip storage (Paragraph 35 teaches "The vertex attribute shading results of in-tile vertices are not kept in the VVB 306, but may be kept in the second storage device 110 (if the overflow condition is not met) or the COV buffer 310 (if the overflow condition is met). In other words, the priority of writing vertex attribute shading results of in-tile vertices into the on-chip cache is higher than the priority of writing vertex attribute shading results of in-tile vertices into a fixed-size buffer allocated in an off-chip bin memory." The overflow condition can be considered an allocation failure message requiring to write to the COV buffer).
Goudie and Zhao are considered analogous to the claimed invention as because both are in the same field of allocating and storing data for graphic processing tasks. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the method of allocating memory for a geometry task taught by Goudie with the allocation failure causing the geometry data to be written to the allocated off-chip storage taught by Zhao in order to store and buffer any geometry data that cannot be stored in the on-chip store (Zhao Paragraph 35).
However, Goudie and Zhao are not relied upon for the below claim language: the method further comprising: in response to allocating the region of the on-chip store, sending a message to the shader core to indicate a successful allocation; and in response to determining not to allocate the region of the on-chip store, sending a message to the shader core to indicate allocation failure, wherein the message indicating a successful allocation causes the shader core to write the geometry data for the geometry task to the on-chip store.
Zhang teaches the method further comprising: in response to allocating the region of the on-chip store, sending a message to the shader core to indicate a successful allocation; and in response to determining not to allocate the region of the on-chip store, sending a message to the shader core to indicate allocation failure (Paragraph 0123 teaches "If the allocation is successful, send a message of successful allocation to node j and inform it of the starting address and size of the allocated memory; if the allocation fails, send a message of allocation failure to node j". This teaches sending a message of success when allocation of on-chip store is successful and a message of failure with the allocation of on-chip store has failed),
wherein the message indicating a successful allocation causes the shader core to write the geometry data for the geometry task to the on-chip store (Paragraph 0123 teaches "If the allocation is successful, send a message of successful allocation to node j and inform it of the starting address and size of the allocated memory". This teaches writing to local or on-chip memory).
Goudie, Zhao, and Zhang are considered analogous to the claimed invention as because both are in the same field of allocating memory for programs. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the method of allocating memory for a geometry task taught by Goudie in view of Zhao with the message indicating a successful or failed allocation taught by Zhang in order to inform the task of the location of the allocated memory (Zheng Paragraph 0123).
30. Claim(s) 12 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Goudie (U.S. Patent Application Publication No. 2022/0114013 A1) in view of Zhao et al. (U.S. Patent Application Publication No. 2016/0035128 A1), hereinafter referred to as Zhao, and Livesley et al. (UK Patent Application Publication No. 2605665 A), hereinafter referred to as Livesley, as applied to claim 11 above, and further in view of Landers et al. (U.S. Patent Application Publication No. 2017/0286151 A1), hereinafter referred to as Landers.
31. Regarding claim 12, Goudie in view of Zhao and Livesley teaches the limitations of claim 11. Goudie further teaches the method wherein the allocated region of off-chip storage is identified by a geometry data spill identifier allocated to the task (P65 teaches tasks are given a task identifier that points to the allocated block of memory. This includes tasks that store their data on off-chip or on-chip memory as taught in Paragraph 46)
However, Goudie, Zhao, and Livesley are not relied upon for the below claim language: wherein the method further comprises: in response to completion of the geometry task, freeing the geometry data spill identifier.
Landers teaches wherein the method further comprises: in response to completion of the geometry task, freeing the geometry data spill identifier (Paragraph 32 teaches "Transaction IDs are freed up so that they can be re-used (i.e. assigned to another incoming memory request) once a transaction is complete." This teaches freeing an identifier at the completion of a task).
Goudie, Zhao, Livesley, and Landers are considered analogous to the claimed invention as because both are in the same field of memory allocation for tasks. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the method of allocating memory for a geometry task taught by Goudie in view of Zhao and Livesley with the freeing of an identifier taught by Landers in order to re-use the identifier for another request (Landers Paragraph 32).
32. Regarding claim 13, Goudie in view of Zhao, Livesley, and Landers teach the limitations of claim 12. However, Goudie, Zhao, and Livesley are not relied upon for the below claim language: the method wherein the geometry data spill identifier is allocated to the task on creation of the geometry task from a finite pool of geometry data spill identifiers.
Landers teaches the method wherein the geometry data spill identifier is allocated to the task on creation of the geometry task from a finite pool of geometry data spill identifiers (Paragraph 32 teaches transaction IDs are re-used and that there exists a set of transaction IDs used when assigning to certain memory requests. This teaches a finite pool of geometry data spill identifiers.).
Goudie, Zhao, Livesley, and Landers are considered analogous to the claimed invention as because both are in the same field of memory allocation for tasks. Thus, it would have been obvious to a person holding ordinary skill in the art before the effective filing date to modify the method of allocating memory for a geometry task taught by Goudie in view of Zhao and Livesley with the freeing of an identifier taught by Landers in order to maintain distinct IDs only for memory requests (Landers Paragraph 32).
Conclusion
33. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ray et al. (U.S. Patent Application Publication No. 2021/0125581 A1) teaches a shared local memory for spilling of registers associated with a graphics processor.
Howes et al. (U.S. Patent Application Publication No. 2017/0053374 A1) teaches managing register spill by moving data from registers into another memory unit.
34. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE Y AHN whose telephone number is (571)272-0672. The examiner can normally be reached M-F 9-5pm.
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/CHRISTINE YERA AHN/Examiner, Art Unit 2615
/ALICIA M HARRINGTON/Supervisory Patent Examiner, Art Unit 2615
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