DETAILED ACTION
Status of Application
Claims 1-20 are pending in the present application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/16/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 10, and 12-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chrysos et al (hereinafter Chrysos), US 20220100680 A1.
Referring to claims 1 and 12, taking claim 1 as exemplary, Chrysos discloses a system comprising:
a set of processing cores [paragraph 133, “A processor (e.g., having one or more cores) may execute instructions (e.g., a thread of instructions) to operate on data, for example, to perform arithmetic, logic, or other functions”];
a set of one or more memories, on the set of processing cores, storing computational instructions for component computations of a complex computation and storing data movement instructions for routing computation data for the complex computation [paragraphs 149, 155, “processor 200 (e.g., accelerator(s) and/or core(s) thereof) may be coupled to memory”; “control operators which assist in the management of dataflow tokens in the program graph”…”dataflow operators for complex operations”];
an interconnect fabric that networks the set of processing cores [paragraph 165, “configuration may load the state of a dataflow graph into the interconnect (and/or communications network (e.g., a network dataflow endpoint circuit thereof)) and processing elements (e.g., fabric), e.g., generally from memory”];
a set of computational pipelines on the set of processing cores [paragraphs 159, 165, “dataflow graph channels are implemented in a pipelined fashion”; “properties of a latency-insensitive dataflow architecture of an embodiment of a CSA to yield efficient, largely pipelined implementations of these functions”];
a set of core controllers on the set of processing cores to administrate an execution of the computational instructions by the set of computational pipelines [paragraphs 221, 230-231, “processing elements are organized as pipelines and support the injection of one pipelined dataflow operator per cycle. Processing elements may have a single-cycle latency. However, other pipelining choices may be used for other (e.g., more complicated) operations. For example, floating point operations may use multiple pipeline stages”; “Depicted processing element 1100 includes input controller 1101, input controller 1103, output controller 1105, and output controller 1107”; input controllers…output controllers];
a set of routers on the set of processing cores [paragraph 457, “embodiments herein provide circuitry to overlay high-radix dataflow operations on these networks for communications. For example, certain embodiments herein utilize the existing network for communications (e.g., interconnect network 104 described in reference to FIG. 1) to provide data routing capabilities between processing elements and other components of the spatial array, but also augment the network (e.g., network endpoints) to support the performance and/or control of some (e.g., less than all) of dataflow operations (e.g., without utilizing the processing elements to perform those dataflow operations)”];
a set of data movement processing cores on the set of processing cores [paragraphs 545, 0836, “flow 6800 includes decoding an instruction with a decoder of a core of a processor into a decoded instruction 6802; executing the decoded instruction with an execution unit of the core of the processor to perform a first operation 6804; receiving an input of a dataflow graph comprising a plurality of nodes 6806; overlaying the dataflow graph into a plurality of processing elements of the processor and an interconnect network between the plurality of processing elements of the processor with each node represented as a dataflow operator in the plurality of processing elements 6808; and performing a second operation of the dataflow graph with the interconnect network and the plurality of processing elements by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements 6810”]; and
a set of data movement core controllers, on the set of data movement processing cores, to administrate an execution of the data movement instructions and thereby generate commands for the set of routers to route the computation data through the interconnect fabric during an execution of the complex computation [paragraphs 211, 465, 527, 532, "In certain embodiments, the routing of data between components (e.g., PEs) is enabled by setting switches (e.g., multiplexers and/or demultiplexers) and/or logic gate circuits of a circuit switched network (e.g., a local network) to achieve a desired configuration, e.g., a configuration according to a dataflow graph”; “As one example, a pick dataflow operation may have a plurality of inputs and steer (e.g., route) one of them as an output, e.g., as in FIG. 42…Additionally or alternatively, the network dataflow endpoint circuits may route data between processing elements, e.g., for the processing elements to perform processing operations on the data. Embodiments herein may thus utilize to the communications network to perform (e.g., steering) dataflow operations. Additionally or alternatively, the network dataflow endpoint circuits may perform as a mezzanine network discussed below”; “dataflow instructions on the actual CSA hardware”].
Referring to claims 2 and 13, taking claim 2 as exemplary, Chrysos discloses the system of claim 1, wherein:
the data movement core controllers in the set of data movement core controllers each include a program counter and a decoder stage [paragraphs 149, 188, 533, “decoder (e.g., of core) may receive an (e.g., single) instruction (e.g., macro-instruction) and decode the instruction, e.g., into micro-instructions and/or micro-operations”; “PE is depicted which may support addition, subtraction, and various logic operations. Other kinds of PEs may be created by substituting different kinds of functional units into the PE”; “combined with a traditional RISC-like control-flow architecture (e.g., with branches and a program counter”]; and
the data movement processing cores in the set of data movement processing cores each include a functional processing unit [paragraphs 149, 188, 533, “PE is depicted which may support addition, subtraction, and various logic operations. Other kinds of PEs may be created by substituting different kinds of functional units into the PE”].
Referring to claims 3 and 14, taking claim 3 as exemplary, Chrysos discloses the system of claim 1, wherein:
the core controllers in the set of core controllers and the data movement core controllers in the set of data movement core controllers all use their own separate program counters [paragraphs 533, 569, 570, 692, 707, “dependency token counters 8814 (e.g., one per input queue), a set of dependency queues 8818 (e.g., one each per input queue)”; “input channels and output channels of the dependency queues are both implemented with counters”; “LCC operation may begin when it receives a pointer to a code segment. Depending on the LCB microarchitecture, this pointer (e.g., stored in pointer register 7206) may come either over a network (e.g., from within the CSA (fabric) itself) or through a memory system access to the LCC. When it receives such a pointer, the LCC optionally drains relevant state from its portion of the fabric for context storage, and then proceeds to immediately reconfigure the portion of the fabric for which it is responsible”; “LCCs is informed of the program to load, for example, by a set of (e.g., OS-visible) control-status-registers which will be used to inform individual LCCs of new program pointers, etc”].
Referring to claims 4 and 15, taking claim 4 as exemplary, Chrysos discloses the system of claim 1, wherein: the set of one or more memories includes a set of scratch pad memories; and the set of scratch pad memories store the computation data [paragraphs 594, 595, 652, “In-Fabric Storage (Scratchpad) Caching—In this mode the configuration cache receives a reference to a configuration sequence”; “LEC may make use of both a chip-level memory hierarchy and a fabric-level communications networks to move data from the fabric into storage”].
Referring to claim 10, Chrysos discloses the system of claim 1, wherein:
the set of data movement processing cores reformat the computation data during the execution of the complex computation and using conditional logic [paragraphs 539-540, “As a concrete example, consider the code and corresponding dataflow graph in FIGS. 66A-66C, which conditionally computes a value of y based on several inputs”].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chrysos et al (hereinafter Chrysos), US 20220100680 A1, in view of Wang et al (hereinafter Wang), US 20230325345 A1.
Referring to claim 19, Chrysos discloses a processing core comprising:
one or more memories storing computational instructions for component computations of a complex computation and data movement instructions for routing data for the complex computation [paragraphs 149, 155, “processor 200 (e.g., accelerator(s) and/or core(s) thereof) may be coupled to memory”; “control operators which assist in the management of dataflow tokens in the program graph”…”dataflow operators for complex operations”];
a computational pipeline [paragraphs 159, 165, “dataflow graph channels are implemented in a pipelined fashion”; “properties of a latency-insensitive dataflow architecture of an embodiment of a CSA to yield efficient, largely pipelined implementations of these functions”; fig. 3C, paragraph 156, “FIG. 3C illustrates an accelerator (e.g., CSA) with a plurality of processing elements 301 configured to execute the dataflow graph of FIG. 3B according to embodiments of the disclosure. More particularly, the dataflow graph 300 is overlaid into the array of processing elements 301 (e.g., and the (e.g., interconnect) network(s) therebetween), for example, such that each node of the dataflow graph 300 is represented as a dataflow operator in the array of processing elements 301”; see the computation being performed in fig. 3C which constitutes a pipeline];
a core controller to administrate an execution of the computational instructions by the computational pipeline [paragraphs 221, 230-231, “processing elements are organized as pipelines and support the injection of one pipelined dataflow operator per cycle. Processing elements may have a single-cycle latency. However, other pipelining choices may be used for other (e.g., more complicated) operations. For example, floating point operations may use multiple pipeline stages”; “Depicted processing element 1100 includes input controller 1101, input controller 1103, output controller 1105, and output controller 1107”; input controllers…output controllers];;
a router [paragraph 457, “embodiments herein provide circuitry to overlay high-radix dataflow operations on these networks for communications. For example, certain embodiments herein utilize the existing network for communications (e.g., interconnect network 104 described in reference to FIG. 1) to provide data routing capabilities between processing elements and other components of the spatial array, but also augment the network (e.g., network endpoints) to support the performance and/or control of some (e.g., less than all) of dataflow operations (e.g., without utilizing the processing elements to perform those dataflow operations)”];
a data movement processing core [paragraphs 545, 0836, “flow 6800 includes decoding an instruction with a decoder of a core of a processor into a decoded instruction 6802; executing the decoded instruction with an execution unit of the core of the processor to perform a first operation 6804; receiving an input of a dataflow graph comprising a plurality of nodes 6806; overlaying the dataflow graph into a plurality of processing elements of the processor and an interconnect network between the plurality of processing elements of the processor with each node represented as a dataflow operator in the plurality of processing elements 6808; and performing a second operation of the dataflow graph with the interconnect network and the plurality of processing elements by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements 6810”]; and
a data movement core controller, on the data movement processing core, to administrate an execution of the data movement instructions and thereby generate commands for the router to route data for the complex computation on and off the processing core [paragraphs 211, 465, 527, 532, "In certain embodiments, the routing of data between components (e.g., PEs) is enabled by setting switches (e.g., multiplexers and/or demultiplexers) and/or logic gate circuits of a circuit switched network (e.g., a local network) to achieve a desired configuration, e.g., a configuration according to a dataflow graph”; “As one example, a pick dataflow operation may have a plurality of inputs and steer (e.g., route) one of them as an output, e.g., as in FIG. 42…Additionally or alternatively, the network dataflow endpoint circuits may route data between processing elements, e.g., for the processing elements to perform processing operations on the data. Embodiments herein may thus utilize to the communications network to perform (e.g., steering) dataflow operations. Additionally or alternatively, the network dataflow endpoint circuits may perform as a mezzanine network discussed below”; “dataflow instructions on the actual CSA hardware”].
Chrysos does not explicitly disclose having a network-on-chip interface.
However, Wang discloses a router having a network-on-chip interface [paragraph 25, “NOC” refers to a network of routers, links between the routers, and interfaces between the routers and processing elements (e.g., general purpose computing cores or IP cores)].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Wang in the core of Chrysos, to implement a router having a network-on-chip interface, in order to interface more efficiently with the particular resources that their corresponding processing element need [Wang, paragraph 34].
Referring to claim 20, the modified Chrysos discloses the processing core of claim 19 wherein: the core controller and the data movement core controller use their own separate program counters [Chrysos, paragraphs 533, 569, 570, 692, 707, “dependency token counters 8814 (e.g., one per input queue), a set of dependency queues 8818 (e.g., one each per input queue)”; “input channels and output channels of the dependency queues are both implemented with counters”; “LCC operation may begin when it receives a pointer to a code segment. Depending on the LCB microarchitecture, this pointer (e.g., stored in pointer register 7206) may come either over a network (e.g., from within the CSA (fabric) itself) or through a memory system access to the LCC. When it receives such a pointer, the LCC optionally drains relevant state from its portion of the fabric for context storage, and then proceeds to immediately reconfigure the portion of the fabric for which it is responsible”; “LCCs is informed of the program to load, for example, by a set of (e.g., OS-visible) control-status-registers which will be used to inform individual LCCs of new program pointers, etc”].
Allowable Subject Matter
Claims 5-9, 11, 16, 17, and 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein: the routers in the set of routers and the scratch pad memories in the set of scratch pad memories are communicatively coupled; and the routers in the set of routers move the computation data from the set of scratch pad memories through the interconnect fabric, in combination with other recited limitations in claim 5.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein: a subset of the data movement instructions are configuration instructions for a configurable global address space for the set of processing cores; and the set of processing cores store a configurable mapping that maps the configurable global address space to physical addresses in the set of one or more memories, in combination with other recited limitations in claim 6.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein: a subset of the data movement instructions are data reformatting instructions; and the data reformatting instructions: (i) change a data type of the computation data; (ii) change a compression state of the computation data; and (iii) change a quantity of data structures storing the computation data, in combination with other recited limitations in claim 7.
Claims 8-9 are objected to based on their dependency.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein: the set of data movement processing cores receive information regarding a state of the interconnect fabric during the complex computation; and the conditional logic uses the information regarding the state of the interconnect fabric, in combination with other recited limitations in claim 11.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest changing a data type of the computation data using a subset of the data movement instructions, the subset of the data movement instructions being data reformatting instructions; changing a compression state of the computation data using the subset of the data movement instructions; and changing a quantity of data structures storing the computation data using the subset of the data movement instructions, in combination with other recited limitations in claim 18.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest wherein routing the computation data through the interconnect fabric comprises: moving, by the routers in the set of routers, the computation data from the set of scratch pad memories through the interconnect fabric, the routers in the set of routers and the scratch pad memories in the set of scratch pad memories being communicatively coupled, in combination with other recited limitations in claim 16.
The prior art of record taken alone or in combination fails to teach and/or fairly suggest storing, by the set of processing cores, a configurable mapping that maps a configurable global address space to physical addresses in the one or more memories, a subset of the data movement instructions being configuration instructions for the configurable global address space for the set of processing cores, in combination with other recited limitations in claim 17.
Conclusion
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/Farley Abad/ Primary Examiner, Art Unit 2181
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