Prosecution Insights
Last updated: July 17, 2026
Application No. 19/043,886

Latency Tolerance Escalation Detection

Non-Final OA §103
Filed
Feb 03, 2025
Priority
Sep 24, 2024 — provisional 63/698,383
Examiner
SHIN, CHRISTOPHER B
Art Unit
2181
Tech Center
2100 — Computer Architecture & Software
Assignee
Apple Inc.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
596 granted / 663 resolved
+34.9% vs TC avg
Minimal +5% lift
Without
With
+5.0%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
11 currently pending
Career history
676
Total Applications
across all art units

Statute-Specific Performance

§101
2.9%
-37.1% vs TC avg
§103
63.4%
+23.4% vs TC avg
§102
10.5%
-29.5% vs TC avg
§112
4.6%
-35.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 663 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 have been presented and pending in the application. Allowable Subject Matter After careful consideration and search of the present claimed invention(s), the examiner finds the claims 1-12 are allowable over the prior art of record. More specifically, the prior art of record does not teach the combinations of the claim 1 as a whole; therefore, the claims 1-12 are allowed. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over RAINDEL et al. (US 2024/0004683 A1). Examiner relies on the entire teachings of the RAINDEL reference for this rejection; therefore, the examiner advises the applicant to carefully consider the entire teachings of the RAINDEL to better understand the examiner’s position and interpretations applied to the claimed invention. The examiner also advises the applicant to carefully consider the entire teachings of the prior art of record, since the examiner relies on them for support of the well-known prior art teachings. The RAINDEL reference teaches functionally/operationally equivalent teachings of the claimed invention, when the examiner applies Broadest Reasonable Interpretation, as follows: CLAIMS 13-20 RAINDEL REF. TEACHINGS (emphasis added) 13. A method comprising: distributing, by a performance management circuit, Fig 1 & 3 with accompanying description where the MIGRATION CONTROL 116 teaches, along with 160-180, the performance management circuit respective indications of available bandwidth to ones of a plurality of agent circuits included in a computer system par 39-41, “migration control 116 scans through each relevant latency tolerance…shown using decision operation 310…operation 312 determines whether sufficient time exists to perform the page migration…whether sufficient time exist…pending page migration 171 and 172 are both performed” (examiner notes that the sufficient time(s) for page migration(s) teaches the claimed available bandwidth, the devices 156/158/116 teaches the claimed agent circuits, see also figure 9) implemented on one or more co-packaged integrated circuit dies; Not expressly taught, but obvious from the figures 1/9 teachings where one skilled in the art can easily recognize and/or motive to implement the figure 1/9 teachings (i.e., well-known to applicant from the applicant’s own and others & to one skilled in the art as commonly well-known practices in the art) receiving, by a latency escalation detector circuit coupled to a given agent circuit of the plurality of agent circuits, a respective indication of available bandwidth for the given agent circuit; par 39-41, “migration control 116 scans through each relevant latency tolerance…shown using decision operation 310…operation 312 determines whether sufficient time exists to perform the page migration…whether sufficient time exist…pending page migration 171 and 172 are both performed” (examiner notes that the sufficient time(s) teaches the claimed available bandwidth, the device 156/158/116 teaches the claimed agent circuits, see also figure 9, & the ML COMPONENT 164 with MIGRATION INFORAMATION 166 teaches the claimed escalation detector) based on determining that the respective indication of available bandwidth is insufficient for the given agent circuit, par 42, “If there is insufficient time…Operation 314 starts timer 162…Timer 162 lapses in operation 316…” asserting, by the latency escalation detector circuit, a trigger signal; and based on the asserting of the trigger signal, par 37, “based on a trigger condition, reporting, by the device 156, latency tolerance 181 of device 156, with the trigger condition comprising lapse of a timer…comprises sending an interrupt signal” capturing, by a snapshot circuit, current values from a set of registers in the given agent circuit without affecting a state of the set of registers. Par 39, “estimates an amount of time required for the page migration, based on at least a prior page migration (e.g., in page migration information 166) …estimation had previously been performed by ML component 164… migration control 116 merely looks up the result the result during operation” (examiner note that the look up the result of the ML 164/166 teaches the claimed capturing, by a snapshot circuit”) 14. The method of claim 13, wherein determining that the respective indication of available bandwidth is insufficient includes: determining, by the latency escalation detector circuit, a current latency tolerance based on current activity the given agent circuit; and Obvious from the teachings of par 39-41, “migration control 116 scans through each relevant latency tolerance…shown using decision operation 310…operation 312 determines whether sufficient time exists to perform the page migration…whether sufficient time exist…pending page migration 171 and 172 are both performed” (examiner notes that the sufficient time(s) teaches the claimed available bandwidth, the device 156/158/116 teaches the claimed agent circuits, see also figure 9, & the ML COMPONENT 164 with MIGRATION INFORAMATION 166 teaches the claimed escalation detector); see also par 25-32, “Determination of whether sufficient time exists…” determining, by the latency escalation detector circuit, that the current latency tolerance for the given agent circuit is insufficient to satisfy a target latency tolerance. par 42, “If there is insufficient time…Operation 314 starts timer 162…Timer 162 lapses in operation 316…”; see also par 25-32, “Determination of whether sufficient time exists…” 15. The method of claim 14, further comprising capturing, based on determining that the current latency tolerance is insufficient, up-to-date values for the current and target latency tolerances, and a minimum determined value of the current latency tolerance. Obvious from the teachings of Par 39, “estimates an amount of time required for the page migration, based on at least a prior page migration (e.g., in page migration information 166) …estimation had previously been performed by ML component 164… migration control 116 merely looks up the result the result during operation” (examiner note that the look up the result of the ML 164/166 teaches the claimed capturing, by a snapshot circuit” & the ML training can easily include values or desired values such as minimum or maximum that can be used and/or beneficial to the overall operations of figure 1/9) 16. The method of claim 13, further comprising reducing, by the given agent circuit in response to the asserting of the trigger signal, activity that consumes available bandwidth. Obvious from the teachings of par 42, “If there is insufficient time…Operation 314 starts timer 162…Timer 162 lapses in operation 316…” (examiner notes that the starting the timer delays one or more migration operations which reduces available bandwidth) 17. An apparatus, comprising: an agent circuit configured to: receive an indication of a current available bandwidth for a communication fabric, coupled to the agent circuit, that is configured to support transactions between the agent circuit and other circuit blocks; and Teachings of the claim 13 are similarly applied issue real-time (RT) transactions via the communication fabric in accordance with the indication, wherein RT transactions have a higher priority than other types of transactions; Par 38, “page migration queue 170 is sorted so that the most urgent page migrations are addressed first…” (examiner notes that it is well-known in the art to give RT transactions priority over other less priority transactions) a latency escalation detector circuit that is coupled to the agent circuit and configured to: receive the indication of the current available bandwidth; determine that the indicated current available bandwidth is insufficient for tasks assigned to the agent circuit; and based on the determination that the indicated current available bandwidth is insufficient, assert a trigger signal; and a snapshot circuit that is coupled to the agent circuit and configured to: based on the assertion of the trigger signal, capture current values from a particular set of registers in the agent circuit without affecting a state of the particular set of registers. Teachings of the claim 13 are similarly applied 18. The apparatus of claim 17, wherein the snapshot circuit includes a buffer circuit, and wherein the snapshot circuit is further configured to: capture, prior to the trigger signal, a series of values from the particular set of registers; and store the series of values in the buffer circuit. Obvious from the teachings of Par 39, “estimates an amount of time required for the page migration, based on at least a prior page migration (e.g., in page migration information 166) …estimation had previously been performed by ML component 164… migration control 116 merely looks up the result the result during operation” (examiner note that the look up the result of the ML 164/166 teaches the claimed capturing, by a snapshot circuit” & the ML training can easily include values or desired values such as minimum or maximum that can be used and/or beneficial to the overall operations of figure 1/9) 19. The apparatus of claim 17, further comprising a different snapshot circuit that is coupled to the agent circuit and configured to: based on the assertion of the trigger signal, capture current values from a different set of registers in the agent circuit without affecting a state of the different set of registers, wherein the particular set and different set are mutually exclusive. Obvious from the teachings of Par 39, “estimates an amount of time required for the page migration, based on at least a prior page migration (e.g., in page migration information 166) …estimation had previously been performed by ML component 164… migration control 116 merely looks up the result the result during operation” (examiner note that the look up the result of the ML 164/166 teaches the claimed capturing, by a snapshot circuit” & the ML training can easily include values or desired values such as minimum or maximum that can be used and/or beneficial to the overall operations of figure 1/9) 20. The apparatus of claim 19, wherein a number of captured values in the particular set is different than a number of captured values in the different set. Obvious from the teachings of Par 39, “estimates an amount of time required for the page migration, based on at least a prior page migration (e.g., in page migration information 166) …estimation had previously been performed by ML component 164… migration control 116 merely looks up the result the result during operation” (examiner note that the look up the result of the ML 164/166 teaches the claimed capturing, by a snapshot circuit” & the ML training can easily include values or desired values such as minimum or maximum that can be used and/or beneficial to the overall operations of figure 1/9) Examiner notes that the RAINDEL reference does not expressly disclose or identically label the claimed limitation “available bandwidth”; however, the RAINDEL reference does teach the functionally equivalent limitations or operations of “sufficient time exists to perform the page migration” that provides the substantially identical functional limitations of the claimed “available bandwidth”, as discussed above in detail. In addition, the claimed invention does not actually utilize the “capture current value”, other than simply store/capture; as a result, the examiner applies Broadest Reasonable Interpretation to the “capture current value” (i.e., no specific functional & operational limitation of the claimed “capture current value” is recited by the claimed invention). Therefore, it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to come up with the claimed invention from the functionally equivalent teachings of the RAINDEL reference for the detailed teachings and reasons discussed above. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER B SHIN whose telephone number is (571)272-4159. The examiner can normally be reached 8:00-4:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, IDRISS N ALROBAYE can be reached at 571-270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER B SHIN/Primary Examiner, Art Unit 2181
Read full office action

Prosecution Timeline

Feb 03, 2025
Application Filed
Jun 23, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
95%
With Interview (+5.0%)
2y 0m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 663 resolved cases by this examiner. Grant probability derived from career allowance rate.

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