DETAILED ACTION
The instant application having Application No. 19/044,005 has a total of 20 claims pending in the application, all of which are ready for examination by the examiner.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The instant application 19/044,005 filed 2/3/2025 is a Continuation of 18/526,634, filed 12/1/2023, now U.S. Patent #12307111.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 2/26/2025 and 11/20/2025 are being considered by the examiner.
Claim Objections
Claims 18-20 are objected to because of the following informalities:
Claims 18-20 are stated to be based on independent claim 9, and claims 18-20 recite computer-readable non-transitory storage medium of claim 9. However, claim 9 is directed to a method while claim 17 is directed to a computer-readable non-transitory storage medium. The examiner suggests amending claims 18-20 to state either their dependency to be based on claim 17 or modify the phrase reciting computer-readable non-transitory storage medium to recite method instead.
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-5, 9-15 of U.S. Patent No. 11886726 and Pletka et al. (US 20200066353 A1). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the commonly owned patent disclose/obviate the claims on the instant application.
Note that (MPEP 804.0 (I.B.1)) states: A complete response to a nonstatutory double patenting (NDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional.
As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. Therefore, an application must not be allowed unless the required compliant terminal disclaimer(s) is/are filed and/or the withdrawal of the nonstatutory double patenting rejection(s) is made of record by the examiner. See MPEP § 804.02, subsection VI, for filing terminal disclaimers required to overcome nonstatutory double patenting rejections in applications filed on or after June 8, 1995.
Instant application 19044005
U.S. Patent #11886726 (corresponding to Application # 17/542,943)
1. A system comprising: a memory device; and a processing device, operatively coupled to the memory device, the processing device to perform operations, comprising: identifying a first block family associated with a specified memory address; identifying a first threshold voltage offset bin associated with the first block family; calibrating a second block family associated with the first threshold voltage offset bin; responsive to calibrating the second block family, associating the first block family with a second threshold voltage offset bin; and reading, using the second threshold voltage offset bin, data from the specified memory address.
6. The system of claim 1, wherein the second block family is an oldest block family associated with the first threshold voltage offset bin.
1. A system comprising: a memory device; and a processing device, operatively coupled to the memory device, the processing device to: associate, with a first threshold voltage offset bin, a current block family associated with the memory device; responsive to programming a block residing on the memory device, associate the block with the current block family; and associate the current block family with a second threshold voltage offset bin by calibrating an oldest block family associated with the first threshold voltage offset bin.
9. The system of claim 1, wherein the processing device is further to: read, using a threshold voltage offset associated with the second threshold voltage offset bin, data from a block of the current block family.
2. The system of claim 1, wherein the block family comprises a plurality of blocks that have been programmed within at least one of: a specified time window or a specified temperature window.
10. The system of claim 1, wherein the block family comprises a plurality of blocks that have been programmed within at least one of: a specified time window or a specified temperature window.
3. The system of claim 1, wherein identifying the first block family associated with the specified memory address is performed based on block family metadata comprising a first table including a first plurality of records, wherein a first record of the first plurality of records associates the first block with the block family.
2. The system of claim 1, wherein associating the block with the current block family further comprises: appending, to block family metadata, a record associating the block with the current block family.
3. The system of claim 2, wherein the block family metadata comprises a first table including a plurality of records, wherein a record of the plurality of records associates the block with the current block family.
4. The system of claim 3, wherein the block family metadata comprises a second table including a second plurality of records, wherein a second record of the second plurality of records associates a plurality of dies of the block family with respective threshold voltage offset bins.
4. The system of claim 2, wherein the block family metadata comprises a second table including a plurality of records, wherein each record of the plurality of records associates a plurality of dies of the current block family with respective threshold voltage offset bins.
5. The system of claim 3, wherein the block family metadata comprises a third table including a third plurality of records, wherein a third record of the plurality of records associates a threshold voltage offset bin with one or more threshold voltages to be applied to respective base voltage read levels for performing read operations.
7. The system of claim 1, wherein the first threshold voltage offset bin defines a set of threshold voltage offsets to be applied to a base voltage read level for performing read operations.
5. The system of claim 2, wherein the block family metadata comprises a third table including a plurality of records, wherein each record of the plurality of records associates a corresponding threshold voltage offset bin with one or more threshold voltages to be applied to respective base voltage read levels for performing read operations.
9. A method, comprising: identifying, by a processing device managing a memory device, a first block family associated with a specified memory address; identifying a first threshold voltage offset bin associated with the first block family; calibrating a second block family associated with the first threshold voltage offset bin; responsive to calibrating the second block family associated with the first threshold voltage offset bin, associating the first block family with a second threshold voltage offset bin; reading, using the second threshold voltage offset bin, data from the specified memory address.
14. The method of claim 9, wherein the second block family is an oldest block family associated with the first threshold voltage offset bin.
11. A method, comprising:
identifying, by a processing device, based on block family metadata associated with a memory device, a block family associated with a physical block of the memory device;
identifying a first threshold voltage offset bin associated with the block family;
associating the block family with a second threshold voltage offset bin by calibrating an oldest block family associated with the first threshold voltage offset bin;
reading, using a threshold voltage offset associated with the second threshold voltage offset bin, data from the physical block.
10. The method of claim 9, wherein the block family comprises a plurality of blocks that have been programmed within at least one of: a specified time window or a specified temperature window.
12. The method of claim 11, wherein the block family comprises a plurality of blocks that have been programmed within at least one of: a specified time window or a specified temperature window.
11. The method of claim 9, wherein identifying the first block family associated with the specified memory address is performed based on block family metadata comprising a first table including a first plurality of records, wherein a first record of the first plurality of records associates the first block with the block family.
13. The method of claim 11, wherein the block family metadata comprises a first table including a plurality of records, wherein a record of the plurality of records associates the physical block with the block family.
12. The method of claim 11, wherein the block family metadata comprises a second table including a second plurality of records, wherein a second record of the second plurality of records associates a plurality of dies of the block family with respective threshold voltage offset bins.
14. The method of claim 11, wherein the block family metadata comprises a second table including a plurality of records, wherein each record of the plurality of records associates a plurality of dies of the block family with respective threshold voltage offset bins.
13. The method of claim 11, wherein the block family metadata comprises a third table including a third plurality of records, wherein a third record of the plurality of records associates a threshold voltage offset bin with one or more threshold voltages to be applied to respective base voltage read levels for performing read operations.
15. The method of claim 9, wherein the first threshold voltage offset bin defines a set of threshold voltage offsets to be applied to a base voltage read level for performing read operations.
15. The method of claim 11, wherein the block family metadata comprises a third table including a plurality of records, wherein each record of the plurality of records associates a corresponding threshold voltage offset bin with one or more threshold voltages to be applied to respective base voltage read levels for performing read operations.
17. A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a processing device, cause the processing device to perform operations, comprising: identifying, by a processing device managing a memory device, a first block family associated with a specified memory address; identifying a first threshold voltage offset bin associated with the first block family; calibrating a second block family associated with the first threshold voltage offset bin; responsive to calibrating the second block family associated with the first threshold voltage offset bin, associating the first block family with a second threshold voltage offset bin; reading, using the second threshold voltage offset bin, data from the specified memory address.
19. The computer-readable non-transitory storage medium of claim 9, wherein the second block family is an oldest block family associated with the first threshold voltage offset bin.
1. A system comprising: a memory device; and a processing device, operatively coupled to the memory device, the processing device to: associate, with a first threshold voltage offset bin, a current block family associated with the memory device; responsive to programming a block residing on the memory device, associate the block with the current block family; and associate the current block family with a second threshold voltage offset bin by calibrating an oldest block family associated with the first threshold voltage offset bin.
9. The system of claim 1, wherein the processing device is further to: read, using a threshold voltage offset associated with the second threshold voltage offset bin, data from a block of the current block family.
18. The computer-readable non-transitory storage medium of claim 9, wherein the block family comprises a plurality of blocks that have been programmed within at least one of: a specified time window or a specified temperature window.
10. The system of claim 1, wherein the block family comprises a plurality of blocks that have been programmed within at least one of: a specified time window or a specified temperature window.
Regarding claims 1, 7-9, 15-17, and 20, U.S. Patent #11886726 discloses all limitations except for an address corresponding to a block family and calibrating voltage offset used with a bin. However, Pletka et al. (US 20200066353 A1) teaches addresses for performing read/writes to logical blocks or physical pages in a block (para. 25, 28, 31) and offsets for modifying initial read voltage thresholds (para. 38-40; figs. 4A-4B and associated paragraphs), the offsets determined based on a calibration performed by applying different offsets on pages of a block and comparing bit error rates (para. 62-67; fig. 10 and associated paragraphs; also see para. 74 providing for a computer readable storage medium having computer readable program instructions).
U.S. Patent #11886726 and Pletka are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of U.S. Patent #11886726 and Pletka, to modify the disclosures by U.S. Patent #11886726 to include disclosures by Pletka since they both teach data storage and memory access, wherein Pletka is directed towards improved voltage calibration process (para. 6). Therefore, it would be applying a known technique (determining voltage offsets applied to initial read voltage thresholds based on a calibration using different offsets and resulting bit error rates, reading data in a page/block based on a logical address, the process executable based on program instructions in a computer readable storage medium) to a known device (device configured to read a block in a current block family using a second threshold voltage offset bin, where a bin comprises threshold voltages to be applied to base voltage read levels for reads, and where calibration is performed on a second block family) ready for improvement to yield predictable results (device configured, based on program instructions in a computer readable storage medium, to read a block in a current block family using a second threshold voltage offset bin and a corresponding address, where a bin comprises offsets to be applied to base voltage read levels for reads, and where calibration is performed on a second block family based on different offsets and corresponding bit error rates in order to provide for improved read voltage calibration and memory access). MPEP 2143
The double patenting rejection above applies to claims 1-20.
Claims 1-20 are additionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 7-11 of U.S. Patent No. 11231863 and Pletka et al. (US 20200066353 A1). Although the claims at issue are not identical, they are not patentably distinct from each other because the claims of the commonly owned patent disclose/obviate the claims on the instant application.
Instant application 19044005
U.S. Patent #11231863 (corresponding to Application #16/800,221)
1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, the processing device to perform operations, comprising:
identifying a first block family associated with a specified memory address;
identifying a first threshold voltage offset bin associated with the first block family;
calibrating a second block family associated with the first threshold voltage offset bin;
responsive to calibrating the second block family, associating the first block family with a second threshold voltage offset bin; and
reading, using the second threshold voltage offset bin, data from the specified memory address.
6. The system of claim 1, wherein the second block family is an oldest block family associated with the first threshold voltage offset bin.
7. A method, comprising:
receiving, by a processing device, a read command specifying an identifier of a logical block;
translating the identifier of the logical block into a physical address of a physical block stored on a memory device, wherein the physical address comprises an identifier of a memory device die;
identifying, based on block family metadata associated with the memory device, a block family associated with the physical address;
identifying a first threshold voltage offset bin associated with the block family;
associating the block family with a second threshold voltage offset bin by calibrating an oldest block family associated with the first threshold voltage offset bin;
determining a threshold voltage offset associated with the block family and the memory device die;
computing a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the memory device die; and
reading, using the modified threshold voltage, data from the physical block.
11. The method of claim 7, wherein the block family metadata comprises a third table including a plurality of records, wherein a record of the plurality of records associates a threshold voltage offset bin with one or more threshold voltages to be applied to respective base voltage read levels for performing read operations.
2. The system of claim 1, wherein the block family comprises a plurality of blocks that have been programmed within at least one of: a specified time window or a specified temperature window.
8. The method of claim 7, wherein the block family comprises a plurality of blocks that have been programmed within at least one of: a specified time window or a specified temperature window.
3. The system of claim 1, wherein identifying the first block family associated with the specified memory address is performed based on block family metadata comprising a first table including a first plurality of records, wherein a first record of the first plurality of records associates the first block with the block family.
9. The method of claim 7, wherein the block family metadata comprises a first table including a plurality of records, wherein a record of the plurality of records associates the physical block with the block family.
4. The system of claim 3, wherein the block family metadata comprises a second table including a second plurality of records, wherein a second record of the second plurality of records associates a plurality of dies of the block family with respective threshold voltage offset bins.
10. The method of claim 7, wherein the block family metadata comprises a second table including a plurality of records, wherein a record of the plurality of records associates a plurality of dies of the block family with respective threshold voltage offset bins.
5. The system of claim 3, wherein the block family metadata comprises a third table including a third plurality of records, wherein a third record of the plurality of records associates a threshold voltage offset bin with one or more threshold voltages to be applied to respective base voltage read levels for performing read operations.
7. The system of claim 1, wherein the first threshold voltage offset bin defines a set of threshold voltage offsets to be applied to a base voltage read level for performing read operations.
11. The method of claim 7, wherein the block family metadata comprises a third table including a plurality of records, wherein a record of the plurality of records associates a threshold voltage offset bin with one or more threshold voltages to be applied to respective base voltage read levels for performing read operations.
9. A method, comprising:
identifying, by a processing device managing a memory device, a first block family associated with a specified memory address;
identifying a first threshold voltage offset bin associated with the first block family;
calibrating a second block family associated with the first threshold voltage offset bin;
responsive to calibrating the second block family associated with the first threshold voltage offset bin, associating the first block family with a second threshold voltage offset bin;
reading, using the second threshold voltage offset bin, data from the specified memory address.
14. The method of claim 9, wherein the second block family is an oldest block family associated with the first threshold voltage offset bin.
7. A method, comprising:
receiving, by a processing device, a read command specifying an identifier of a logical block;
translating the identifier of the logical block into a physical address of a physical block stored on a memory device, wherein the physical address comprises an identifier of a memory device die;
identifying, based on block family metadata associated with the memory device, a block family associated with the physical address;
identifying a first threshold voltage offset bin associated with the block family;
associating the block family with a second threshold voltage offset bin by calibrating an oldest block family associated with the first threshold voltage offset bin;
determining a threshold voltage offset associated with the block family and the memory device die;
computing a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the memory device die; and
reading, using the modified threshold voltage, data from the physical block.
11. The method of claim 7, wherein the block family metadata comprises a third table including a plurality of records, wherein a record of the plurality of records associates a threshold voltage offset bin with one or more threshold voltages to be applied to respective base voltage read levels for performing read operations.
10. The method of claim 9, wherein the block family comprises a plurality of blocks that have been programmed within at least one of: a specified time window or a specified temperature window.
8. The method of claim 7, wherein the block family comprises a plurality of blocks that have been programmed within at least one of: a specified time window or a specified temperature window.
11. The method of claim 9, wherein identifying the first block family associated with the specified memory address is performed based on block family metadata comprising a first table including a first plurality of records, wherein a first record of the first plurality of records associates the first block with the block family.
9. The method of claim 7, wherein the block family metadata comprises a first table including a plurality of records, wherein a record of the plurality of records associates the physical block with the block family
12. The method of claim 11, wherein the block family metadata comprises a second table including a second plurality of records, wherein a second record of the second plurality of records associates a plurality of dies of the block family with respective threshold voltage offset bins.
10. The method of claim 7, wherein the block family metadata comprises a second table including a plurality of records, wherein a record of the plurality of records associates a plurality of dies of the block family with respective threshold voltage offset bins.
13. The method of claim 11, wherein the block family metadata comprises a third table including a third plurality of records, wherein a third record of the plurality of records associates a threshold voltage offset bin with one or more threshold voltages to be applied to respective base voltage read levels for performing read operations.
15. The method of claim 9, wherein the first threshold voltage offset bin defines a set of threshold voltage offsets to be applied to a base voltage read level for performing read operations.
11. The method of claim 7, wherein the block family metadata comprises a third table including a plurality of records, wherein a record of the plurality of records associates a threshold voltage offset bin with one or more threshold voltages to be applied to respective base voltage read levels for performing read operations.
17. A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a processing device, cause the processing device to perform operations, comprising:
identifying, by a processing device managing a memory device, a first block family associated with a specified memory address;
identifying a first threshold voltage offset bin associated with the first block family;
calibrating a second block family associated with the first threshold voltage offset bin;
responsive to calibrating the second block family associated with the first threshold voltage offset bin, associating the first block family with a second threshold voltage offset bin;
reading, using the second threshold voltage offset bin, data from the specified memory address.
19. The computer-readable non-transitory storage medium of claim 9, wherein the second block family is an oldest block family associated with the first threshold voltage offset bin.
7. A method, comprising:
receiving, by a processing device, a read command specifying an identifier of a logical block;
translating the identifier of the logical block into a physical address of a physical block stored on a memory device, wherein the physical address comprises an identifier of a memory device die;
identifying, based on block family metadata associated with the memory device, a block family associated with the physical address;
identifying a first threshold voltage offset bin associated with the block family;
associating the block family with a second threshold voltage offset bin by calibrating an oldest block family associated with the first threshold voltage offset bin;
determining a threshold voltage offset associated with the block family and the memory device die;
computing a modified threshold voltage by applying the threshold voltage offset to a base read level voltage associated with the memory device die; and
reading, using the modified threshold voltage, data from the physical block.
11. The method of claim 7, wherein the block family metadata comprises a third table including a plurality of records, wherein a record of the plurality of records associates a threshold voltage offset bin with one or more threshold voltages to be applied to respective base voltage read levels for performing read operations.
18. The computer-readable non-transitory storage medium of claim 9, wherein the block family comprises a plurality of blocks that have been programmed within at least one of: a specified time window or a specified temperature window.
8. The method of claim 7, wherein the block family comprises a plurality of blocks that have been programmed within at least one of: a specified time window or a specified temperature window.
Regarding claims 7-8, 15-17, and 20, U.S. Patent #11231863 discloses all limitations except for calibrating voltage offset used with a bin. However, Pletka et al. (US 20200066353 A1) teaches offsets for modifying initial read voltage thresholds (para. 38-40; figs. 4A-4B and associated paragraphs), the offsets determined based on a calibration performed by applying different offsets on pages of a block and comparing bit error rates (para. 62-67; fig. 10 and associated paragraphs; also see para. 74 providing for a computer readable storage medium having computer readable program instructions).
U.S. Patent #11231863 and Pletka are analogous to the claimed invention because they are in the same field of endeavor involving data storage and memory access.
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention, having knowledge of U.S. Patent #11231863 and Pletka, to modify the disclosures by U.S. Patent #11231863 to include disclosures by Pletka since they both teach data storage and memory access, wherein Pletka is directed towards improved voltage calibration process (para. 6). Therefore, it would be applying a known technique (determining voltage offsets applied to initial read voltage thresholds based on a calibration using different offsets and resulting bit error rates, the process executable based on program instructions in a computer readable storage medium) to a known device (device configured to read a block in a block family using a second threshold voltage offset bin, where a bin comprises threshold voltages to be applied to base voltage read levels for reads, and where calibration is performed on a second block family) ready for improvement to yield predictable results (device configured, based on program instructions in a computer readable storage medium, to read a block in a block family using a second threshold voltage offset bin, where a bin comprises offsets to be applied to base voltage read levels for reads, and where calibration is performed on a second block family based on different offsets and corresponding bit error rates in order to provide for improved read voltage calibration and memory access). MPEP 2143
The double patenting rejection above applies to claims 1-20.
Allowable Subject Matter
Claims 1-20 are rejected on the ground of nonstatutory double patenting as shown above, and claims 18-20 are further objected as shown above. But the claims would be allowable if they were further amended to overcome the nonstatutory double patenting rejections or through a timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d), in addition to being amended to overcome the claim objections.
With respect to claim 1, “… identifying a first block family associated with a specified memory address; identifying a first threshold voltage offset bin associated with the first block family; calibrating a second block family associated with the first threshold voltage offset bin; responsive to calibrating the second block family, associating the first block family with a second threshold voltage offset bin.” in conjunction with the other limitations of the claim, are not disclosed by the prior art of record.
The closest prior art of record are Hyun et al. (US 9916237 B2), Fisher et al. (US 10236067 B2), Navon et al. (US 20180373437 A1), Bakshi et al. (US 20160170682 A1), and Papandreou (US 20200051621 A1).
Hyun teaches a configuration parameter module for determining different read voltage thresholds for different word lines of groups of erase blocks. Fisher teaches retrieving read adta by applying read voltages which divide the programmed threshold voltage window into discrete regimes and then applying a reverse mapping between the detected threshold voltage levels and corresponding read data values. Navon teaches applying respective time tags indicating respective operating parameters to blocks. Bakshi teaches assigning age tags indicating programming signals to corresponding memory regions. Papandreous teaches identifying a group of pages in an open state having comparable characteristics and performing calibration of read voltage to the pages of the group.
However, the prior arts of record, neither individually nor in combination, teaches, with respect to a first block family which is associated with a first threshold voltage offset bin and a specified memory address, calibrating a second block family which is also associated with the first threshold voltage offset bin, where, responsive to calibrating the second block family, the first block family becomes associated with a second threshold voltage offset bin, and read operations for the first block family is performed using the second threshold voltage offset bin at the specified memory address.
Therefore, the prior arts of record, neither individually nor in combination disclose, in conjunction with the other limitations of the claim, the claim as a whole.
With respect to claim 9, “… a first block family associated with a specified memory address; identifying a first threshold voltage offset bin associated with the first block family; calibrating a second block family associated with the first threshold voltage offset bin; responsive to calibrating the second block family associated with the first threshold voltage offset bin, associating the first block family with a second threshold voltage offset bin; reading, using the second threshold voltage offset bin, data from the specified memory address.” in conjunction with the other limitations of the claim, are not disclosed by the prior art of record.
The closest prior art of record are Hyun et al. (US 9916237 B2), Fisher et al. (US 10236067 B2), Navon et al. (US 20180373437 A1), Bakshi et al. (US 20160170682 A1), and Papandreou (US 20200051621 A1).
Hyun teaches a configuration parameter module for determining different read voltage thresholds for different word lines of groups of erase blocks. Fisher teaches retrieving read adta by applying read voltages which divide the programmed threshold voltage window into discrete regimes and then applying a reverse mapping between the detected threshold voltage levels and corresponding read data values. Navon teaches applying respective time tags indicating respective operating parameters to blocks. Bakshi teaches assigning age tags indicating programming signals to corresponding memory regions. Papandreous teaches identifying a group of pages in an open state having comparable characteristics and performing calibration of read voltage to the pages of the group.
However, the prior arts of record, neither individually nor in combination, teaches, with respect to a first block family which is associated with a first threshold voltage offset bin and a specified memory address, calibrating a second block family which is also associated with the first threshold voltage offset bin, where, responsive to calibrating the second block family, the first block family becomes associated with a second threshold voltage offset bin, and read operations for the first block family is performed using the second threshold voltage offset bin at the specified memory address.
Therefore, the prior arts of record, neither individually nor in combination disclose, in conjunction with the other limitations of the claim, the claim as a whole.
With respect to claim 17, “… identifying, by a processing device managing a memory device, a first block family associated with a specified memory address; identifying a first threshold voltage offset bin associated with the first block family; calibrating a second block family associated with the first threshold voltage offset bin; responsive to calibrating the second block family associated with the first threshold voltage offset bin, associating the first block family with a second threshold voltage offset bin; reading, using the second threshold voltage offset bin, data from the specified memory address.” in conjunction with the other limitations of the claim, are not disclosed by the prior art of record.
The closest prior art of record are Hyun et al. (US 9916237 B2), Fisher et al. (US 10236067 B2), Navon et al. (US 20180373437 A1), Bakshi et al. (US 20160170682 A1), and Papandreou (US 20200051621 A1).
Hyun teaches a configuration parameter module for determining different read voltage thresholds for different word lines of groups of erase blocks. Fisher teaches retrieving read adta by applying read voltages which divide the programmed threshold voltage window into discrete regimes and then applying a reverse mapping between the detected threshold voltage levels and corresponding read data values. Navon teaches applying respective time tags indicating respective operating parameters to blocks. Bakshi teaches assigning age tags indicating programming signals to corresponding memory regions. Papandreous teaches identifying a group of pages in an open state having comparable characteristics and performing calibration of read voltage to the pages of the group.
However, the prior arts of record, neither individually nor in combination, teaches, with respect to a first block family which is associated with a first threshold voltage offset bin and a specified memory address, calibrating a second block family which is also associated with the first threshold voltage offset bin, where, responsive to calibrating the second block family, the first block family becomes associated with a second threshold voltage offset bin, and read operations for the first block family is performed using the second threshold voltage offset bin at the specified memory address.
Therefore, the prior arts of record, neither individually nor in combination disclose, in conjunction with the other limitations of the claim, the claim as a whole.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS KIM whose telephone number is (571)272-8093. The examiner can normally be reached Monday - Friday: 7:30-5:30.
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/E.Y.K./Examiner, Art Unit 2135
/JARED I RUTZ/Supervisory Patent Examiner, Art Unit 2135