DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
CLAIM INTERPRETATION
Claims in this application are not interpreted under 35 U.S.C. §112(f) in this application.
Claim Objections
Claims 1-8, 12-15 and 17-20 are objected to because of the following informalities:
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. US 2022/0100681 A1 (Chen) in view of US Patent Application Publication No. US 2025/0307189 A1 (Medeiros).
Regarding claim 1:
Chen discloses, a method, comprising: storing, in a memory sub-system (by disclosing that an SSD (200) (memory sub-system), including NAND Flash Memory Devices (202), NAND Interface (204), SSD controller (206) and host interface (208). The methods of the invention may be practiced by non-transitory computer program instructions, for execution by a processor to perform the disclosed methods [0020-0022] [0031]) having a physical storage space (the SSD (200) may include a NAND storage device (304) and a command memory buffer (CMB) of the controller (302) [0038]. Data from the host may be stored in these locations (i.e., both may be considered a physical storage space) [0038]) and providing a logical storage space (by teaching that the host interacts with the SSD using logical addresses, which are used to identify data stored in physical memory spaces (such as the CMB or the NAND storage device (304)) in the SSD [0037] [0043] [0052]) a plurality of entries in a block table, each respective entry in the plurality of entries configured to identify… a corresponding portion of the logical storage space (by teaching that to keep track of which data is buffered in the CMB of the controller (302), a block table (500) may record the status of a plurality of logical blocks of data being processed by the controller (302) in a plurality of entries [0043]. The block table may record control data (C), which includes the logical block address (LBA) of the data represented by each entry [0045]. The block table (500) may also include a data valid flag that indicates that data to be read from the storage device for the read quest has been written to the CMB (i.e. a memory space and a physical memory space) [0047] [Fig. 5]) receiving, a storage access request (the SSD may receive a read command. The read command may specify a logical block address or logical block addresses (i.e. logical storage space) indicating locations of data blocks to be read from a storage device [0037] [0043] [0052]); and executing, in the memory sub-system, the storage access request to cause a data portion, from the logical storage space, to be buffered or cached in a memory space of the memory sub-system (by teaching that in response to the read request, the data corresponding to each LBA L (in the logical storage space) may be read from the NAND, and stored in a buffer such as a command memory buffer (CMB) internal to the controller (302) (in a memory space of the memory sub-system and a physical storage space of the memory sub-system) [0038]). To keep track of the buffered data, a block table (500) may record the status of each of the plurality of logical blocks of data being processed by the controller (302) [0043]. The block table may record control data (C) for each entry, which includes the logical block address (LBA) of the data represented by the entry [0045]) configuring a first entry, among the plurality of entries, to indicate that the data portion is cached or buffered in the memory space (by teaching that each entry may include a data valid flag (DV) that indicates whether the data has been retrieved from the storage device and written to a buffer (i.e., is cached or buffered) such as the CMB (in the memory space) [0047]).
Chen does not explicitly disclose, but Medeiros teaches storing, in a memory sub-system, a plurality of entries in a logical to physical translation table, each respective entry in the plurality of entries configured to identify mapping between a portion of the logical storage space and a portion of the physical storage space of the memory sub-system (by teaching that a cache metadata table may include a plurality of entries. The entries may map a different one of the logical block addresses (LBAs) (logical storage space) to a corresponding physical memory address (physical storage space of the memory sub-system), including whether the physical memory address points to a location in DIMM, PCR, or CMB. In this way, for each memory address that is identified in the cache metadata table, the cache metadata table also indicates the type of hardware that is used to implement each of the cache slots [0021]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the block table used for keeping track of cached data in the CMB as taught by Chen to include the physical addresses of the location the cached data is stored (i.e. such that the plurality of entries taught by Chen are entries in a logical to physical table as taught by Medeiros), and the type of hardware used to implement each of the cache slots as taught by Medeiros.
One of ordinary skill in the art would have been motivated to make this modification because it allows system administrators to have an additional tool for fine-tuning their caching algorithms as taught by Medeiros in [0021].
Claims 2-5 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Medeiros in further view of US Patent Application Publication No. US 2015/0347026 A1 (Thomas).
Regarding claim 2 and analogous claim 16:
The method of claim 1 is made obvious by Chen in view of Medeiros.
Chen further discloses, wherein the method further comprises:
Chen does not explicitly disclose, but Medeiros teaches, and storing, in the memory sub-system, information to identify a location, in the memory space, at which the data portion is cached or buffered (by teaching that a cache metadata table may include a plurality of entries. The entries may map a different one of the logical block addresses (LBAs) (logical storage space) to a corresponding physical memory address (i.e., a memory space and a physical storage space of the memory sub-system), including whether the physical memory address points to a location in DIMM, PCR, or CMB. In this way, for each memory address that is identified in the cache metadata table, the cache metadata table also indicates the type of hardware that is used to implement each of the cache slots [0021]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the block table using for keeping track of cached data in the CMB as taught by Chen to include the physical addresses of the location the cached data is stored, and the type of hardware used to implement each of the cache slots as taught by Medeiros.
One of ordinary skill in the art would have been motivated to make this modification because it allows system administrators to have an additional tool for fine-tuning their caching algorithms as taught by Medeiros in [0021].
Chen does not explicitly disclose, but Thomas teaches wherein each of the plurality of entries as stored in the memory sub-system occupies a same size of storage resources (by teaching that using fixed-size mapping entries is easier to implement).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the block table entries as taught by Chen in view of Medeiros to be fixed-size entries that therefore each take up the same amount of storage resources as taught by Thomas.
One of ordinary skill in the art would have been motivated to make this modification because using fixed-size entries is easier to implement as taught by Thomas in [0004].
Regarding claim 3 and analogous claim 17:
The method of claim 2 is made obvious by Chen in view of Medeiros in further view of Thomas (Chen-Medeiros-Thomas).
Chen further discloses, wherein each respective entry in the plurality of entries is configured with a bit-sized field configured to store a parameter indicative of whether or not the corresponding portion of the logical storage space, (mapped to the corresponding portion of the physical storage space as taught by Medeiros in the analysis performed for claims 1-2 above) has data buffered or cached in the memory space (by teaching that each entry may include the data valid flag (DV) (i.e., flag is understood to be binary ‘1’ or ‘0’) (bit sized field) that indicates whether the data has been retrieved from the storage device and written to a buffer such as the CMB [0047]).
Regarding claim 4:
The method of claim 3 is made obvious by Chen-Medeiros-Thomas.
Chen further discloses, wherein the corresponding portion of the logical storage space includes a plurality of logical storage blocks addressable via a plurality of logical block addressing (LBA) addresses (by teaching that the memory device may be accessed with a plurality of LBAs, as there may be a plurality of LBAs in the block table (500) [0043], and there is typically one LBA per 4kb of data in the storage device, but other granularities may be used [0044]).
Regarding claim 5 and analogous claim 18:
The method of claim 4 is made obvious by Chen-Medeiros-Thomas.
Chen further discloses, wherein the first entry is configured to map a first portion of the logical storage space; and the method further comprises: searching the information to identify the location based on an identifier of the first portion (by teaching that each block of data is identified by the LBA in the block table (500) [0043], in this way, the controller can look up a buffer address in the block table using the LBA [0061]).
Claims 6-7 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen-Medeiros-Thomas in further view of US Patent Application Publication No. US 2022/0229772 A1 (Jin).
Regarding claim 6 and analogous claim 19:
The method of claim 5 is made obvious by Chen-Medeiros-Thomas.
Chen does not explicitly disclose, but Jin teaches, further comprising: sorting the information to identify the location based on the identifier of the first portion (by teaching that sorting mapping entries by a logical address order allows the map to be searched in a more efficient manner, such as with a binary search operation, which is more efficient than a sequential scan and allows for the map to be searched with less resources, in order to find an entry associated with the logical block address [0031] [0039] [0047] [0163] [0202]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the block table as taught by Chen-Medeiros-Thomas to include being sorted by LBA, so that searching for an entry can use a more efficient searching algorithm as taught by Jin.
One of ordinary skill in the art would have been motivated to make this modification because it would allow the table to be searched with less resources as taught by Jin in [0047] [0202].
Regarding claim 7:
The method of claim 6 is made obvious by Chen-Medeiros-Thomas in further view of Jin (Chen-Medeiros-Thomas-Jin).
Chen further discloses, wherein the data portion is a portion of data stored in the first portion of the logical storage space (by teaching that in response to the read request, the data corresponding to each LBA L (a portion of data stored in the first portion of the logical storage space) may be read from the NAND, and stored in a buffer such as a command memory buffer (CMB) internal to the controller (302) [0037] [0044])).
Claims 8 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen-Medeiros-Thomas-Jin in further view of US Patent Application Publication No. US 2026/0079625 A1 (Colline).
Regarding claim 8 and analogous claim 20:
The method of claim 7 is made obvious by Chen-Medeiros-Thomas-Jin.
Chen does not explicitly disclose, but Colline teaches, wherein a size of the data portion is smaller than a size of each of the plurality of logical storage blocks addressable respectively via the plurality of logical block addressing (LBA) addresses (by teaching that short block IO are common among AI workloads that operate on small data segments, such as data segments that are smaller than a NVMe devices minimum read size [0012]. To address the mismatch, the system can accumulate a plurality of short IO requests. the system can read the full block for each short I/O request and then discard the unwanted portions [0013]. A plurality of data for multiple short block I/O requests can then be accumulated so that the data for multiple requests can be returned to the host in one larger packed that combines multiple of the short block I/O request’s data together into the typical block size [0014]. The data requested by the short block I/O requests is smaller than the data read for a corresponding single LBA read [0025]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified reading data to the buffer to satisfy host read requests as taught by Chen-Medeiros-Thomas-Jin to include being able to read data short block I/O data and accumulate the data (such as in the buffer as taught by Chen-Medeiros-Thomas-Jin) into a single block size for transfer to the host in a single packet as taught by Colline.
One of ordinary skill in the art would have been motivated to make this modification because it would allow the system to process the short block I/O requests that are commonly used by AI in an efficient manner as taught by Colline in [0012-0014]].
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable Chen in view of US Patent Application Publication No. US 2020/0272574 A1 (Shen).
Regarding claim 9:
Chen discloses A memory sub-system, comprising: memory of a first type to provide a memory space; memory cells of a second type to provide a physical storage space for implementation of a logical storage space (by disclosing that an SSD (200) (memory sub-system), including NAND Flash Memory Devices (202) (memory cells of a second type to provide a physical storage space), NAND Interface (204), SSD controller (206) and host interface (208), may receive a read command. The read command may specify a logical block address or logical block addresses indicating locations of data blocks to be read from a storage device (304) (i.e. a physical storage space implementing a logical storage space) [0037] [0043] [0052]. The memory device may also include a buffer in the memory internal to the controller used to buffer data called the CMB (memory cells of a first type to provide a memory space) [0038] [0047]. The storage system may keep track of logical-to-physical address translations using an FTL [0037]); store a plurality of entries in a table, each respective entry in the plurality of entries configured to identify a corresponding portion of the logical storage space (by teaching that to keep track of which data is buffered in the CMB of the controller (302), a block table (500) may record the status of a plurality of logical blocks of data being processed by the controller (302) in a plurality of entries [0043]. The block table may record control data (C), which includes the logical block address (LBA) of the data represented by each entry [0045]. The block table (500) may also include a data valid flag that indicates that data to be read from the storage device for the read quest has been written to the CMB (i.e. a memory space and a physical memory space) [0047] [Fig. 5]) and store, in the memory space, a copy of a data portion addressable in the logical storage space (by teaching that in response to the read request, the data corresponding to each LBA L (in the logical storage space) may be read from the NAND, and stored in a buffer such as a command memory buffer (CMB) internal to the controller (302) (in the memory space) [0038]. To keep track of the buffered data, the controller uses a block table (500) [0043]) and configure a first entry, among the plurality of entries, to indicate that the data portion is cached or buffered in the memory space (by teaching that each entry may include the data valid flag (DV) that indicates whether the data corresponding to the logical address stored in the control data (C) has been retrieved from the storage device and written to a buffer such as the CMB [0047]).
Chen does not explicitly disclose, but Shen teaches, memory cells of a first type; and a controller configured to: store a plurality of entries in a logical to physical translation table, each respective entry in the plurality of entries configured to identify mapping between a portion of a logical storage space and a portion of the physical storage space of the memory sub-system; (by teaching that the memory controller may use temporary storage (206) for temporary data required during the operations of flash memory (202), which may be dynamic random access memory (DRAM) or static random access memory (SRAM) (i.e., memory cells of a first type). The temporary storage may also be used to store a logical to physical (L2P) table. Each entry in a L2P address mapping table (220) may be used to map logical addresses (of a logical storage space) to physical addresses of a physical space of the flash memory (S314) [Figs. 2-3] [0033]. However, depending on some bits of the physical address area of the L2P map, the L2P map may also indicate whether or not data is in a temporary storage space in the controller and a physical address of the temporary storage space in the controller where the data is stored [0033-0044]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the FTL used for address translation and the block table used for keeping track of data in the cache as taught by Chen to instead store a L2P table in the temporary DRAM or SRAM storage (in addition to storing the CMB there), and to keep track of whether data is buffered/cached in the CMB using bits of the physical address in the L2P table as taught by Shen (i.e. such that the plurality of entries taught by Chen are entries in a logical to physical table as taught by Shen).
One of ordinary skill in the art would have been motivated to make this modification because it allows a controller to determine whether data is cached/buffered using the L2P and determine where the data is stored, without using additional or exclusive bits in the L2P mapping table, which allows a larger storage area to be recorded with the same number of bits as taught by Shen in [0039].
Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Shen in further view of Thomas.
Regarding claim 10:
The memory sub-system of claim 9 is made obvious by Chen in view of Shen (Chen-Shen).
Chen does not explicitly disclose, but Shen teaches, wherein the controller is further configured to: store information to identify a location, in the memory space, at which the data portion is cached or buffered (by teaching that each entry in a L2P address mapping table (220) may be used to map logical addresses (of a logical storage space) to physical addresses of a physical space of the flash memory (S314) [Figs. 2-3] [0033]. However, depending on some bits of the physical address area of the L2P map, the L2P map may also indicate whether or not data is in a temporary storage space in the controller and a physical address of the temporary storage space in the controller where the data is stored [0033-0044]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the FTL used for address translation and the block table used for keeping track of data in the cache as taught by Chen to instead store a L2P table in the temporary DRAM or SRAM storage (in addition to storing the CMB there), and to keep track of whether data is buffered/cached in the CMB using bits of the physical address in the L2P table as taught by Shen.
One of ordinary skill in the art would have been motivated to make this modification because it allows a controller to determine whether data is cached/buffered using the L2P and determine where the data is stored, without using additional or exclusive bits in the L2P mapping table, which allows a larger storage area to be recorded with the same number of bits as taught by Shen in [0039].
Chen does not explicitly disclose, but Thomas teaches wherein each of the plurality of entries as stored in the memory sub-system occupies a same size of storage resources (by teaching that using fixed-size mapping entries is easier to implement).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the logical-to-physical table entries as taught by Chen in view of Shen to be fixed-size entries that therefore each take up the same amount of storage resources as taught by Thomas.
One of ordinary skill in the art would have been motivated to make this modification because using fixed-size entries is easier to implement as taught by Thomas in [0004].
Regarding claim 11:
The memory sub-system of claim 10 is made obvious by Chen-Shen in further view of Thomas (Chen-Shen-Thomas).
Chen does not explicitly disclose, but Shen teaches, wherein each respective entry in the plurality of entries is configured with a bit-sized field configured to store a parameter indicative of whether or not the corresponding portion of the logical storage space mapped to the corresponding portion of the physical storage space has data buffered or cached in the memory space (by teaching that each entry in a L2P address mapping table (220) may be used to map logical addresses (of a logical storage space) to physical addresses of a physical space of the flash memory (S314) [Figs. 2-3] [0033]. However, depending on some bits of the physical address area of the L2P map (bit-sized field), the L2P map may also indicate whether or not data is in a temporary storage space in the controller and a physical address of the temporary storage space in the controller where the data is stored [0033-0044]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the FTL used for address translation and the block table used for keeping track of data in the cache as taught by Chen to instead store a L2P table in the temporary DRAM or SRAM storage (in addition to storing the CMB there), and to keep track of whether data is buffered/cached in the CMB using bits of the physical address in the L2P table as taught by Shen.
One of ordinary skill in the art would have been motivated to make this modification because it allows a controller to determine whether data is cached/buffered using the L2P and determine where the data is stored, without using additional or exclusive bits in the L2P mapping table, which allows a larger storage area to be recorded with the same number of bits as taught by Shen in [0039].
Regarding claim 12:
The memory sub-system of claim 11 is made obvious by Chen-Shen-Thomas.
Chen further discloses, wherein the corresponding portion of the logical storage space include a plurality of logical storage blocks addressable, by a host system outside of the memory sub-system, via a plurality of logical block addressing (LBA) addresses configured according to a standard of non-volatile memory express (NVMe) (by teaching that the memory device may be accessed with a plurality of LBAs, as there may be a plurality of LBAs in the block table (500) [0043], and there is typically one LBA per 4kb of data in the storage device, but other granularities may be used [0044]. The memory device implements a controller that implements a NVMe interface to the host device [0039-0040]).
Regarding claim 13:
The memory sub-system of claim 12 is made obvious by Chen-Shen-Thomas.
Chen further discloses, wherein the first entry is configured to map a first portion of the logical storage space; and wherein the location is addressable, by the host system, using a memory address in accordance with a standard for compute express link (CXL) or component interconnect express (PCIe) (by teaching that the memory device may be accessed with a plurality of LBAs, as there may be a plurality of LBAs in the block table (500) [0043], and there is typically one LBA per 4kb of data in the storage device, but other granularities may be used [0044]. The memory device implements a controller that implements a NVMe interface to the host device over a PCIe bus (with a standard for component interconnect express (PCIe) [0039-0040]).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chen-Shen-Thomas in further view of Jin.
Regarding claim 14:
The memory sub-system of claim 13 is made obvious by Chen-Shen-Thomas.
Chen does not explicitly disclose, but Jin teaches, wherein the controller is further configured to: sort the information to identify the location based on an identifier of the first portion; and search the information to identify the location based on the identifier of the first portion (by teaching that sorting mapping entries by a logical address order allows the map to be searched in a more efficient manner, such as with a binary search operation, which is more efficient than a sequential scan and allows for the map to be searched with less resources, in order to find an entry associated with the logical block address [0031] [0039] [0047] [0163] [0202]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the logical block address table as taught by Chen-Shen-Thomas to include being sorted by LBA, so that searching for an entry can use a more efficient searching algorithm as taught by Jin.
One of ordinary skill in the art would have been motivated to make this modification because it would allow the table to be searched with less resources as taught by Jin in [0047] [0202].
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chen-Shen-Thomas in further view of Jin in further view of Colline.
Regarding claim 15:
The memory sub-system of claim 14 is made obvious by Chen-Shen-Thomas in further view of Jin (Chen-Shen-Thomas-Jin).
Chen further discloses wherein the data portion is a portion of data stored in the first portion of the logical storage space (by teaching that in response to the read request, the data corresponding to each LBA L (a portion of data stored in the first portion of the logical storage space) may be read from the NAND, and stored in a buffer such as a command memory buffer (CMB) internal to the controller (302) [0037] [0044])).
Chen does not explicitly disclose, but Colline teaches and wherein a size of the data portion is smaller than a size of each of the plurality of logical storage blocks addressable respectively via the plurality of logical block addressing (LBA) addresses (by teaching that short block IO are common among AI workloads that operate on small data segments, such as data segments that are smaller than a NVMe devices minimum read size [0012]. To address the mismatch, the system can accumulate a plurality of short IO requests. the system can read the full block for each short I/O request and then discard the unwanted portions [0013]. A plurality of data for multiple short block I/O requests can then be accumulated so that the data for multiple requests can be returned to the host in one larger packed that combines multiple of the short block I/O request’s data together into the typical block size [0014]. The data requested by the short block I/O requests is smaller than the data read for a corresponding single LBA read [0025]).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified reading data to the buffer to satisfy host read requests as taught by Chen-Shen-Thomas-Jin to include being able to read data short block I/O data and accumulate the data (such as in the buffer as taught by Chen-Shen-Thomas-Jin) into a single block size for transfer to the host in a single packet as taught by Colline.
One of ordinary skill in the art would have been motivated to make this modification because it would allow the system to process the short block I/O requests that are commonly used by AI in an efficient manner as taught by Colline in [0012-0014]].
Response to Arguments/Amendments
In response to the amendments to the claims, the previous claim objections have been withdrawn.
In response to the amendments to the claims, the rejections have been updated to reflect the amended subject matter.
Applicant’s arguments have been fully considered, but are not persuasive.
Applicant argues that Chen does not disclose entries containing logical-to-physical address translations. However, this argument is not persuasive because it addresses Chen in isolation rather that the combination of references relied upon in the rejection. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
In particular, the rejection does not rely on Chen as teaching that its entries contain logical-to-physical translations. Rather, Chen is relied upon for teaching entries in a cache management data structure that include logical addresses and a DV indicator indicating whether the corresponding data is cached or buffered in the CMB (a memory space). Medeiros and Shen are relied upon for teaching the inclusion of corresponding physical addresses and for rendering obvious the modification of Chen’s block table to include such physical addresses, thereby providing logical-to-physical address translations.
Applicant generally asserts that the additional references do not cure the alleged deficiencies in Chen, but does not identify any deficiency in the teachings of Medeiros and Shen or the Examiner’s stated rationale for modifying Chen’s entries to include physical addresses. Accordingly, Applicant’s argument attacks Chen individually and does not address the rejection as actually presented.
The argument is therefore not persuasive, the 35 USC §103 rejection of the claims has been updated to reflect the amendments to the claims, and the claims are not indicated as allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US Patent Application Publication No. US 2011/0055458 A1 (Kuehne) – teaches a cache flag indicating if the requested logical page is present in the page buffer cache (415), which is a cache used to temporarily store data being sent to/from the host and ]the flash memory [0027] [0081-0082] [0086] [Figs. 5-7]. The cache flag will indicate whether the location pointed to by the logical to physical address table (400) points to the location of the page in the page buffer cache or in the flash memory [0027] [0081-0082] [0086] [Figs. 5-7].
US Patent Application Publication No. US 2017/0003881 A1 (Amidi)– teaches flags of an entry of an L2P table that may be used to determine if the data corresponding to the entry should be retrieved from the volatile (i.e. cache) memory or the non-volatile memory [0044].
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/CURTIS JAMES KORTMAN/ Primary Examiner, Art Unit 2139
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