Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. This office acknowledges receipt of the following item(s) from the Applicant:
Information Disclosure Statement (IDS) was considered.
2. Claims 1-20 are presented for examination.
Double Patenting
3. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. See In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970);and, In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent is shown to be commonly owned with this application. See 37 CFR 1.130(b).
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to
www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
4. Claims 1-20 are rejected under the judicially created doctrine of obviousness-type double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12249367. Although the conflicting claims are not identical, they are not patentably distinct from each other because the examined application claim is either anticipated by, or would have been obvious over, the reference claims as follows:
Claims 1-9 of the examined application are anticipated and the same scope of invention by claims 1-9 of the reference such as a device, comprising: a memory cell configured to operate with a first supply voltage and a second supply voltage different from the first supply voltage; and a first write assist circuit comprising: a first write assist switch operating in response to a first control signal; and a second write assist switch operating in response to a second control signal and being coupled to the memory cell and the first write assist switch through a first data line, wherein in a read operation of the memory cell the second control signal is floating.
Claims 10-13 and 15-16 of the examined application are anticipated and the same scope of invention by claims 10-16 of the reference such as a method, comprising: generating, according to a read enable signal and a logic value of a data being written into a memory cell, first to fourth control signals to first to fourth write assist switches, wherein the memory cell is coupled to the first and third write assist switches at a first node and coupled to the second and fourth write assist switches at a second node; in a write operation of the data having a first logic value, charging a first data line to have a voltage level of a first voltage by turning on a first write assist switch in response to the first control signal, and discharging a second data line to have a voltage level of a second voltage by turning on a second write assist switch in response to the second control signal; and in a read operation of the memory cell, turning off the first write assist switch in response to the first control signal and the fourth write assist switch in response to the fourth control signal, wherein the first control signal and the fourth control signal have the same logic value, and the second control signal and the third control signal have the same state.
Claim 14 is obvious to a claim 1 of the reference for a floating limitation.
Claims 17-20 of the examined application are anticipated and the same scope of invention by claims 17-20 of the reference such as a device, comprising: a plurality of memory cells arranged in a plurality of memory columns; and a plurality of pairs of first and second write assist circuits each pair arranged in one of the plurality of memory columns, wherein in each pair of the first and second write assist circuits, the first write assist circuit comprises: a first transistor coupled between a first supply voltage terminal and a first data line; and a second transistor coupled between a second supply voltage terminal and the first data line, wherein the second write assist circuit comprises: a third transistor coupled between the first supply voltage terminal and a second data line; and a fourth transistor coupled between the second supply voltage terminal and the second data line, wherein in a write operation to a cell in the plurality of memory cells, the first transistor and the second transistor are configured to operating in response to a first control signal and a second control signal that have a same logic state, wherein in a read operation to the cell, the first transistor is turned off in response to the first control signal and the second transistor is turned off in response to the second control signal having state different from that of the first control signal.
5. When responding to the office action, Applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner to locate the appropriate paragraphs.
6. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the date of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V HO whose telephone number is (571) 272-1777. The examiner can normally be reached 7:00 AM -- 5:30 PM from Thursday and Friday of the first week of a bi-week and Tuesday and Wednesday of the second week.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached on (571) 272-1852. The fax phone number for the organization where this application or proceeding is assigned is (571)-273-8300.
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/HOAI V HO/Primary Examiner, Art Unit 2827
