DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-6, 12-13, 18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Marathe et al. (US 9606937 B1) hereinafter Marathe et al.
Regarding claim 1, Marathe et al. teaches a memory device, comprising:
one or more components configured to:
access a first set of data stored in a first memory component (a read of or write to block 205(1) was made during interval of time 230 Column 5, Lines 1-20);
update a first access counter associated with the first memory component based on accessing the first set of data (block 205(1) which is resident on storage volume 210 is associated with an access count 265(1) Column 5, Lines 1-20);
determine whether the first access counter satisfies a first value of an access counter threshold (access count module determines access count 265(1) of block 205(1) and compares access count with threshold access frequency to determine whether it matches or exceeds the frequency Column 5, Lines 12-24);
update a value of the access counter threshold to a second value (with the insertion of block 205(1) into cache, threshold access frequency module determines the changes caused to cache Column 5, Lines 22-32, and threshold access frequency 220 based on cache pressure/occupancy can be adjusted Column 6, Lines 22-47. For example, during interval of time T2, the threshold frequency can be increased to 3 as shown in Fig. 3A);
access a second set of data stored in a second memory component (a read of or write to block 205(1)-(3) was made during interval of time 230 Column 5, Lines 1-20);
update a second access counter associated with the second memory component based on accessing the second set of data (block 205(1)-(3) which is resident on storage volume 210 is associated with an access count 265 Column 5, Lines 1-20); and
determine whether the second access counter satisfies the second value of the access counter threshold (it can be determined that blocks 205(2) and 205(3) have high access frequencies and are inserted based on the adjusted threshold access frequency Column 7, Lines 6-20).
Regarding claim 4, Marathe et al. teaches all of the features of claim 1, as outline above.
Marathe et al. further teaches wherein the one or more components are further configured to: determine that a time period has elapsed; and set the value of the access counter threshold to a third value based on determining that the time period has elapsed, wherein the third value is one of: a default value of the access counter threshold, a current value of the access counter threshold reduced according to a reduction factor, or the current value of the access counter threshold (a threshold value is adjusted based on a varied interval of time proportion to cache pressure, for example, if the cache is nearly empty and has lots of free space, there is no need to re-adjust threshold access frequency, or in other words, the third value is kept at the current value Column 9, Lines 39-49).
Regarding claim 5, Marathe et al. teaches all of the features of claim 1, as outline above.
Marathe et al. further teaches wherein the one or more components are further configured to receive configuration information associated with the access counter threshold, and wherein the configuration information indicates at least one of: enablement of dynamic adjustment of the access counter threshold, a beginning value of the access counter threshold, an adjustment policy for the access counter threshold, a reset policy for the access counter threshold (the value of threshold access frequency 220 can be determined dynamically based on cache pressure and historical information Column 8, Lines 9-21).
Regarding claim 6, Marathe et al. teaches all of the features of claim 1, as outline above.
Marathe et al. further teaches wherein the one or more components are further configured to determine that the first access counter satisfies the first value, and wherein the one or more components, to determine the second value, are configured to add an integer to the first value based on determining that the first access counter satisfies the first value (with the insertion of block 205(1) into cache, threshold access frequency module determines the changes caused to cache Column 5, Lines 22-32, and threshold access frequency 220 based on cache pressure/occupancy can be adjusted Column 6, Lines 22-47. For example, during interval of time T2, the threshold frequency can be increased to 3 as shown in Fig. 3A).
Claims 12 and 18 are rejected under 35 USC 102(a)(1) for the same reasons as claim 1, as outlined above.
Claim 13 is rejected under 35 USC 102(a)(1) for the same reasons as claim 6, as outlined above.
Claim 20 is rejected under 35 USC 102(a)(1) for the same reasons as claim 4, as outlined above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-3 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marathe et al. in view of Ramamoorthy et al. (US 2015/0046142 A1) hereinafter Ramamoorthy et al.
Regarding claim 2, Marathe et al. teaches all of the features of claim 1, as outline above.
Marathe et al. further teaches wherein the one or more components are further configured to: determine that at least one of the first access counter satisfies the first value or the second access counter satisfies the second value; and add at least one of a first identifier of the first memory component or a second identifier of the second memory component to a … data structure based on determining that the at least one of the first access counter satisfies the first value or the second access counter satisfies the second value (it can be determined that blocks 205(2) and 205(3) have high access frequencies and are inserted based on the adjusted threshold access frequency Column 7, Lines 6-20).
Marathe et al. does not appear to explicitly teach, however, Ramamoorthy et al. teaches wherein the data structure is a first-in-first-out data structure (a FIFO cache of a certain size can be simulated and cache accesses can be tracked Paragraph [0026]-[0027]).
The disclosures of Marathe et al. and Ramamoorthy et al., hereinafter MR, are analogous art to the claimed invention because they are in the same field of cache/buffer management in a memory system. Because both MR teach the use of tracking I/O access to data structure (ex. to a cache of Marathe et al.), it would have been obvious to one skilled in the art to substitute one specific type of cache algorithm to achieve the predictable result of availability of data stored in a cache following a particular type of algorithm as disclosed by Ramamoorthy et al., in this case, a FIFO cache (KSR, MPEP 2143).
Regarding claim 3, Marathe et al. teaches all of the features of claim 1, as outline above.
Marathe et al. further teaches wherein the one or more components are further configured to: determine that at least one of the first access counter does not satisfy the first value or the second access counter does not satisfy the second value; and refrain from adding at least one of a first identifier of the first memory component or a second identifier of the second memory component to a … data structure based on determining that the at least one of the first access counter does not satisfy the first value or the second access counter does not satisfy the second value (blocks may be considered a candidate for inclusion into the cache, but ultimately may not be inserted into the cache if the access frequency of these blocks are not equal or greater than the threshold access frequency Column 9, Lines 28-34).
Marathe et al. does not appear to explicitly teach, however, Ramamoorthy et al. teaches wherein the data structure is a first-in-first-out data structure (a FIFO cache of a certain size can be simulated and cache accesses can be tracked Paragraph [0026]-[0027]).
The disclosures of Marathe et al. and Ramamoorthy et al., hereinafter MR, are analogous art to the claimed invention because they are in the same field of cache/buffer management in a memory system. Because both MR teach the use of tracking I/O access to data structure (ex. to a cache of Marathe et al.), it would have been obvious to one skilled in the art to substitute one specific type of cache algorithm to achieve the predictable result of availability of data stored in a cache following a particular type of algorithm as disclosed by Ramamoorthy et al., in this case, a FIFO cache (KSR, MPEP 2143).
Claim 19 is rejected under 35 USC 103 for the same reasons as claim 2, as outlined above.
Allowable Subject Matter
Claims 7-11 and 14-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 7, “wherein the one or more components are further configured to determine that the first access counter satisfies the first value, and wherein the one or more components, to determine the second value, are configured to determine a ceiling of an average of the first value and a value of the first access counter,” is not taught by the prior art of record. The closest prior art is Marathe et al. in view of Bozman (EP 0659923 A2). Bozman et al. generally discusses determining a data cache ceiling size, however, is silent with regards to the remaining limitations discussed above.
Regarding claim 8, “wherein the one or more components are further configured to determine that the first access counter satisfies the first value, and wherein the one or more components, to determine the second value, are configured to determine a maximum of the first value and a value of the first access counter,” is not taught by the prior art of record. The closest prior art is Marathe et al. which discusses incrementing or decrementing a previous threshold value to determine the second value, but is silent with regards to determining the second value based on a maximum of the first value and first access counter value.
Regarding claim 9, “wherein the one or more components, to determine the second value, are configured to determine a ceiling of an average of the first value and a value of the first access counter,” is not taught by the prior art of record. The closest prior art is Marathe et al. in view of Bozman (EP 0659923 A2). Bozman et al. generally discusses determining a data cache ceiling size, however, is silent with regards to the remaining limitations discussed above.
Regarding claim 10, “wherein the one or more components, to determine the second value, are configured to determine a ceiling of an average of values of multiple access counters associated with multiple memory components,” is not taught by the prior art of record. The closest prior art is Marathe et al. in view of Bozman (EP 0659923 A2). Bozman et al. generally discusses determining a data cache ceiling size, however, is silent with regards to the remaining limitations discussed above. Claim 11 depends upon claim 10, thus, would be allowable for the same reasons discussed above.
Claim 14 recites subject matter substantially similar to that of claim 7 and would be allowable for the same reasons as claim 7, as discussed above.
Claim 15 recites subject matter substantially similar to that of claim 8 and would be allowable for the same reasons as claim 8, as discussed above.
Claim 16 recites subject matter substantially similar to that of claim 9 and would be allowable for the same reasons as claim 9, as discussed above.
Claim 17 recites subject matter substantially similar to that of claim 10 and would be allowable for the same reasons as claim 10, as discussed above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liu et al. (US 2020/0333981 A1) teaches using an average of access counts of memory objections in a DRAM domain for adjusting a hotness threshold.
Tang et al. (US 2023/0359360 A1) teaches counting access operations to memory locations of different memory arrays and determining an exponential moving average of the number of access operations.
McGlaughlin (US 2020/0104263 A1) teaches using a data structure to track accesses, where an access counter is incrementable in response to performing a memory management operation.
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JANE W. BENNER
Primary Examiner
Art Unit 2131
/JANE W BENNER/Primary Examiner, Art Unit 2139