DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or
nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) [ 1-6, 13-18, 20 ] are rejected under 35 U.S.C. 103 as being unpatentable over [ Yu et al. (US 11928343), hereinafter "Yu", in view of Parry et al. (US 10838807), hereinafter "Parry"].
As per claim 1, Yu significantly teaches a memory controller comprising ( FIG. 9 is a block diagram illustrating an embodiment of an example memory controller 910 external to a set of memory dies. [Yu PP 0071]):
a memory interface configured to perform a data input/output operation of transmitting/receiving data to/from a memory device through an input/output line (interface 915 [Yu PP 0071], FIG. 2 illustrates an embodiment of an example memory die 205-1 coupled to a processing device 210 via an interface 215. [Yu PP 0027]);
a power manager configured to monitor a peak current period of the data input/output operation, and generate peak sensing information when the peak current period is sensed (a PPM manager can be structured to monitor key circuit blocks or a command state machine to detect cache write operation start and finish in a data path for writing. Additionally, the PPM manager can be structured to monitor key circuit blocks or the command state machine to detect a cache read operation start and finish for reading. [Yu PP 0024], a first flag received from a data path identifying start of a cache operation" and "a second flag received from the data path identifying an end of the cache operation. [Yu PP 0084]);
Yu does not explicitly teach “and an Error Correction Code (ECC) engine configured to perform an error correction operation on the data while the data input/output operation is performed, and control a speed of the error correction operation in the peak current period in response to the peak sensing information.”
However, Parry, in an analogous art, teaches and an Error Correction Code (ECC) engine configured to perform an error correction operation on the data while the data input/output operation is performed, and control a speed of the error correction operation in the peak current period in response to the peak sensing information (dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device. [Parry PP 0018], The present subject matter lowers ECC power and frequency using a variety of methods, including: using a clock frequency control; using a voltage level control. [Parry PP 0017]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the peak current monitoring and flag-generating system disclosed by Yu to incorporate Parry's teaching of dynamically adjusting ECC clock frequency and voltage in response to the peak sensing information, in order to reduce peak power consumption and improve overall power efficiency in memory systems (dynamically adjusting error correcting code (ECC) voltages and frequencies ... to regulate power loss" [Parry PP 0014]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Yu's invention.
As per claim 2, Yu does not explicitly teach “wherein the ECC engine decreases the speed of the error correction operation in the peak current period, and increases the speed of the error correction operation after the peak current period.”
However, Parry, in an analogous art, teaches wherein the ECC engine decreases the speed of the error correction operation in the peak current period, and increases the speed of the error correction operation after the peak current period (The present system dynamically adjusts voltage for ECC logic in the memory controller between 0.7 and 1.0 Volts. ... The present system adjusts frequency for ECC logic in the memory controller between 100 MHz and 1000 MHz [Parry PP 0030], lowers ECC power and frequency [Parry PP 0017] by implication, restores/increases them when conditions allow).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the peak current monitoring and flag-generating system disclosed by Yu to incorporate Parry's teaching of dynamically adjusting ECC clock frequency and voltage in response to the peak sensing information, in order to reduce peak power consumption and improve overall power efficiency in memory systems (dynamically adjusting error correcting code (ECC) voltages and frequencies ... to regulate power loss" [Parry PP 0014]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Yu's invention.
As per claim 3, Yu does not explicitly teach “wherein the ECC engine sets the speed of the error correction operation lower than a default speed in the peak current period, and sets the speed of the error correction operation higher than the default speed after the peak current period.”
However, Parry, in an analogous art, teaches wherein the ECC engine sets the speed of the error correction operation lower than a default speed in the peak current period, and sets the speed of the error correction operation higher than the default speed after the peak current period (The present system dynamically adjusts voltage for ECC logic in the memory controller between 0.7 and 1.0 Volts. ... The present system adjusts frequency for ECC logic in the memory controller between 100 MHz and 1000 MHz [Parry PP 0030] A default operating point is inherent, and adjusting down or up from that default is expressly taught by "dynamically adjusts" and the exemplary ranges).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the peak current monitoring and flag-generating system disclosed by Yu to incorporate Parry's teaching of dynamically adjusting ECC clock frequency and voltage in response to the peak sensing information, in order to reduce peak power consumption and improve overall power efficiency in memory systems (dynamically adjusting error correcting code (ECC) voltages and frequencies ... to regulate power loss" [Parry PP 0014]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Yu's invention.
As per claim 4, Yu does not explicitly teach “wherein the ECC engine decreases a frequency of the error correction operation in the peak current period, and increases the frequency of the error correction operation after the peak current period.”
However, Parry, in an analogous art, teaches wherein the ECC engine decreases a frequency of the error correction operation in the peak current period, and increases the frequency of the error correction operation after the peak current period (using a clock frequency control [Parry PP 0017] to lower ECC power, adjusts frequency for ECC logic ... between 100 MHz and 1000 MHz [Parry PP 0030] inherently scaling down during high-demand periods and up afterward.).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the peak current monitoring and flag-generating system disclosed by Yu to incorporate Parry's teaching of dynamically adjusting ECC clock frequency and voltage in response to the peak sensing information, in order to reduce peak power consumption and improve overall power efficiency in memory systems (dynamically adjusting error correcting code (ECC) voltages and frequencies ... to regulate power loss" [Parry PP 0014]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Yu's invention.
As per claim 5, Yu does not explicitly teach “wherein the ECC engine sets the frequency of the error correction operation lower than a default frequency in the peak current period, and sets the frequency of the error correction operation higher than the default frequency after the peak current period.”
However, Parry, in an analogous art, teaches wherein the ECC engine sets the frequency of the error correction operation lower than a default frequency in the peak current period, and sets the frequency of the error correction operation higher than the default frequency after the peak current period (adjusts frequency for ECC logic ... between 100 MHz and 1000 MHz [Parry PP 0030] dynamic frequency adjustment relative to a nominal/default operating point).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the peak current monitoring and flag-generating system disclosed by Yu to incorporate Parry's teaching of dynamically adjusting ECC clock frequency and voltage in response to the peak sensing information, in order to reduce peak power consumption and improve overall power efficiency in memory systems (dynamically adjusting error correcting code (ECC) voltages and frequencies ... to regulate power loss" [Parry PP 0014]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Yu's invention.
As per claim 6, Yu significantly teaches wherein the ECC engine performs the error correction operation after the peak current period (PPM logic management can be structured to manage cache operations in a memory die in combination with memory array operations of the memory die and can be structured to provide feedback to a system memory controller to slow down a working frequency of an interface coupling the system memory controller to the memory die, based on the PPM logic management managing a current budget. The slowdown of the working frequency of the interface can be performed to reduce current operations of a cache of the memory die, if the PPM calculated total peak power budget will exceed system peak power budget. [Yu PP 0052], The memory controller 230 waits until it receives a signal to proceed from the PPM logic management 220-1 before executing code in the instructions 232 that cause ICC peaks in memory array operation of the memory die 205-1. [Yu PP 0038]).
As per claim 13, Yu significantly teaches wherein the power manager monitors a consumed current of the data input/output operation through a status check of the input/output line (The PPM logic management 220-1 uses the flags for the write cache operation and the read cache operation as a determination that current is being used in the respective cache operation. [Yu PP 0035] The flags are generated from the data path (I/O line), and using them to determine current consumption constitutes a status check of the input/output line).
As per claim 14, Yu does not explicitly teach “wherein the ECC engine includes: an ECC encoder configured to perform error correction encoding on a program data transmitted to the memory device; and an ECC decoder configured to perform error correction decoding on a read data received from the memory device, and wherein the error correction operation includes the error correction encoding and the error correction decoding.”
However, Parry, in an analogous art, teaches wherein the ECC engine includes: an ECC encoder configured to perform error correction encoding on a program data transmitted to the memory device (using ECC generation logic (for encoding) [Parry PP 0017]);
and an ECC decoder configured to perform error correction decoding on a read data received from the memory device, and wherein the error correction operation includes the error correction encoding and the error correction decoding (that runs at a different voltage than ECC checking logic (for decoding) [Parry PP 0017]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the peak current monitoring and flag-generating system disclosed by Yu to incorporate Parry's teaching of dynamically adjusting ECC clock frequency and voltage in response to the peak sensing information, in order to reduce peak power consumption and improve overall power efficiency in memory systems (dynamically adjusting error correcting code (ECC) voltages and frequencies ... to regulate power loss" [Parry PP 0014]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Yu's invention.
As per claim 15, Yu significantly teaches wherein the memory interface performs the data input/output operation using a plurality of memory devices and a plurality of channels, and wherein at least one channel from among the plurality of channels shares any one ECC engine from among a plurality of ECC engines (FIG. 1 illustrates an embodiment of an example relationship of a memory device package 103 ... The memory device package 103 includes memory dies 105-1, 105-2, 105-3, 105-4, 105-5, 105-6, 105-7, and 105-8 … the memory device package of memory dies has two channels. [Yu PP 0025] Sharing an ECC engine across channels is a predictable implementation of a multi-channel memory system).
As per claim 16, Yu significantly teaches a method of operating a memory controller, the method comprising: performing a data input/output operation of transmitting/receiving data to/from a memory device through an input/output line (interface 915 [Yu PP 0071], memory die 205-1 coupled to a processing device 210 via an interface 215 [Yu PP 0027]);
monitoring a peak current period of the data input/output operation, and generating peak sensing information when the peak current period is sensed (a PPM manager can be structured to monitor key circuit blocks or a command state machine to detect cache write operation start and finish in a data path for writing. Additionally, the PPM manager can be structured to monitor key circuit blocks or the command state machine to detect a cache read operation start and finish for reading [Yu PP 0024], a first flag received from a data path identifying start of a cache operation … a second flag received from the data path identifying an end of the cache operation [Yu PP 0084]);
Yu does not explicitly teach “performing an error correction operation on the data while the data input/output operation is performed; controlling a speed of the error correction operation in the peak current period in response to the peak sensing information.”
However, Parry, in an analogous art, teaches performing an error correction operation on the data while the data input/output operation is performed (dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device [Parry PP 0018]);
controlling a speed of the error correction operation in the peak current period in response to the peak sensing information (dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device [Parry PP 0018]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the peak current monitoring and flag-generating system disclosed by Yu to incorporate Parry's teaching of dynamically adjusting ECC clock frequency and voltage in response to the peak sensing information, in order to reduce peak power consumption and improve overall power efficiency in memory systems (dynamically adjusting error correcting code (ECC) voltages and frequencies ... to regulate power loss" [Parry PP 0014]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Yu's invention.
As per claim 17, Yu does not explicitly teach “wherein the controlling of the speed of the error correction operation includes: decreasing the speed of the error correction operation in the peak current period; and increasing the speed of the error correction operation after the peak current period.”
However, Parry, in an analogous art, teaches wherein the controlling of the speed of the error correction operation includes: decreasing the speed of the error correction operation in the peak current period (The present subject matter lowers ECC power and frequency using a variety of methods, including: using a clock frequency control; using a voltage level control [Parry PP 0017]);
and increasing the speed of the error correction operation after the peak current period (The present system dynamically adjusts voltage for ECC logic in the memory controller between 0.7 and 1.0 Volts. ... The present system adjusts frequency for ECC logic in the memory controller between 100 MHz and 1000 MHz. [Parry PP 0030]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the peak current monitoring and flag-generating system disclosed by Yu to incorporate Parry's teaching of dynamically adjusting ECC clock frequency and voltage in response to the peak sensing information, in order to reduce peak power consumption and improve overall power efficiency in memory systems (dynamically adjusting error correcting code (ECC) voltages and frequencies ... to regulate power loss" [Parry PP 0014]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Yu's invention.
As per claim 18, Yu does not explicitly teach “wherein the controlling of the speed of the error correction operation includes: decreasing a frequency of the error correction operation in the peak current period; and increasing the frequency of the error correction operation after the peak current period.”
However, Parry, in an analogous art, teaches wherein the controlling of the speed of the error correction operation includes: decreasing a frequency of the error correction operation in the peak current period (using a clock frequency control [Parry PP 0017]); and
increasing the frequency of the error correction operation after the peak current period (The present system adjusts frequency for ECC logic in the memory controller between 100 MHz and 1000 MHz [Parry PP 0030]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the peak current monitoring and flag-generating system disclosed by Yu to incorporate Parry's teaching of dynamically adjusting ECC clock frequency and voltage in response to the peak sensing information, in order to reduce peak power consumption and improve overall power efficiency in memory systems (dynamically adjusting error correcting code (ECC) voltages and frequencies ... to regulate power loss" [Parry PP 0014]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Yu's invention.
As per claim 20, Yu significantly teaches a method of operating a memory controller, the method comprising: performing a data input/output operation of transmitting/receiving data to/from a memory device through an input/output line (interface 915 [Yu PP 0071], memory die 205-1 coupled to a processing device 210 via an interface 215 [Yu PP 0027]);
monitoring a peak current period of the data input/output operation, and generating peak sensing information when the peak current period is sensed (a PPM manager can be structured to monitor key circuit blocks or a command state machine to detect cache write operation start and finish in a data path for writing. Additionally, the PPM manager can be structured to monitor key circuit blocks or the command state machine to detect a cache read operation start and finish for reading. [Yu PP 0024], first flag received from a data path identifying start of a cache operation … a second flag received from the data path identifying an end of the cache operation [Yu PP 0084]);
Yu does not explicitly teach “performing an error correction operation on the data after the peak current period.”
However, Parry, in an analogous art, teaches performing an error correction operation on the data after the peak current period (dynamically adjusting at least one of a clock frequency and a voltage level of an error-correcting code (ECC) subsystem of the memory controller based on the at least one parameter to control power usage of the host device [Parry PP 0018]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the peak current monitoring and flag-generating system disclosed by Yu to incorporate Parry's teaching of dynamically adjusting ECC clock frequency and voltage in response to the peak sensing information, in order to reduce peak power consumption and improve overall power efficiency in memory systems (dynamically adjusting error correcting code (ECC) voltages and frequencies ... to regulate power loss" [Parry PP 0014]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Yu's invention.
Claim(s) [ 7-12, 19, 21] are rejected under 35 U.S.C. 103 as being unpatentable over [ Yu, in view of Parry, in further view Bazarsky et al. (US Pub No. 20170269991), hereinafter "Bazarsky" ].
As per claim 7, Yu in view of Parry do not explicitly teach “wherein the ECC engine checks an error level of the data, and controls the speed of the error correction operation in the peak current period according to the error level”
However, Bazarsky, in an analogous art, teaches wherein the ECC engine checks an error level of the data, and controls the speed of the error correction operation in the peak current period according to the error level (when the BER estimate 124 for a codeword or sub code is less than the first threshold 131, the DPMU 130 may skip transfer of soft bit data for the codeword or sub code (e.g., the request 118 may not be sent) and may select the ULP mode 126 as the initial decoding mode 134. [Bazarsky PP 0038], when the BER estimate 124 is greater than or equal to the third threshold 133, the DPMU 130 may request soft bit data for the codeword or sub code (e.g., via the request 118) and may select the FP mode 128 as the initial decoding mode 134. [Bazarsky PP 0041] These modes have different speeds/power consumption).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the peak current monitoring system of Yu and Parry to incorporate Bazarsky's teaching of selecting ECC modes based on error level, in order to optimize power consumption based on data quality and further improve overall power efficiency in memory systems (operations based on bit error rate (BER) [Bazarsky PP 0036]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Yu's invention.
As per claim 8, Yu in view of Parry do not explicitly teach “wherein, when the error level is a reference value or less, the ECC engine sets the speed of the error correction operation as a default speed in the peak current period.”
However, Bazarsky, in an analogous art, teaches wherein, when the error level is a reference value or less, the ECC engine sets the speed of the error correction operation as a default speed in the peak current period (when the BER estimate 124 for a codeword or sub code is less than the first threshold 131, the DPMU 130 may skip transfer of soft bit data for the codeword or sub code (e.g., the request 118 may not be sent) and may select the ULP mode 126 as the initial decoding mode 134. [Bazarsky PP 0038] In the context of the combination, the ULP mode corresponds to a lower-power/default speed setting).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the peak current monitoring system of Yu and Parry to incorporate Bazarsky's teaching of selecting ECC modes based on error level, in order to optimize power consumption based on data quality and further improve overall power efficiency in memory systems (operations based on bit error rate (BER) [Bazarsky PP 0036]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Yu's invention.
As per claim 9, Yu does not explicitly teach “wherein, which the error level is higher than the reference value, the ECC engine sets the speed of the error correction operation lower than the default speed in the peak current period.”
However, Parry, in an analogous art, teaches wherein, which the error level is higher than the reference value, the ECC engine sets the speed of the error correction operation lower than the default speed in the peak current period (The present subject matter lowers ECC power and frequency using a variety of methods, including: using a clock frequency control; using a voltage level control [Parry PP 0017] lowering ECC speed (clock frequency/voltage) to reduce power consumption during constrained periods).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the peak current monitoring and flag-generating system disclosed by Yu to incorporate Parry's teaching of dynamically adjusting ECC clock frequency and voltage in response to the peak sensing information, in order to reduce peak power consumption and improve overall power efficiency in memory systems (dynamically adjusting error correcting code (ECC) voltages and frequencies ... to regulate power loss" [Parry PP 0014]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Yu's invention.
As per claim 10, Yu in view of Parry do not explicitly teach “wherein, when the error level is a reference value or less, the ECC engine sets a frequency of the error correction operation as a default frequency in the peak current period.”
However, Bazarsky, in an analogous art, teaches wherein, when the error level is a reference value or less, the ECC engine sets a frequency of the error correction operation as a default frequency in the peak current period (The ECC decoder 125 may support decoding operations in an ultra-low power (ULP) mode 126, a low-power (LP) mode 127, and a full power (FP) mode 128. [Bazarsky PP 0034] The ULP mode inherently operates at a lower/default frequency compared to higher modes).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the peak current monitoring system of Yu and Parry to incorporate Bazarsky's teaching of selecting ECC modes based on error level, in order to optimize power consumption based on data quality and further improve overall power efficiency in memory systems (operations based on bit error rate (BER) [Bazarsky PP 0036]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Yu's invention.
As per claim 11, Yu does not explicitly teach “wherein, when the error level is higher than the reference value, the ECC engine sets the frequency of the error correction operation lower than the default frequency in the peak current period.”
However, Parry, in an analogous art, teaches wherein, when the error level is higher than the reference value, the ECC engine sets the frequency of the error correction operation lower than the default frequency in the peak current period (The present system adjusts frequency for ECC logic in the memory controller between 100 MHz and 1000 MHz [Parry 0030] The range of 100 MHz to 1000 MHz implies a nominal/default frequency).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the peak current monitoring and flag-generating system disclosed by Yu to incorporate Parry's teaching of dynamically adjusting ECC clock frequency and voltage in response to the peak sensing information, in order to reduce peak power consumption and improve overall power efficiency in memory systems (dynamically adjusting error correcting code (ECC) voltages and frequencies ... to regulate power loss" [Parry PP 0014]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Yu's invention.
As per claim 12, Yu significantly teaches wherein, when the error level is higher a reference value, the ECC engine performs the error correction operation after the peak current period (The memory controller 230 waits until it receives a signal to proceed from the PPM logic management 220-1 before executing code in the instructions 232 that cause ICC peaks in memory array operation of the memory die 205-1.[Yu PP 0038] deferring peak-causing operations until the PPM logic gives permission to proceed).
As per claim 19, Yu does not explicitly teach “wherein the controlling of the speed of the error correction operation includes: checking an error level of the data; and decreasing the speed of the error correction operation in the peak current period when the error level is higher than a reference value.”
However, Parry, in an analogous art, teaches decreasing the speed of the error correction operation in the peak current period when the error level is higher than a reference value (The present subject matter lowers ECC power and frequency using a variety of methods, including: using a clock frequency control; using a voltage level control [Parry PP 0017]).
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the peak current monitoring and flag-generating system disclosed by Yu to incorporate Parry's teaching of dynamically adjusting ECC clock frequency and voltage in response to the peak sensing information, in order to reduce peak power consumption and improve overall power efficiency in memory systems (dynamically adjusting error correcting code (ECC) voltages and frequencies ... to regulate power loss" [Parry PP 0014]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Yu's invention.
Yu in view of Parry do not explicitly teach “wherein the controlling of the speed of the error correction operation includes: checking an error level of the data;”
However, Bazarsky, in an analogous art, teaches wherein the controlling of the speed of the error correction operation includes: checking an error level of the data (when the BER estimate 124 for a codeword or sub code is less than the first threshold 131, the DPMU 130 may skip transfer of soft bit data for the codeword or sub code (e.g., the request 118 may not be sent) and may select the ULP mode 126 as the initial decoding mode 134. [Bazarsky PP 0038] This teaches checking the error level by comparing BER to thresholds);
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the peak current monitoring system of Yu and Parry to incorporate Bazarsky's teaching of selecting ECC modes based on error level, in order to optimize power consumption based on data quality and further improve overall power efficiency in memory systems (operations based on bit error rate (BER) [Bazarsky PP 0036]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Yu's invention.
As per claim 21, Yu significantly teaches performing the error correction operation after the peak current period when the error level is higher than a reference value (The memory controller 230 waits until it receives a signal to proceed from the PPM logic management 220-1 before executing code in the instructions 232 that cause ICC peaks in memory array operation of the memory die 205-1 [Yu PP 0038]).
Yu in view of Parry do not explicitly teach “wherein the performing of the error correction operation includes: checking an error level of the data;”
However, Bazarsky, in an analogous art, teaches wherein the performing of the error correction operation includes: checking an error level of the data (When the BER estimate 124 is greater than or equal to the third threshold 133 , the DPMU 130 may request soft bit data for the codeword or sub code (e.g., via the request 118 ) and may select the FP mode 128 as the initial decoding mode 134 [Bazarsky PP 0041]);
Therefore, it would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the peak current monitoring system of Yu and Parry to incorporate Bazarsky's teaching of selecting ECC modes based on error level, in order to optimize power consumption based on data quality and further improve overall power efficiency in memory systems (operations based on bit error rate (BER) [Bazarsky PP 0036]). Applying these teachings would have been a predictable variation for someone of ordinary skill in the art to Yu's invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM FUAD ALHWAMDEH whose telephone number is (571)272-5501. The examiner can normally be reached Mon-Fri 7:30-5:00.
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/KAREEM FUAD ALHWAMDEH/Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112
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