DETAILED ACTION
Claims 1-20 are pending in this action.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-7, 10-16 and 19 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims claims 1-19 of U.S. Patent No. 11,494,522 [hereinafter ‘522] and 1-19 of U.S. Patent No. 12,216,806 [hereinafter ‘806]. Although the claims at issue are not identical, they are not patentably distinct from each other because:
1. A method of operating a memory device, comprising: detecting a predefined event of the memory device [See ‘522 claim 1 and ‘806 claim 1]; counting a quantity of clock cycles in response to detecting the predefined event [See ‘522 claim 1 and ‘806 claim 1]; temporarily disabling a circuit configured to access a fuse array of the memory device based on counting the quantity of clock cycles [See ‘522 claim 1 and ‘806 claim 1].
2. The method of claim 1, further comprising: storing a threshold number of clock cycles in the memory device [See ‘522 claim 5 and ‘806 claim 5].
3. The method of claim 2, further comprising: comparing the counted quantity of clock cycles with the threshold number ; and determining the counted quantity of clock cycles is greater than or equal to the threshold number [See ‘522 claim 3 and ‘806 claim 3].
4. The method of claim 1, further comprising: pausing counting the quantity of clock cycles when the circuit is activated to access the fuse array of the memory device [See ‘522 claim 1 and ‘806 claim 1].
5. The method of claim 4, further comprising: resuming counting the quantity of clock cycles when the circuit is deactivated after accessing the fuse array of the memory device [See ‘522 claim 6 and ‘806 claim 6].
6. The method of claim 1, wherein: the predefined event corresponds to a specific sequence of commands directed to the memory device [See ‘522 claim 7 and ‘806 claim 7].
7. The method of claim 1, wherein: the predefined event corresponds to a voltage supplied to the memory device exceeding a portion of an operating voltage of the memory device [See ‘522 claim 8 and ‘806 claim 8].
As per claim 10, the substance of the claimed invention is identical or substantially similar to that of claim 1. Accordingly, this claim is rejected under the same rationale.
As per claim 11, the substance of the claimed invention is identical or substantially similar to that of claim 2. Accordingly, this claim is rejected under the same rationale.
As per claim 13, the substance of the claimed invention is identical or substantially similar to that of claim 4. Accordingly, this claim is rejected under the same rationale.
As per claim 14, the substance of the claimed invention is identical or substantially similar to that of claim 5. Accordingly, this claim is rejected under the same rationale.
As per claim 15, the substance of the claimed invention is identical or substantially similar to that of claim 6. Accordingly, this claim is rejected under the same rationale.
As per claim 19, the substance of the claimed invention is identical or substantially similar to that of claim 1. Accordingly, this claim is rejected under the same rationale.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-6, 8-11, 13-15 and 17-19 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Fujiwara et al. (US Patent No. 9,666,307) [hereinafter “Fujiwara”].
As per claim 1, Fujiwara teaches a method of operating a memory device, comprising: detecting a predefined event of the memory device (Col. 6, lines 4-18, receiving token control bits for use with the fuse array at the start of transmitting/loading data see Fig. 1); counting a quantity of clock cycles in response to detecting the predefined event (Col. 6, lines 11-16, counter decremented based on clock signal); temporarily disabling a circuit configured to access a fuse array of the memory device based on counting the quantity of clock cycles (Col. 6, lines 10-12, fuse array is temporarily disabled for a predetermined number of latches per a count of clock cycles – also once counter reaches “0” fuse array is temporarily disabled from transmitting data see Col. 6, lines 20-26).
As per claim 2, Fujiwara teaches the method of claim 1, further comprising: storing a threshold number of clock cycles in the memory device (Col. 6, lines 10-15, counter set to a threshold value equal to a number of latches).
As per claim 4, Fujiwara teaches the method of claim 1, further comprising: pausing counting the quantity of clock cycles when the circuit is activated to access the fuse array of the memory device (Col. 6, lines 10-15, counter stops at “0” once number of latches to skip is reached and data from fuse array is transmitted/loaded).
As per claim 5, Fujiwara teaches the method of claim 4, further comprising: resuming counting the quantity of clock cycles when the circuit is deactivated after accessing the fuse array of the memory device (Col. 6, lines 10-15, fuse array is blocked by the token control bits while counter is running and resumes after counter reaches “0” see Col. 6, lines 20-25).
As per claim 6, Fujiwara teaches the method of claim 1, wherein: the predefined event corresponds to a specific sequence of commands directed to the memory device (Col. 6, lines 4-9, starting event is the transmission or loading of data by the fuse array).
As per claim 8, Fujiwara teaches the method of claim 1, wherein: the predefined event comprises to a power-up event of the memory device (Col. 4, lines 40-45, the initialization of the loading/transmitting circuit is a power-up event of the memory device).
As per claim 9, Fujiwara teaches the method of claim 1, wherein: the predefined event comprises to an initialization procedure of the memory device (Col. 6, lines 40-56, reset signal also triggers a reset of the counter which can signal the transmit/load circuit see Col. 6, lines 57-65).
As per claim 10, the substance of the claimed invention is identical or substantially similar to that of claim 1. Accordingly, this claim is rejected under the same rationale.
As per claim 11, the substance of the claimed invention is identical or substantially similar to that of claim 2. Accordingly, this claim is rejected under the same rationale.
As per claim 13, the substance of the claimed invention is identical or substantially similar to that of claim 4. Accordingly, this claim is rejected under the same rationale.
As per claim 14, the substance of the claimed invention is identical or substantially similar to that of claim 5. Accordingly, this claim is rejected under the same rationale.
As per claim 15, the substance of the claimed invention is identical or substantially similar to that of claim 6. Accordingly, this claim is rejected under the same rationale.
As per claim 17, the substance of the claimed invention is identical or substantially similar to that of claim 8. Accordingly, this claim is rejected under the same rationale.
As per claim 18, the substance of the claimed invention is identical or substantially similar to that of claim 9. Accordingly, this claim is rejected under the same rationale.
As per claim 19, the substance of the claimed invention is identical or substantially similar to that of claim 1. Accordingly, this claim is rejected under the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara in view of Fischer et al. (WO-2008133680-A1) [hereinafter “Fischer”].
As per claim 3, Fujiwara teaches the method of claim 2.
Fujiwara does not explicitly teach comparing the counted quantity of clock cycles with the threshold number; and determining the counted quantity of clock cycles is greater than or equal to the threshold number. Fischer teaches comparing the counted quantity of clock cycles with the threshold number; and determining the counted quantity of clock cycles is greater than or equal to the threshold number (Page 12, lines 12-19, comparing counted clock cycles to a threshold number and determining if has been exceeded – Examiner interprets this counter in Fischer to be easily combined with the counting of latches in Fujiwara).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Fujiwara with the teachings of Fischer, comparing the counted quantity of clock cycles with the threshold number; and determining the counted quantity of clock cycles is greater than or equal to the threshold number, to implement a counting mechanism to properly transmit/load data into a processor.
As per claim 12, the substance of the claimed invention is identical or substantially similar to that of claim 3. Accordingly, this claim is rejected under the same rationale.
Claims 7 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara in view of Rusu et al. (PGPUB No. 2003/0065960) [hereinafter “Rusu”].
As per claim 7, Fujiwara teaches the method of claim 1.
Fujiwara does not explicitly teach the predefined event corresponds to a voltage supplied to the memory device exceeding a portion of an operating voltage of the memory device. Rusu teaches the predefined event corresponds to a voltage supplied to the memory device exceeding a portion of an operating voltage of the memory device ([0033], event detecting operating voltage exceeding a threshold and taking proper response see [0027]).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Fujiwara with the teachings of Rusu, the predefined event corresponds to a voltage supplied to the memory device exceeding a portion of an operating voltage of the memory device, to implement a counting mechanism to properly transmit/load data into a processor.
As per claim 16, the substance of the claimed invention is identical or substantially similar to that of claim 7. Accordingly, this claim is rejected under the same rationale.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara in view of Iyer et al. (PGPUB No. 2007/0051805) [hereinafter “Iyer”].
As per claim 20, Fujiwara teaches the method of claim 19.
Fujiwara does not explicitly teach wherein disabling the circuit of the memory device allows read-only access to the fuse array of the memory device. Iyer teaches wherein disabling the circuit of the memory device allows read-only access to the fuse array of the memory device (Abstract, disabling circuit to only allow read access to fuse array once voting is complete).
At the time of filing, it would have been obvious to one of ordinary skill in the art to combine Fujiwara with the teachings of Iyer, wherein disabling the circuit of the memory device allows read-only access to the fuse array of the memory device, to implement temporal policies with data and allow for processing of previous results.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lee (US PGPUB No. 2015/0241509), Lamphier et al. (US Patent No. 5,659,508), Shehata (US PGPUB No. 2010/0161035), Shim (US Patent No. 9,508,456), Kurd et al. ("Multi-GHz clocking scheme for Intel(R) Pentium(R) 4 microprocessor," 2001 IEEE ISSCC (Cat. No.01CH37177), San Francisco, CA, USA, 2001, pp. 404-405, doi: 10.1109/ISSCC.2001.912694), Dong et al. ("A trimming circuit design with pre-trim and fuse protection," 2024 8th International Conference on Electrical, Mechanical and Computer Engineering (ICEMCE), Xi'an, China, 2024, pp. 727-730, doi: 10.1109/ICEMCE64157.2024.10862899), Cowan et al. ("On-chip repair and an ATE independent fusing methodology," Proceedings. International Test Conference, Baltimore, MD, USA, 2002, pp. 178-186, doi: 10.1109/TEST.2002.1041759) and Heath et al. ("Synchro-tokens: eliminating nondeterminism to enable chip-level test of globally-asynchronous SoC's," Proceedings Design, Automation and Test in Europe Conference and Exhibition, Paris, France, 2004, pp. 410-415 Vol.1, doi: 10.1109/DATE.2004.126888) all disclose various aspects of the claimed invention including monitoring a time period before changing access to a memory device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER C SHAW whose telephone number is (571)270-7179. The examiner can normally be reached Max Flex.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Carl Colin can be reached at 571-272-3862. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PETER C SHAW/Primary Examiner, Art Unit 2493 July 31, 2026
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