Detailed Action
Summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1.This office action is in response to the application filed on February 04,2025.
2. Claims 1-4 are pending and has been examined.
Priority
3. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d), which the certified copy has been placed in the record of the file.
Information Disclosure Statement
4.The information disclosure statement (IDS) submitted on 05/14/2026, 07/31/2025 and 02//04/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
5. The drawings submitted on 02/04/2025 are acceptable.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Beart “DE 102014218240” in a view of Weis “20250142713”.
In regard to claim 1, Beart discloses an inverter device (Fig. 3 shows a power module, see parag. 0047) , comprising: an interconnect substrate with a first interconnect layer (conductor tracks 14) , a second interconnect layer (upper copper layer 2, see parag. 0045), and a third interconnect layer (lower copper layer 3) stacked one upon another; a first transistor (power component 4 on the right side ) and a second transistor (power component 4 on the left side) , each having a source region and a drain region surrounding the source region on one face (see Fig. 6 and it is implicit or understood in the art that a power component has a source and drain terminals or region) , arranged side by side in a middle layer (connecting layers 5, see prag.0043) between the second interconnect layer (upper copper layer 2) and the third interconnect layer (bottom copper layer 3) so that the one face faces the second interconnect layer (figs. 5-6 shows connecting layer 5 is between upper copper layer 2 and lower copper layer 3) ; and
a capacitor (capacitor 13) with one terminal connected to a first power line (conductor tracks 14 on the right hand side ) in the first interconnect layer and the other terminal connected to a second power line in the first interconnect layer (conductor tracks 14 on the left hand side) , wherein the first power line extends from the one terminal of the capacitor in a first direction in the first interconnect layer, and is connected to a drain of the first transistor in the drain region on a side of the source region of the first transistor in the first direction (see Fig. 6) ,
and the second power line extends from the other terminal of the capacitor in the second direction in the first interconnect layer, and is connected to a source of the second transistor (See Fig. 6) but fails to discloses an output interconnect connected to a source of the first transistor extends in a second direction opposite to the first direction in the second interconnect layer and is connected to a drain of the second transistor in the drain region on a side of the source region of the second transistor in the first direction. (Examiner noted that it is implicit in the art Fig. 6 has a half bridge and half bridge has an output conductor coupled between the source and drain of the first and second transistors or vice versa. However, examiner brought a second reference just to show the recited claim languages.
Weis discloses an output interconnect connected to a source of the first transistor extends in a second direction opposite to the first direction in the second interconnect layer and is connected to a drain of the second transistor in the drain region on a side of the source region of the second transistor in the first direction (Figs. 1-8 shows component carrier 100 and Fig. 3 shows first and second transistor 110 and 120 configured as a half bridge and to provide an output interconnect connected (interconnected source conductor 145a and drain conductor 145b to output voltage via an arrow are equivalent to output interconnect ) to a source of the first transistor (110) extends in a second direction opposite (Figs.4-6: 145a and 15b are in opposite direction, see fig. 6 ) to the first direction in the second interconnect layer is connected to a drain of the second transistor in the drain region on a side of the source region of the second transistor in the first direction (see Figs 3-6, transistor 110 and 120 are arranged between different layers in a different , X,Y and Z directions)) .
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to have modified an power module of Beart to include an output interconnect connected to a source of the first transistor extends in a second direction opposite to the first direction in the second interconnect layer and is connected to a drain of the second transistor in the drain region on a side of the source region of the second transistor in the first direction as taught by Weis to provide an efficient and compact switching cell in the component carrier stack that can reliably handle low-, mid- and high current ranges in a flexible manner, thus improve the reliability and efficiency of the converter, see parag. 0016.
In regard to claim 4, Beart discloses an inverter device (Fig. 3 shows a power module, see parag. 0047), comprising: an interconnect substrate with a first interconnect layer (conductor tracks 14), a second interconnect layer (upper copper layer 2, see parag. 0045), and a third interconnect layer (lower copper layer 3) stacked one upon another; a first transistor (power component 4 on the right side) and a second transistor (power component 4 on the left side), each having a source region on one face and a drain region on the other face (see Fig. 6 and it is understood in the art power component has a source and drain terminals or regions ), arranged side by side in a middle layer (connecting layers 5, see prag.0043) between the second interconnect layer (upper copper layer 2) and the third interconnect layer (bottom copper layer 3); and
a capacitor (capacitor 13) with one terminal connected to a first power line in the first interconnect layer (conductor tracks 14 on the right hand side ) and the other terminal (conductor tracks 14 on the left hand side) connected to a second power line in the first interconnect layer and the first power line extends from the one terminal of the capacitor in a first direction in the first interconnect layer and is connected to a drain of the first transistor (see Fig.6) but fails to discloses wherein the one face of the first transistor faces the second interconnect layer, and the other face of the second transistor faces the second interconnect layer and an output interconnect connected to a source of the first transistor extends in a second direction opposite to the first direction in the second interconnect layer and is connected to a drain of the second transistor, and the second power line extends from the other terminal of the capacitor in the second direction in the first interconnect layer and is connected to a source of the second transistor
Weis discloses Figs .4-5 shows one face of transistor 110 faces the second interconnect layers between interconnect layers L1/, L1/L2 and L2 and the other face of the second transistor 120 faces between interconnect layers L1/, L1/L2 and L2 .
Furthermore, Weis discloses an output interconnect connected to a source of the first transistor extends in a second direction opposite to the first direction in the second interconnect layer and is connected to a drain of the second transistor in the drain region on a side of the source region of the second transistor in the first direction (Figs. 1-8 shows component carrier 100 and Fig. 2 shows first and second transistor 110 and 120 configured as a half bridge and to provide an output interconnect connected (interconnected source conductor 145a and drain conductor 145b are equivalent to output interconnect ) to a source of the first transistor (110) extends in a second direction opposite (Figs.4-6: 145a and 15b are in opposite direction, see fig. 6 ) to the first direction in the second interconnect layer (Figs. 4-6, transistor 110 and 120 are arranged between different layers) is connected to a drain of the second transistor in the drain region on a side of the source region of the second transistor in the first direction (see Figs 3-6) .
Therefore, it would have been obvious to one of ordinary skilled in the art before the effective filing date of the claimed invention to have modified an power module of Beart to include an output interconnect connected to a source of the first transistor extends in a second direction opposite to the first direction in the second interconnect layer and is connected to a drain of the second transistor in the drain region on a side of the source region of the second transistor in the first direction as taught by Weis to provide an efficient and compact switching cell in the component carrier stack that can reliably handle low-, mid- and high current ranges in a flexible manner, thus improve the reliability and efficiency of the converter, see parag. 0016.
Allowable Subject Matter
7. Claim 2-3 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter.
Claim 2 is objected because the prior art of record fails to disclose or suggest the inverter device including the limitation of “wherein the first power lines in the second interconnect layer and the third interconnect layer are mutually connected through a via, and the first power line in the third interconnect layer is connected to the drain of the first transistor.”
Claim 3 is objected because the prior art of record fails to disclose or suggest the inverter device including the limitation of “wherein the output interconnects in the second interconnect layer and the third interconnect layer are mutually connected through a via, and the output interconnect in the third interconnect layer is connected to the drain of the second transistor”
Conclusion
8. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Furukawa “20250309781” the first interconnect can be made wide, the number of vias connecting the source of the first transistor and the drain of the second transistor with the first interconnect can be increased, whereby the influence of the self-inductance due to vias can be reduced.
Furukawa “20250311377” the technology disclosed herein belongs to a technical field related to an inverter device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Crystal L Hammond can be reached at (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SISAY G TIKU/
Primary Examiner, Art Unit 2838
Prosecution Insights