Prosecution Insights
Last updated: April 19, 2026
Application No. 19/044,855

Quantum Error Correction with Leakage

Final Rejection §103
Filed
Feb 04, 2025
Examiner
PATEL, JIGAR P
Art Unit
2114
Tech Center
2100 — Computer Architecture & Software
Assignee
Riverlane Ltd.
OA Round
2 (Final)
80%
Grant Probability
Favorable
3-4
OA Rounds
3y 1m
To Grant
97%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allow Rate
460 granted / 575 resolved
+25.0% vs TC avg
Strong +17% interview lift
Without
With
+16.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
26 currently pending
Career history
601
Total Applications
across all art units

Statute-Specific Performance

§101
8.8%
-31.2% vs TC avg
§103
62.9%
+22.9% vs TC avg
§102
13.6%
-26.4% vs TC avg
§112
5.2%
-34.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 575 resolved cases

Office Action

§103
DETAILED ACTION This communication is responsive to the application, filed November 12, 2025. Claims 1-23 are pending in this application. Examined under the first inventor to file provisions of the AIA The present application was filed on February 4, 2025, which is on or after March 16, 2013, and thus is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-23 are rejected under 35 U.S.C. 103 as being unpatentable over Yoder (US 11,736,122 B1) in view of Dial et al. (US 11,960,970 B2) and further in view of Nickerson et al. (US 11,263,076 B2). As per claim 1: A quantum computing system comprising: a plurality of quantum devices; and Yoder discloses [Fig. 1; col. 4, lines 12-32] a plurality of quantum computers. a decoding system comprising memory storing a decoding hypergraph associated with a quantum error correction code, the decoding hypergraph comprising a plurality of nodes connected by hyperedges representing error mechanisms associated with the plurality of quantum devices, Yoder discloses [col. 3, lines 1-21] a maximum likelihood decoder component executing on a server and using a decoding graph for QEC decoding and the efficiency depends on edge weights that characterize error probabilities. Yoder further discloses [col. 4 and 5] a hypergraph component generating decoding hypergraphs used by the decoder. Yoder further teaches [col. 8, lines 1-23] the hypergraph has vertices/nodes corresponding to error-sensitive faults and the hyper edges connect these in the decoding structure. determine that a leakage event has occurred at one or more of a plurality of quantum devices; Yoder discloses identifying error events, but fails to explicitly disclose determining a leakage event at a quantum device. Dial discloses a similar system, which further teaches [Fig. 11; col. 20] detecting a quantum state leakage associated with one or more qubits and generating a time pause in response to the quantum state leakage. The quantum state leakage decays during the time pause. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Yoder with that of Dial. One would have been motivated to adjust the weight/flags of hypergraph edges tied to operations involving the leaked qubit so the decoder accounts for the event and avoids propagating corrupted information [Dial; col. 20] wherein the quantum computing system is configured to, during runtime of a quantum computation on the quantum computing system: determine one or more hyperedges of the decoding hypergraph that are associated with an increased likelihood of an error mechanism as a result of the leakage event; and adjust at least one hyperedge of the one or more hyperedges of the decoding hypergraph associated with the increased likelihood of the error mechanism. Yoder discloses [Fig. 3; col. 7 and 8] identifying error-sensitive events and mapping them into the decoding hypergraph. Furthermore, Yoder discloses [col. 3, lines 1-21 and col. 8, lines 1-23] that decoding uses edge weights on the hypergraph that encode error probabilities, and the algorithm selects an optimal correction based on those weights. Yoder discloses determining hyperedges of the hypergraph, but fails to explicitly disclose determining hyperedges associated with an increased likelihood of an error mechanism and adjusting hyperedge associated with the error mechanism. Nickerson discloses a similar system, which further teaches [Fig. 7, col. 18, lines 27-67; col. 12, lines 25-37; Fig. 5A, col. 14, lines 1-12] identifying “clusters” or “erased qubits” in the syndrome graph (decoding hypergraph) that correspond to known errors (like qubit loss/erasure). The decoder explicitly identifies which edges/nodes are affected. The decoding happens dynamically as syndrome data is received, specifically described as being capable of running in real-time or handling data as it is generated. Nickerson further discloses [col. 17, lines 44-58, claim 1; col. 14, lines 25-29; col. 18, lines 58-67] once the problem areas (clusters/erasures) are identified, the decoder modifies the graph by growing clusters, merging them, or removing/reconstructing specific edges to account for the error. This is a structural adjustment of the decoding graph. The adjustment is specifically targeted at the identified “invalid clusters” or “erased qubits” (associated with error mechanism). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Yoder and Dial with that of Nickerson. One would have been motivated to apply Nickerson’s erasure/loss adjustment technique to the leakage events detected by Dial within Yoder’s decoder because it provides increased robustness and a higher error threshold [Nickerson; col. 5, lines 59-67]. As per claim 2: The quantum computing system of claim 1, wherein adjusting the at least one hyperedge comprises setting respective edge weights of each of the determined one or more hyperedges to a predetermined weight value. Yoder discloses [col. 3, lines 1-21 and col. 8 lines 1-23] decoding hypergraphs have edges with weights that characterize probabilities. This allows to adjust weights of hyperedges. As per claim 3: The quantum computing system of claim 2, wherein the predetermined weight value is zero. Yoder discloses [col. 12, lines 1-25] truncating the probability distribution and maintaining only those entries consistent with bit string. The truncation removes disallowed entries, which is equivalent to assigning weight zero to the removed edges (edge never chosen). As per claim 4: The quantum computing system of claim 1, wherein adjusting the at least one hyperedge comprises setting an error flag or mask for each of the determined one or more hyperedges. Yoder discloses [col. 10, lines 1-21 and col. 11, lines 1-26] per-hyperedge weights used in the decoding pipeline. Furthermore, Dial discloses [Fig. 11; col. 20] detecting leakage and refraining from executing subsequent operations during a pause window. Given Yoder’s per-hyperedge weighting and Dial’s leakage trigger, a mask and/or flag on affected hyperedges lets the decoder skip those edges efficiently. As per claim 5: The quantum computing system of claim 1, wherein the decoding system is configured to: receive syndrome data representative of an error state of the plurality of quantum devices; and determine a correction for the error state by decoding the syndrome data with the decoding hypergraph. Yoder discloses [col. 3, lines 1-20] decoder takes measurement bit string and outputs a correction. Yoder further discloses [col. 13, lines 45-67 and col. 14, lines 1-10] executing ML decoding to determine an error correction. The system can provide instructions to the quantum computer to perform the error correction. As per claim 6: The quantum computing system of claim 5, wherein the quantum computing system is further configured to: measure a logical state encoded in the plurality of quantum devices to obtain a logical state measurement; and apply the correction to the logical state measurement. Yoder discloses [col. 3, lines 1-20] decoder takes measurement bit string and outputs a correction. Yoder further discloses [col. 13, lines 45-67 and col. 14, lines 1-10] executing ML decoding to determine an error correction. The system can provide instructions to the quantum computer to perform the error correction. As per claim 7: The quantum computing system of claim 1, wherein determining the one or more hyperedges of the decoding hypergraph that are associated with the increased likelihood of the error mechanism comprises: determining at least one possible source of the leakage event; Dial discloses [Fig. 11; col. 20] detecting one or more qubits as source of the leakage event. determining one or more quantum operations affected by the at least one possible source of the leakage event; Dial discloses [Fig. 11; col. 20] identifying the circuit/operations of the quantum state leakage arises during the execution of the previous circuit. identifying a plurality of error mechanisms associated with the one or more quantum operations affected by the at least one possible source of the leakage event; and Yoder discloses [col. 7, lines 43-67 and col. 8, lines 1-21] hypergraph component maps error-sensitive events to faults/error mechanism per operation in the circuit. identifying a respective decoding hypergraph hyperedge associated with each of the plurality of error mechanisms. Yoder discloses [col. 10, lines 1-20] each hyperedge aggregates faults/error mechanism and carries a probability/weight. As per claim 8: The quantum computing system of claim 1, wherein determining the one or more hyperedges of the decoding hypergraph that are associated with the increased likelihood of the error mechanism comprises: generating a first decoding hypergraph for an error model excluding leakage events; Yoder discloses [col. 7, lines 43-67 and col. 8, lines 1-21] construct a decoding hypergraph from a specified error model. Yoder further discloses [col. 10, lines 1-20] assign probabilities per hyperedge from the model. generating a second decoding hypergraph for an error model including leakage events; and identifying corresponding hypergraph hyperedges in the first decoding hypergraph and the second decoding hypergraph that have different edge weights. Dial discloses [col. 9, lines 15-30 and col. 10, lines 1-25] supplying the leakage mechanism and teaches leakage as an error to be handled. Furthermore, Yoder discloses [col. 10, lines 1-21 and col. 11 lines 1-20] per-hyperedge probabilities/weights depend on the assumed error mechanism. Therefore, when leakage mechanism is added, the computed weights for affected hyperedges of Yoder will differ. As per claim 9: The quantum computing system of claim 1, wherein the plurality of quantum devices is a plurality of qubits. Yoder discloses [Fig. 1, (104)] the plurality of quantum devices can be a plurality of qubits. As per claim 10: The quantum computing system of claim 1, wherein the decoding hypergraph is a decoding graph and wherein the hyperedges are edges. Yoder discloses [col. 3, lines 1-21] decoding graph with nodes (events) and edges (faults with weights). Yoder further discloses [col. 7, lines 43-67 and col. 8, lines 1-20] decoding hypergraph generalization. As per claim 11: The quantum computing system of claim 1, wherein adjusting the at least one hyperedge of the hyperedges of the decoding hypergraph comprises uniformly adjusting the at least one hyperedge of the decoding hypergraph. Yoder discloses [col. 13, lines 1-20] a uniform decoder using uniform edge weights as a baseline. Yoder further discloses [col. 10, lines 1-20 and col. 11, lines 1-21] weights per hyperedge are configurable per the error model. As per claims 12-22: Although claims 12-22 are directed towards a method claim, they are rejected under the same rationale as the system claims 1-11 above. As per claim 23: Although claim 23 is directed towards a medium claim, it is rejected under the same rationale as the system claim 1 above. Response to Arguments Applicant’s arguments with respect to amended claim(s) 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c). · US 2025/0068953 A1 – Senior discloses the decoder can process features of quantum measurements of different types, such as leakage data, detection events, and/or other parameters. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIGAR P PATEL whose telephone number is (571)270-5067. The examiner can normally be reached on Monday to Friday 10AM-6PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas, can be reached on 571-272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JIGAR P PATEL/Primary Examiner, Art Unit 2114
Read full office action

Prosecution Timeline

Feb 04, 2025
Application Filed
Feb 19, 2025
Response after Non-Final Action
Aug 22, 2025
Non-Final Rejection — §103
Nov 07, 2025
Applicant Interview (Telephonic)
Nov 07, 2025
Examiner Interview Summary
Nov 12, 2025
Response Filed
Dec 02, 2025
Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12602273
SAFETY MONITORING OF A SYSTEM-ON-A-CHIP
2y 5m to grant Granted Apr 14, 2026
Patent 12602298
Self-Repairable Chip For Silent Data Corruption Issues
2y 5m to grant Granted Apr 14, 2026
Patent 12591480
AUTOMATIC IDENTIFICATION OF ROOT CAUSE AND MITIGATION STEPS FOR INCIDENTS GENERATED IN AN INCIDENT MANAGEMENT SYSTEM
2y 5m to grant Granted Mar 31, 2026
Patent 12585570
Microchip with on-chip debug and trace engine
2y 5m to grant Granted Mar 24, 2026
Patent 12579017
APPARATUS AND METHODS FOR SECURING INTEGRITY AND DATA ENCRYPTION LINK SESSIONS WITHIN DIE INTERCONNECT ARCHITECTURES
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
80%
Grant Probability
97%
With Interview (+16.9%)
3y 1m
Median Time to Grant
Moderate
PTA Risk
Based on 575 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month