Detailed Action
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 of U.S. Application 19/045,072 filed on February 04,2025 are presented for examination.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/04/2025, 01/26/2026, and 06/12/2026 has been considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1,3,11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (USPGPub 20220178993) in view of Pendse et al (USPGPub 20090289253).
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Prior Art: Lee
Regarding claim 1, Lee discloses a wafer test system (100) comprising: a chuck (102) for supporting a wafer (101) including a plurality of dies (pars 2 and 9 discloses a plurality of dies); a probe card (106 and 506) for inputting a test signal for an electrical test to the plurality of dies (par 17 discloses applying voltage and currents to the circuitry) through a plurality of pins (200) and receiving test results; a sensing device (122) mounted on a surface of the probe card (shown in fig 5 as mounted on the probe card), for sensing an active state (when wafer is heated). Lee does not fully disclose a determination unit for receiving the test results and an active state information for the plurality of dies and determining whether each of the plurality of dies has failed using both of the test results of the electrical test on the wafer and the active state information which is sensed when the electrical test is performed.
However, Pendse discloses a determination unit (using computer test system 176) for receiving the test results and an active state information (par 52 discloses range of operating temperatures) for the plurality of dies and determining whether each of the plurality of dies has failed using both of the test results of the electrical test on the wafer and the active state information which is sensed when the electrical test is performed (par 52 discloses detecting defects which is based on the test and temperature).It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to combine Lee in view of Pendse in order to test and remove defective dies.
Regarding claim 3, Lee does not fully disclose wherein the determination unit classifies the plurality of dies into a plurality of categories using characteristic parameters resulting from the electrical test on the wafer and the active state information.
However, Pendse discloses wherein the determination unit classifies the plurality of dies into a plurality of categories using characteristic parameters resulting from the electrical test on the wafer and the active state information (pars 11 and 13 discloses detecting the defects in dies and par 49 discloses detecting known good dies (KGD). Therefore, categorized into different classifications). It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have combined Lee in view of Pendse in order to test and remove defective dies.
Regarding claim 11, Lee discloses a probe head (218) disposed on an opposite side of a side where the plurality of pins (200) are disposed on the probe card (shown in fig 5 at the top of probe card where 200 is towards the bottom), and configured for inputting the test signal for the electrical test to the probe card and receiving the test results of the electrical test corresponding to the test signal (pars 15 and 17 discloses using 218 to provide feedback from sensors to the board. Therefore correspond to the test system).
Regarding claim 12, Lee discloses a method for operating a wafer test system (100), comprising: performing an electrical test on a wafer (101)including a plurality of dies (par 2 and 9 discloses having a plurality of dies); sensing an active state (when wafer is heated) occurring in the wafer when the electrical test is performed (par 17 discloses using the probe card to apply and receive test signals). Lee does not fully disclose determining whether each of the plurality of dies included in the wafer has failed using both of a result of the electrical test on the wafer and active state information obtained in the sensing of the active state, and the active state information is sensed when the electrical test is performed.
However, Pendse discloses determining (using computer test system 176) whether each of the plurality of dies included in the wafer has failed using both of a result of the electrical test on the wafer and active state (par 52 discloses range of operating temperatures) information obtained in the sensing of the active state, and the active state information is sensed when the electrical test is performed (par 52 discloses detecting defects which is based on test and temperatures). It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to combine Lee in view of Pendse in order to test and remove defective dies.
Claims 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (USPGPub 20220178993) in view of Pendse et al (USPGPub 20090289253) in further view of Bello et al ((USPGPub 20180048169).
Regarding claim 4, Lee in view of Pendse does not fully disclose wherein the determination unit generates a wafer temperature distribution map for the wafer using the active state information.
However, Bello discloses wherein the determination unit generates a wafer temperature distribution map for the wafer using the active state information (par 37 discloses a sensing unit to measure distribution of heat on the wafer. Therefore, would create a distribution map based on the equipment used). It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have combined Lee in view of Pendse in further view of Bello order to test and remove defective dies based on the measured heat.
Regarding claim 15, Lee in view of Pendse does not fully disclose generating a wafer temperature distribution map for the wafer using the active state information.
However, Bello discloses generating a wafer temperature distribution map for the wafer using the active state information (par 37 discloses a sensing unit to measure distribution of heat on the wafer. Therefore, would create a distribution map based on the equipment used). It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have combined Lee in view of Pendse in further view of Bello order to test and remove defective dies based on the measured heat.
Claims 5 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (USPGPub 20220178993) in view of Pendse et al (USPGPub 20090289253) in further view of Takesako et al (USPGPub 20170102410).
Regarding claim 5, Lee in view of Pendse does not fully disclose wherein the determination unit stops the electrical test based on the active state information of the plurality of dies.
However, Takesako discloses wherein the determination unit stops the electrical test based on the active state information of the plurality of dies (par 66 discloses the controller stops performing the evaluation). It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have combined Lee in view of Pendse in further view of Takesako in order to check or verify problems with the dies.
Regarding claim 16, Lee in view of Pendse does not fully disclose wherein stopping the electrical test based on temperatures of the plurality of dies included in the wafer.
However, Takesako discloses stopping the electrical test based on temperatures of the plurality of dies included in the wafer (par 66 discloses the controller stops performing the evaluation). It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have combined Lee in view of Pendse in further view of Takesako in order to check or verify problems with the dies.
Claims 8, 9, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (USPGPub 20220178993) in view of Pendse et al (USPGPub 20090289253) in further view of Corzine et al (USPGPub 20200266886).
Regarding claim 8, Lee in view of Pendse does not fully disclose wherein the active state is light emission.
However, Corzine discloses wherein the active state is light emission (par 61 discloses light emissions by passive or active means). It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have combined Lee in view of Pendse in further view of Corzine in order to determine electrical parameters of the device.
Regarding claim 9, Lee in view of Pendse does not fully disclose wherein the active state is heat dissipation.
However, Corzine discloses wherein the active state is heat dissipation (par 112 discloses testing DUT including a large heatsink. Therefore, heat dissipation). It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have combined Lee in view of Pendse in further view of Corzine in order to determine electrical parameters of the device while removing heat from the DUT.
Regarding claim 19, Lee in view of Pendse does not fully disclose wherein the active state is light emission or heat dissipation. It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have combined Lee in view of Pendse in further view of Corzine in order to determine electrical parameters of the device.
However, Corzine discloses wherein the active state is light emission or heat dissipation (par 61 discloses light emissions by passive or active means). It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have combined Lee in view of Pendse in further view of Corzine in order to determine electrical parameters of the device.
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (USPGPub 20220178993) in view of Pendse et al (USPGPub 20090289253) in further view of Yamamoto et al (USPGPub 20020039800).
Regarding claim 10, Lee in view of Pendse does not fully disclose wherein the electrical test includes at least one of a DC test, an AC test, a stress test, a cell test and a peripheral test.
However, Yamamoto discloses wherein the electrical test includes at least one of a DC test, an AC test, a stress test, a cell test and a peripheral test (par 88 and 89 discloses using as stress test). It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have combined Lee in view of Pendse in further view of Yamamoto in order to detect stress based on values.
Regarding claim 20, Lee in view of Pendse does not fully disclose wherein the electrical test includes at least one of a DC test, an AC test, a stress test, a cell test and a peripheral test.
However, Yamamoto discloses wherein the electrical test includes at least one of a DC test, an AC test, a stress test, a cell test and a peripheral test (par 88 and 89 discloses using as stress test). It would have been obvious to a person having ordinary skill in the art at the time the invention was made to have combined Lee in view of Pendse in further view of Yamamoto in order to detect stress based on values.
Allowable Subject Matter
Claims 2, 6, 7, 13, 17, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 2, the prior art of record taken alone or in combination fail to teach or suggest a wafer test system comprising: wherein the determination unit compares the test results of the electrical test and the active state information with reference data, and when a die passes the electrical test and a comparison of the active state information of the die to the reference data exceeds a threshold difference, determines the die to be sorted as a fail in combination with the other limitations of the claim.
Regarding claim 6, the prior art of record taken alone or in combination fail to teach or suggest a wafer test system comprising: wherein the active state information is an average temperature of the plurality of dies included in the wafer that is lower than a first threshold temperature or higher than a second threshold temperature, where the second threshold temperature is higher than the first threshold temperature in combination with the other limitations of the claim.
Regarding claim 7, the prior art of record taken alone or in combination fail to teach or suggest a wafer test system comprising: wherein the active state information is a difference between a maximum temperature and a minimum temperature from among temperatures of the plurality of dies included in the wafer that is equal to or higher than a threshold value in combination with the other limitations of the claim.
Regarding claim 13, the prior art of record taken alone or in combination fail to teach or suggest a method for operating a wafer test system, comprising: wherein the determining whether each of the plurality of dies included in the wafer has failed comprising: comparing the result of the electrical test and the active state information with reference data, and determining a die to be sorted as a fail, when the die passes the electrical test and a comparison of the active state information of the die to the reference data exceeds a threshold difference in combination with the other limitations of the claim.
Regarding claim 17, the prior art of record taken alone or in combination fail to teach or suggest a method for operating a wafer test system, comprising: wherein the electrical test is stopped when an average temperature of the plurality of dies included in the wafer is lower than a first threshold temperature or higher than a second threshold temperature, which is higher than the first threshold temperature in combination with the other limitations of the claim.
Regarding claim 18, the prior art of record taken alone or in combination fail to teach or suggest a method for operating a wafer test system, comprising: wherein, in the stopping of the electrical test, the electrical test is stopped when a difference between a maximum temperature and a minimum temperature among the temperatures of the plurality of dies included in the wafer is equal to or higher than a threshold value in combination with the other limitations of the claim.
Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lou et al (US Pat No. 11047880): discloses probing device that measures the temperature of a wafer.
Minemier et al (USPGPub 20140203837): discloses a wafer test system with a photo emitter attached to a probe card.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOMINIC E HAWKINS whose telephone number is (571)272-2647. The examiner can normally be reached Monday-Friday 7:30am-5:00pm EST.
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/DOMINIC E HAWKINS/Primary Examiner, Art Unit 2858
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