Prosecution Insights
Last updated: August 17, 2026
Application No. 19/045,557

POWER MANAGEMENT METHOD AND ELECTRONIC DEVICE

Non-Final OA §101
Filed
Feb 05, 2025
Priority
Jan 03, 2025 — TW 114100210
Examiner
STOYNOV, STEFAN
Art Unit
2175
Tech Center
2100 — Computer Architecture & Software
Assignee
WISTRON Corporation
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
760 granted / 849 resolved
+34.5% vs TC avg
Moderate +13% lift
Without
With
+12.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
10 currently pending
Career history
856
Total Applications
across all art units

Statute-Specific Performance

§101
8.5%
-31.5% vs TC avg
§103
33.1%
-6.9% vs TC avg
§102
26.7%
-13.3% vs TC avg
§112
19.6%
-20.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 849 resolved cases

Office Action

§101
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Objections Claims 16-20 are objected to because of the following informalities: Claims 16-20 recite “on-transitory computer-readable storage medium” instead of “non-transitory computer-readable storage medium” in the preamble. Appropriate correction is required. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-5, 7-12, 15-18 and 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Claim 8 recites the limitation generating a predicted processor performance according to the first log data. The limitation, as drafted, is a process that, under its broadest reasonable interpretation (BRI), covers performance of the limitation in the mind but for the recitation of generic computer components. That is, other than reciting “a memory” and “a processor”, nothing in the claim element precludes the step from particularly being performed in the mind. For example, but for the “memory” and “processor” language, the claim encompasses a user simply reviewing the log data to predict the processor performance in his/her mind. The mere nominal recitation of a generic memory and processor does not take the claim limitation out of the mental processes grouping. Thus, the claim recites a mental process. The claim further recites the limitation “inputting the first log data, the predicted processor performance, and a first prompt into a language model to obtain a power setting related to the electronic device”. Utilizing a language model (which is a mathematical model by its definition) to obtain settings based on input data is a mathematical calculation. Accordingly, the limitation falls within the “mathematical concepts” grouping of abstract ideas. Similarly to the mental step limitation, the mere nominal recitation of a generic memory and processor does not take the claim limitation out of the mathematical concepts grouping. Thus, the claim recites a mathematical concept. The judicial exception is not integrated into a practical application because the claim recites the additional element of “obtaining first log data related to the electronic device, wherein the first log data comprises values of a component within the electronic device and usage behavior data of the electronic device”. This additional element represents mere data gathering that is necessary for use of the recited judicial exception(s) and is recited with a high level of generality. Accordingly, this limitation is an insignificant extra-solution activity. The “memory” and “processor” which carry out the “obtaining first log data” limitation is the tool used to obtain the first log data. However, as mentioned above, the generic recitation of the “memory” and the “processor” represents no more than mere instructions to apply the judicial exceptions on generic computer components. Even when viewed in combination, the additional element does not integrate the recited judicial exception(s) into a practical application and the claim is directed to the judicial exception(s). The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As explained previously, the memory and processor are at best the equivalent of merely adding the words “apply it” to the judicial exception(s). The “obtaining first log data” limitation, which was explained previously is insignificant extra-solution activity. Even when considered in combination, these additional elements represent mere instructions to apply an exception and insignificant extra-solution activity, which do not provide an inventive concept. The claim is not eligible. Claims 1 and 15 are directed to a method and a non-transitory computer-readable storage medium performing the identical claim limitations recited and analyzed above for claim 8. Accordingly, claims 1 and 15 are also not eligible. Claims 2, 9 and 19 merely add elements further limiting what type the obtained data is, which does not take the judicial exception(s) out of the mental processes grouping and the mathematical concept grouping. The additional elements are not sufficient to amount to significantly more than the judicial exception(s). Thus, claims 2, 9 and 19 are not eligible. Claim 3, 10 and 17 merely add different machine learning models (which are mathematical concepts by definition) to obtain predicted performance (data output). Accordingly, these limitations fall within the “mathematical concepts” grouping of abstract ideas – i.e. claims 3, 10 and 17 recite a mathematical concept. Thus, claims 3, 10, and 17 are not eligible. Claims 4 and 11 merely specify the type of machine learning model used – i.e. the type of mathematical concepts used. Accordingly, claims 4 and 11 still fall within the “mathematical concepts” grouping of abstract ideas. Thus, claims 4 and 11 are not eligible. Claims 5, 12 and 18 merely repeat the “obtaining” log data functionality/limitation with different input data (second log data) and feeding the obtained second log data into the language mode. Accordingly, claims 5, 12, and 18 merely repeat the insignificant extra-solution activity of obtaining data for the language model (which is a mathematical concepts by its definition, as indicated previously). Accordingly, the repeated extra-solution activity for obtaining data does not integrate the recited judicial exception(s) into a practical application. Thus, claims 5, 12 and 18 are not eligible. Claims 7 and 20 recite the additional element for “executing the power setting using a function call of the language model” which merely represents generic computer execution based on input from the language model (which itself is a mathematical concept) – i.e. an extra-solution activity for executing data. This does not integrate the recited judicial exception(s) into a practical application. Thus, claims 7 and 20 are not eligible. Allowable Subject Matter Claims 6 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and the claim objection set forth in this Office action is overcome. The following is a statement of reasons for the indication of allowable subject matter: KIM, US Patent Appl. Pub. No. 2024/0193067 teaches a system on chip that may perform energy-efficient performance control by predicting performance in a function unit (processor) and an operating method of the system on chip, utilizing historical measurements of previous performance information (Abstract, FIG. 2, paragraphs 0050-0066). However, KIM does not teach inputting the first log data, the predicted processor performance, and a first prompt into a language model to obtain a power setting related to the electronic device, obtaining a second log data of the electronic device after adjusting the electronic device according to the power setting, inputting the second log data and a second prompt into the language model, wherein the first prompt instructs an artificial intelligence agent to perform power management, and the second prompt instructs the artificial intelligence agent to use the second log data as feedback to modify a strategy of the power management, as required by claims 6, 13 and 19. HE et al., US Patent Appl. Pub. No. 2022/0347583 teaches providing one or more sets of graphics parameters by consolidating data related to settings of graphics parameters for different computer hardware equipment and respective performance values, training a machine learning model based on the consolidated data, determining a weight for each setting of a graphics parameter, by the trained machine learning model, and for each set of graphics parameters, predicting a performance value achievable by the computer gaming application when it is executed on a specific type of computer, by the trained machine learning model (Abstract, FIG. 1, paragraph 0022). However, HE is silent with regards inputting the first log data, the predicted processor performance, and a first prompt into a language model to obtain a power setting related to the electronic device, obtaining a second log data of the electronic device after adjusting the electronic device according to the power setting, inputting the second log data and a second prompt into the language model, wherein the first prompt instructs an artificial intelligence agent to perform power management, and the second prompt instructs the artificial intelligence agent to use the second log data as feedback to modify a strategy of the power management, as required by claims 6, 13 and 19. Gorla et al., US patent Appl. Pub. No. 2026/0149296 teaches power control circuit to control data center power delivery, wherein the power control circuit selectively causes at least a portion of supplied power to be directed to one or more server racks or to charge one or more batteries based, at least in part on, one or more charge levels corresponding to the one or more batteries (Abstract). Gorla further teaches a large language model (LLM) receiving a text input describing the level of SoC, user configuration of battery SoC target level and/or minimum SoC for UPS, and/or additional user specification of power control target and generating an output describing power setting parameters for grid power and/or rack power (FIG. 2, paragraph 0084). Again, Gorla is silent regarding inputting the first log data, the predicted processor performance, and a first prompt into a language model to obtain a power setting related to the electronic device, obtaining a second log data of the electronic device after adjusting the electronic device according to the power setting, inputting the second log data and a second prompt into the language model, wherein the first prompt instructs an artificial intelligence agent to perform power management, and the second prompt instructs the artificial intelligence agent to use the second log data as feedback to modify a strategy of the power management, as required by claims 6, 13 and 19. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEFAN STOYNOV whose telephone number is (571)272-4236. The examiner can normally be reached 8AM - 4:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEFAN STOYNOV/ Primary Examiner, Art Unit 2175
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Prosecution Timeline

Feb 05, 2025
Application Filed
Jul 27, 2026
Non-Final Rejection mailed — §101 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
99%
With Interview (+12.9%)
2y 3m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 849 resolved cases by this examiner. Grant probability derived from career allowance rate.

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