CTNF 19/045,630 CTNF 80149 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Other Refs: McDonnell (US 20190075063) – Virtual switch scaling for networking applications. Allowable Subject Matter Claims 1-20 are allowable, subject to the rejections below. The below rejections must be overcome before allowance. REASONS FOR ALLOWANCE The following is an examiner’s statement of reasons for indicating allowability: Claim 1. Simmons (US 20190347133) discloses A method (e.g., Other processors may include those on microcontrollers, 0017), comprising: storing first code associated with execution of a first application by a first central processing unit (CPU) in a first region of a memory of a device (e.g., Cores 104, 106, 108 may arise from a single processor or multiple processors, such as a traditional central processing unit (CPU) , 0017; programs are executed on cores 104, 106, 108., 0028 Fig. 2; Compiled code 328 may be stored in long-term memory until it is loaded into program memory in memory blocks 110, 112, 114 for execution, 0028). For Claim 1, the prior art does not teach the following limitations when viewed in combination with the other recited limitations: wherein the device includes a plurality of CPUs each having access to the memory, and wherein the memory includes a plurality of regions each corresponding to an address space between a starting address and an ending address; storing second code associated with execution of a second application by a second CPU in a second region of the memory, wherein execution of the first application includes execution of the first code and shared code, not the second code, and wherein execution of the second application includes execution of the second code and the shared code, not the first code; and storing the shared code in a third region of the memory. Claims 2-8, are allowable based on dependency from Claim 1. For Claim 9, Simmons discloses A system (e.g., Other processors may include those on microcontrollers, 0017), comprising: a first central processing unit (CPU) configured to execute a first application (e.g., Cores 104, 106, 108 may arise from a single processor or multiple processors, such as a traditional central processing unit (CPU) , 0017; programs are executed on cores 104, 106, 108., 0028 Fig. 2; Compiled code 328 may be stored in long-term memory until it is loaded into program memory in memory blocks 110, 112, 114 for execution, 0028). For Claim 9, the prior art does not teach the following limitations when viewed in combination with the other recited limitations: which includes execution of first code and shared code; a second CPU configured to execute a second application, which includes execution of second code and the shared code;a memory accessible by the first CPU and the second CPU and configured to: store the first code in a first region of the memory; store the second code in a second region of the memory; and store the shared code, without a duplicate copy of the shared code, in a third region of the memory. Claims 10-16 are allowable based on dependency from Claim 9. For Claim 17, Simmons discloses A method (e.g., Other processors may include those on microcontrollers, 0017), comprising: executing a first function using a first central processing unit (CPU) in a device, which includes executing first code (e.g., Cores 104, 106, 108 may arise from a single processor or multiple processors, such as a traditional central processing unit (CPU) , 0017; programs are executed on cores 104, 106, 108., 0028 Fig. 2; Compiled code 328 may be stored in long-term memory until it is loaded into program memory in memory blocks 110, 112, 114 for execution, 0028). For Claim 17, the prior art does not teach the following limitations when viewed in combination with the other recited limitations: and shared code; and executing a second function using a second CPU in the device, which includes executing second code and the shared code, wherein: the first code is stored in a first region of a memory; the second code is stored in a second region of the memory; and the shared code is stored, without a duplicate copy of the shared code, in a third region of the memory. 13-03 Claims 18-20 are allowable based on dependency from Claim 17. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Double Patenting 08-33 AIA The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. 08-34 AIA Claim s 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim s 1-20 of U.S. Patent No. 12/242379 (hereinafter “reference patent”) . Although the claims at issue are not identical, they are not patentably distinct from each other because Claims 1-20 of the instant application anticipate Claims 1-20 of the reference patent . For Claim 1, the claim limitations in the instant application (method.. .storing first code, storing second code, storing shared code) are generic to (broader than) Claim 1 of the reference patent (refence patent recites other limitations). For Claim 2, the claim limitations of the instant application are generic to (broader than) Claims 1 of the reference patent. For Claim 3, the claim limitations of the instant application are generic to (broader than) Claims 1 of the reference patent. For Claim 4, the claim limitations of the instant application are generic to (broader than) Claim 6 of the reference patent. For Claim 5, the claim limitations of the instant application are generic to (broader than) Claim 1 of the reference patent. For Claim 6, the claim limitations of the instant application are generic to (broader than) Claim 1, 2 of the reference patent. For Claim 7, the claim limitations of the instant application are generic to (broader than) Claim 13 of the reference patent. For Claim 8, the claim limitations of the instant application are generic to (broader than) Claim 14 of the reference patent. Claims 2-8 are also rejected based on dependency from Claim 1. For Claim 9, the claim limitations in the instant application (system, first CPU, … second CPU, … memory accessible….) are generic to (broader than) Claim 15 of the reference patent (refence patent recites other limitations). For Claim 10, the claim limitations of the instant application are generic to (broader than) Claims 7 of the reference patent. For Claim 11, the claim limitations of the instant application are generic to (broader than) Claims 9 of the reference patent. For Claim 12, the claim limitations of the instant application are generic to (broader than) Claim 6 of the reference patent. For Claim 13, the claim limitations of the instant application are generic to (broader than) Claim 15 of the reference patent. For Claim 14, the claim limitations of the instant application are generic to (broader than) Claim 15 of the reference patent. For Claim 15, the claim limitations of the instant application are generic to (broader than) Claim 19 of the reference patent. For Claim 16, the claim limitations of the instant application are generic to (broader than) Claim 14 of the reference patent. Claims 10-16 are also rejected based on dependency from Claim 9. For Claim 17, the claim limitations in the instant application (method, executing … first CPU, … executing … second CPU, wherein .. first code, second code, shared code) are generic to (broader than) Claim 15 of the reference patent (refence patent recites other limitations). For Claim 18, the claim limitations of the instant application are generic to (broader than) Claim 7 of the reference patent. For Claim 19, the claim limitations of the instant application are generic to (broader than) Claim 1 of the reference patent. For Claim 20, the claim limitations of the instant application are generic to (broader than) Claim 6 of the reference patent. Claims 18-20 are also rejected based on dependency from Claim 17. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAUTAM SAIN whose telephone number is (571)270-3555. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached at 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GAUTAM SAIN/Primary Examiner, Art Unit 2135 Application/Control Number: 19/045,630 Page 2 Art Unit: 2135 Application/Control Number: 19/045,630 Page 3 Art Unit: 2135 Application/Control Number: 19/045,630 Page 4 Art Unit: 2135 Application/Control Number: 19/045,630 Page 5 Art Unit: 2135 Application/Control Number: 19/045,630 Page 6 Art Unit: 2135 Application/Control Number: 19/045,630 Page 7 Art Unit: 2135 Application/Control Number: 19/045,630 Page 8 Art Unit: 2135 Application/Control Number: 19/045,630 Page 9 Art Unit: 2135
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