DETAILED ACTION
Claims 1-20 are present for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 5-8, 11-12, 14-15 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dastidar et al. (US 11,074,208) in view of Okada et al (US2017/0075816).
With respect claim 1, Dastidar et al. teaches a plurality of dynamic capacity devices (see Fig. 1, column 1, line 35; column 4, lines 40-42 and claim 1; memory expansion devices 180 are SCM cards, but can be any external memory that is pluggable or attachable into the computing system 100); and
a processing device, operatively coupled with the plurality of dynamic capacity devices (see Fig. 1 and column 4, lines 14-20; HA coupled to memory. HA 105 is a memory controller. The HA 105 may be integrated into a processor), to perform operations comprising:
receiving, from a host system, a request to perform an input/output (I/O) operation at a first memory region of a first dynamic capacity device of the plurality of dynamic capacity devices (see column 9, lines 30-42; request agent initiates load/store operations);
identifying, based on the data structure, a range of physical addresses of the first dynamic capacity device, wherein the range is associated with the first memory region (see column 3, lines 58-59 and column 7, lines 24-41; IC1 also includes corresponding Home Agent Base Address Table (HBAT) entries (H-BAT0 and H-BAT1) which assigns the address range of A:B to MemPool0 and the address range of B:C to MemPool1. Also in column 8, lines 42-48; HA1 has MemPool0 which is mapped to address range A:B by an HBAT entry. HA2, on the other hand, has MemPool0 which is mapped to address range B:C); and
causing the I/O operation to be performed on a plurality of memory cells addressable by the range of physical addresses at the first dynamic capacity device (see column 6, lines 39-51; computing system performs load/store operations using a routing network configured using the global address map. That is, the global address map can configure the HBAT and SBAT entries, along with the routing network, so that requesting agents (RAs) can access the memory pools in the SAs which are managed by the HAs. That is, the HAs permit RAs to perform load/store operations using the memory expansion devices).
Dastidar et al. does not teach determining, based on a data structure referencing a namespace accessible to the host system and to the plurality of dynamic capacity devices, that the host system is associated with an access privilege to access the first memory region of the first dynamic capacity device.
However, Okada et al. teaches wherein IO translation table is a page table and includes an entry for each page (see paragraph 91). The entry of a page includes fields for a page number (#), a translation active flag, a target device, a physical address, a page size, a virtual address, and access rights… The access rights include a Read access right and a Write access right. The Read access right indicates whether Read access to the page can be executed. The Write access right indicates whether Write access to the page can be executed (see paragraph 92).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Dastidar et al. to include the above mentioned to provide memory access protection (see Okada, paragraph 75).
With respect claim 5, Dastidar et al. does not teaches configuring at least one of: a shared access between one or more host systems and the memory region or an access privilege by the one or more host systems to the memory region.
However, Okada et al. teaches wherein IO translation table is a page table and includes an entry for each page (see paragraph 91). The entry of a page includes fields for a page number (#), a translation active flag, a target device, a physical address, a page size, a virtual address, and access rights… The access rights include a Read access right and a Write access right. The Read access right indicates whether Read access to the page can be executed. The Write access right indicates whether Write access to the page can be executed (see paragraph 92).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Dastidar et al. to include the above mentioned to provide memory access protection (see Okada, paragraph 75).
With respect claim 6, Dastidar et al. teaches creating an entry of the data structure, wherein the entry comprises a mapping between an identifier of the first memory region and the range of physical addresses of the first dynamic capacity device (see column 3, lines 58-59 and column 7, lines 24-41; IC1 also includes corresponding Home Agent Base Address Table (HBAT) entries (H-BAT0 and H-BAT1) which assigns the address range of A:B to MemPool0 and the address range of B:C to MemPool1. Also in column 8, lines 42-48; HA1 has MemPool0 which is mapped to address range A:B by an HBAT entry. HA2, on the other hand, has MemPool0 which is mapped to address range B:C).
With respect claim 7, Dastidar et al. teaches wherein the operations further comprise: identifying data associated with one or more results of the I/O operation, wherein the data is stored on a second plurality of memory cells addressable by a second range of physical addresses associated with a second memory region of the first dynamic capacity device (see column 9, lines 30-42, request agent (the coherency or load-store semantics initiator of memory operations) has a Request Agent—System Address Map (R-SAM) 805. The home agent (the coherency or load-store semantics target of memory operations) has either a H-BAT 810 to map request agent accesses to local memory) and wherein an entry of the data structure comprises a mapping between an identifier of the second memory region and the second range of physical address of the first dynamic capacity device (see column 3, lines 58-59 and column 7, lines 24-41; IC1 also includes corresponding Home Agent Base Address Table (HBAT) entries (H-BAT0 and H-BAT1) which assigns the address range of A:B to MemPool0 and the address range of B:C to MemPool1. Also in column 8, lines 42-48; HA1 has MemPool0 which is mapped to address range A:B by an HBAT entry. HA2, on the other hand, has MemPool0 which is mapped to address range B:C).
With respect claim 8, Dastidar et al. teaches receiving, from a host system, a request to perform an input/output (I/O) operation at a first memory region of a first dynamic capacity device of a plurality of dynamic capacity devices (see column 9, lines 30-42; request agent initiates load/store operations);
identifying, based on the data structure, a range of physical addresses of the first dynamic capacity device, wherein the range is associated with the first memory region (see column 3, lines 58-59 and column 7, lines 24-41; IC1 also includes corresponding Home Agent Base Address Table (HBAT) entries (H-BAT0 and H-BAT1) which assigns the address range of A:B to MemPool0 and the address range of B:C to MemPool1. Also in column 8, lines 42-48; HA1 has MemPool0 which is mapped to address range A:B by an HBAT entry. HA2, on the other hand, has MemPool0 which is mapped to address range B:C); and
causing the I/O operation to be performed on a plurality of memory cells addressable by the range of physical addresses at the first dynamic capacity device (see column 6, lines 39-51; computing system performs load/store operations using a routing network configured using the global address map. That is, the global address map can configure the HBAT and SBAT entries, along with the routing network, so that requesting agents (RAs) can access the memory pools in the SAs which are managed by the HAs. That is, the HAs permit RAs to perform load/store operations using the memory expansion devices).
Dastidar et al. does not teach determining, based on a data structure referencing a namespace accessible to the host system and to the plurality of dynamic capacity devices, that the host system is associated with an access privilege to access the first memory region of the first dynamic capacity device.
However, Okada et al. teaches wherein IO translation table is a page table and includes an entry for each page (see paragraph 91). The entry of a page includes fields for a page number (#), a translation active flag, a target device, a physical address, a page size, a virtual address, and access rights… The access rights include a Read access right and a Write access right. The Read access right indicates whether Read access to the page can be executed. The Write access right indicates whether Write access to the page can be executed (see paragraph 92).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Dastidar et al. to include the above mentioned to provide memory access protection (see Okada, paragraph 75).
With respect claim 11, Dastidar et al. does not teach configuring at least one of: a shared access between one or more host systems and the memory region or an access privilege by the one or more host systems to the memory region.
However, Okada et al. teaches wherein IO translation table is a page table and includes an entry for each page (see paragraph 91). The entry of a page includes fields for a page number (#), a translation active flag, a target device, a physical address, a page size, a virtual address, and access rights… The access rights include a Read access right and a Write access right. The Read access right indicates whether Read access to the page can be executed. The Write access right indicates whether Write access to the page can be executed (see paragraph 92).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Dastidar et al. to include the above mentioned to provide memory access protection (see Okada, paragraph 75).
With respect claim 12, Dastidar et al. teaches creating an entry of the data structure, wherein the entry comprises a mapping between an identifier of the first memory region and the range of physical addresses of the first dynamic capacity device (see column 3, lines 58-59 and column 7, lines 24-41; IC1 also includes corresponding Home Agent Base Address Table (HBAT) entries (H-BAT0 and H-BAT1) which assigns the address range of A:B to MemPool0 and the address range of B:C to MemPool1. Also in column 8, lines 42-48; HA1 has MemPool0 which is mapped to address range A:B by an HBAT entry. HA2, on the other hand, has MemPool0 which is mapped to address range B:C).
With respect claim 14, Dastidar et al. teaches identifying data associated with one or more results of the I/O operation, wherein the data is stored on a second plurality of memory cells addressable by a second range of physical addresses associated with a second memory region of the first dynamic capacity device (see column 9, lines 30-42, request agent (the coherency or load-store semantics initiator of memory operations) has a Request Agent—System Address Map (R-SAM) 805. The home agent (the coherency or load-store semantics target of memory operations) has either a H-BAT 810 to map request agent accesses to local memory), and wherein an entry of the data structure comprises a mapping between an identifier of the second memory region and the second range of physical address of the first dynamic capacity device (see column 3, lines 58-59 and column 7, lines 24-41; IC1 also includes corresponding Home Agent Base Address Table (HBAT) entries (H-BAT0 and H-BAT1) which assigns the address range of A:B to MemPool0 and the address range of B:C to MemPool1. Also in column 8, lines 42-48; HA1 has MemPool0 which is mapped to address range A:B by an HBAT entry. HA2, on the other hand, has MemPool0 which is mapped to address range B:C).
With respect claim 15, Dastidar et al. teaches receiving, from a host system, a request to perform an input/output (I/O) operation at a first memory region of a first dynamic capacity device of a plurality of dynamic capacity devices (see column 9, lines 30-42; request agent initiates load/store operations);
identifying, based on the data structure, a range of physical addresses of the first dynamic capacity device, wherein the range is associated with the first memory region (see column 3, lines 58-59 and column 7, lines 24-41; IC1 also includes corresponding Home Agent Base Address Table (HBAT) entries (H-BAT0 and H-BAT1) which assigns the address range of A:B to MemPool0 and the address range of B:C to MemPool1. Also in column 8, lines 42-48; HA1 has MemPool0 which is mapped to address range A:B by an HBAT entry. HA2, on the other hand, has MemPool0 which is mapped to address range B:C); and
causing the I/O operation to be performed on a plurality of memory cells addressable by the range of physical addresses at the first dynamic capacity device (see column 6, lines 39-51; computing system performs load/store operations using a routing network configured using the global address map. That is, the global address map can configure the HBAT and SBAT entries, along with the routing network, so that requesting agents (RAs) can access the memory pools in the SAs which are managed by the HAs. That is, the HAs permit RAs to perform load/store operations using the memory expansion devices).
Dastidar et al. does not teach determining, based on a data structure referencing a namespace accessible to the host system and to the plurality of dynamic capacity devices, that the host system is associated with an access privilege to access the first memory region of the first dynamic capacity device.
However, Okada et al. teaches wherein IO translation table is a page table and includes an entry for each page (see paragraph 91). The entry of a page includes fields for a page number (#), a translation active flag, a target device, a physical address, a page size, a virtual address, and access rights… The access rights include a Read access right and a Write access right. The Read access right indicates whether Read access to the page can be executed. The Write access right indicates whether Write access to the page can be executed (see paragraph 92).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Dastidar et al. to include the above mentioned to provide memory access protection (see Okada, paragraph 75).
With respect claim 19, Dastidar et al. teaches creating an entry of the data structure, wherein the entry comprises a mapping between an identifier of the first memory region and the range of physical addresses of the first dynamic capacity device (see column 3, lines 58-59 and column 7, lines 24-41; IC1 also includes corresponding Home Agent Base Address Table (HBAT) entries (H-BAT0 and H-BAT1) which assigns the address range of A:B to MemPool0 and the address range of B:C to MemPool1. Also in column 8, lines 42-48; HA1 has MemPool0 which is mapped to address range A:B by an HBAT entry. HA2, on the other hand, has MemPool0 which is mapped to address range B:C).
With respect claim 20, Dastidar et al. teaches identifying data associated with one or more results of the I/O operation, wherein the data is stored on a second plurality of memory cells addressable by a second range of physical addresses associated with a second memory region of the first dynamic capacity device (see column 9, lines 30-42, request agent (the coherency or load-store semantics initiator of memory operations) has a Request Agent—System Address Map (R-SAM) 805. The home agent (the coherency or load-store semantics target of memory operations) has either a H-BAT 810 to map request agent accesses to local memory), and wherein an entry of the data structure comprises a mapping between an identifier of the second memory region and the second range of physical address of the first dynamic capacity device (see column 3, lines 58-59 and column 7, lines 24-41; IC1 also includes corresponding Home Agent Base Address Table (HBAT) entries (H-BAT0 and H-BAT1) which assigns the address range of A:B to MemPool0 and the address range of B:C to MemPool1. Also in column 8, lines 42-48; HA1 has MemPool0 which is mapped to address range A:B by an HBAT entry. HA2, on the other hand, has MemPool0 which is mapped to address range B:C).
Claim(s) 2, 9 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dastidar et al. (US 11,074,208) and Okada et al (US2017/0075816) as applied to claims 1, 8 and 15 above, and further in view of Lee et al. (US2023/0359379)
With respect claim 2, Dastidar et al. and Okada et al. do not teach wherein each of the plurality of dynamic capacity devices is connected to the host system via a respective plurality of Compute Express Link (CXL) link.
However, Lee et al. teaches wherein each of the plurality of memory devices is a dynamic capacity device connected to the host system via a respective plurality of Compute Express Link (CXL) links (see paragraph 143; host 201 may be directly connected with the plurality of memory devices 202a and 202b. The host 201, the CXL storage 210, and the plurality of CXL memories 220_1 to 220_n may be connected with the CXL switch SW_CXL and may communicate with each other through the CXL switch).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Dastidar et al. and Okada et al. to include the above mentioned to efficiently use the memory (see Lee, paragraph 194).
With respect claim 9, Dastidar et al. and Okada et al. do not teach wherein each of the plurality of dynamic capacity devices is connected to the host system via a respective plurality of Compute Express Link (CXL) link.
However, Lee et al. teaches wherein each of the plurality of memory devices is a dynamic capacity device connected to the host system via a respective plurality of Compute Express Link (CXL) links (see paragraph 143; host 201 may be directly connected with the plurality of memory devices 202a and 202b. The host 201, the CXL storage 210, and the plurality of CXL memories 220_1 to 220_n may be connected with the CXL switch SW_CXL and may communicate with each other through the CXL switch).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Dastidar et al. and Okada et al. to include the above mentioned to efficiently use the memory (see Lee, paragraph 194).
With respect claim 16, Dastidar et al. and Okada et al. do not teach wherein each of the plurality of dynamic capacity devices is connected to the host system via a respective plurality of Compute Express Link (CXL) link.
However, Lee et al. teaches wherein each of the plurality of memory devices is a dynamic capacity device connected to the host system via a respective plurality of Compute Express Link (CXL) links (see paragraph 143; host 201 may be directly connected with the plurality of memory devices 202a and 202b. The host 201, the CXL storage 210, and the plurality of CXL memories 220_1 to 220_n may be connected with the CXL switch SW_CXL and may communicate with each other through the CXL switch).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Dastidar et al. and Okada et al. to include the above mentioned to efficiently use the memory (see Lee, paragraph 194).
Claim(s) 3-4, 10, 13 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Dastidar et al. (US 11,074,208) and Okada et al (US2017/0075816) as applied to claims 1, 8 and 15 above, and further in view of Clark et al. (US2022/0114086).
With respect claim 3, Dastidar et al. teaches wherein the data structure comprises a plurality of entries, wherein each entry comprises an identifier of a memory region, an identifier of a corresponding range of physical addresses of the plurality of dynamic capacity devices region (see column 3, lines 58-59 and column 7, lines 24-41; IC1 also includes corresponding Home Agent Base Address Table (HBAT) entries (H-BAT0 and H-BAT1) which assigns the address range of A:B to MemPool0 and the address range of B:C to MemPool1. Also in column 8, lines 42-48; HA1 has MemPool0 which is mapped to address range A:B by an HBAT entry. HA2, on the other hand, has MemPool0 which is mapped to address range B:C).
Dastidar et al. and Okada et al. do not teach wherein an identifier of one or more host systems of a plurality of host systems, wherein the memory region is accessible by the one or more host systems.
However, Clark et al. teaches host-managed device memory (HDM) decoders 126 that may be programmed to facilitate a mapping of host to device physical addresses for use in system memory (e.g., pooled system memory) (see paragraph 21).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Dastidar et al. and Okada et al. to include the above mentioned to improve the system (see Clark, paragraph 16).
With respect claim 4, Dastidar et al. and Okada et al. do not teach wherein the system further comprises a fabric management component, and wherein the fabric management component comprises firmware embedded within a baseboard management controller.
However, Clark et al. teaches wherein circuitry 1020 may be arranged to execute one or more software or firmware implemented logic, components, agents, or modules 1022-a (e.g., implemented, at least in part, by a controller of a memory device) (see paragraph 85).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the system taught by Dastidar et al. and Okada et al. to include the above mentioned to improve the system (see Clark, paragraph 16).
With respect claim 10, Dastidar et al. teaches wherein the data structure comprises a plurality of entries, wherein each entry comprises an identifier of a memory region, an identifier of a corresponding range of physical addresses of the plurality of dynamic capacity devices (see column 3, lines 58-59 and column 7, lines 24-41; IC1 also includes corresponding Home Agent Base Address Table (HBAT) entries (H-BAT0 and H-BAT1) which assigns the address range of A:B to MemPool0 and the address range of B:C to MemPool1. Also in column 8, lines 42-48; HA1 has MemPool0 which is mapped to address range A:B by an HBAT entry. HA2, on the other hand, has MemPool0 which is mapped to address range B:C).
Dastidar et al. and Okada et al. do not teach wherein an identifier of one or more host systems of a plurality of host systems, wherein the memory region is accessible by the one or more host systems.
However, Clark et al. teaches host-managed device memory (HDM) decoders 126 that may be programmed to facilitate a mapping of host to device physical addresses for use in system memory (e.g., pooled system memory) (see paragraph 21).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Dastidar et al. and Okada et al. to include the above mentioned to improve the system (see Clark, paragraph 16).
With respect claim 13, Dastidar et al. and Okada et al. do not teach wherein a fabric management component associated with the plurality of dynamic capacity devices comprises firmware embedded within a baseboard management controller.
However, Clark et al. teaches wherein circuitry 1020 may be arranged to execute one or more software or firmware implemented logic, components, agents, or modules 1022-a (e.g., implemented, at least in part, by a controller of a memory device) (see paragraph 85).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the medium taught by Dastidar et al. and Okada et al. to include the above mentioned to improve the system (see Clark, paragraph 16).
With respect claim 17, Dastidar et al. teaches wherein the data structure comprises a plurality of entries, wherein each entry comprises an identifier of a memory region, an identifier of a corresponding range of physical addresses of the plurality of dynamic capacity devices(see column 3, lines 58-59 and column 7, lines 24-41; IC1 also includes corresponding Home Agent Base Address Table (HBAT) entries (H-BAT0 and H-BAT1) which assigns the address range of A:B to MemPool0 and the address range of B:C to MemPool1. Also in column 8, lines 42-48; HA1 has MemPool0 which is mapped to address range A:B by an HBAT entry. HA2, on the other hand, has MemPool0 which is mapped to address range B:C).
Dastidar et al. and Okada et al. do not teach wherein an identifier of one or more host systems of a plurality of host systems, wherein the memory region is accessible by the one or more host systems.
However, Clark et al. teaches host-managed device memory (HDM) decoders 126 that may be programmed to facilitate a mapping of host to device physical addresses for use in system memory (e.g., pooled system memory) (see paragraph 21).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Dastidar et al. and Okada et al. to include the above mentioned to improve the system (see Clark, paragraph 16).
With respect claim 18, Dastidar et al. and Okada et al. do not teach configuring at least one of: a shared access between one or more host systems and the memory region or an access privilege by the one or more host systems to the memory region.
However, Clark et al. teaches wherein circuitry 1020 may be arranged to execute one or more software or firmware implemented logic, components, agents, or modules 1022-a (e.g., implemented, at least in part, by a controller of a memory device) (see paragraph 85).
It would have been obvious to a person having ordinary skill in the art to which said subject matter pertains before the effective filing date of the claimed invention to have modified the method taught by Dastidar et al. and Okada et al. to include the above mentioned to improve the system (see Clark, paragraph 16).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Choi et al. (US2023/0289074) teaches memory/storage capacity expander for large memory resource pooling.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARACELIS RUIZ whose telephone number is (571)270-1038. The examiner can normally be reached Monday-Friday 11:00am-7:30pm.
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/ARACELIS RUIZ/ Primary Examiner, Art Unit 2139