Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/5/25 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ma et al. (US 11,050,431) in view of Lee et al (US 2016/0269040).
With regard to claim 1, Ma teaches:
An analog-to-digital converter (ADC) comprising: a first digital-to-analog converter (DAC) (11A Fig. 1A) configured to change a signal level (SW1 Fig. 1A) of a first node based on one of a first input analog signal and a second input analog signal (Vi Fig. 1A) , a second DAC (11B Fig 1A) configured to change a signal level (SW1 Fig. 1A) of a second node based on one of the first input analog signal and the second input analog signal ; a comparator (12 Fig. 1A) configured to compare the signal level of the first node and the signal level of the second node; and a controller (13 Fig 1A).
Ma fails to teach:
configured to generate a first digital value for the first DAC and a second digital value for the second DAC based on an output of the comparator during a first conversion phase corresponding to a first sampling phase, input the first digital value into the second DAC before a second sampling phase, and input the second digital value into the first DAC before the second sampling phase.
Lee teaches:
(Figs. 7-8; para 108//the timing adjuster 56 generates a plurality of timing signals, and can select the timing signals in which the first and second SAR ADCs 10 and 20 can complete the analog-to-digital conversion operation…That is, the timing adjuster 56 can select the timing signals … in which the LSB of the second digital signal Dout2 can be determined, among the plurality of generated timing signals, before the sampling signal S is changed from the second level (e.g., a logic low level) to the first level (e.g., a logic high level).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to apply the timing adjustment or the conversion of the first DAC and the second DAC in one sampling period as taught by Lee in the converter of Ma for the benefit to provide a semiconductor device with a reduced size so critical in electronic devices.
With regard to claim 3, Ma discloses:
The ADC of claim 1, further comprising: a first capacitor and a second capacitor charged separately based on a corresponding input analog signal of the first input analog signal and the second input analog signal during a sampling phase (the capacitors are separately charged because the two analog input signals are driven by different switches cycle (SW1, SW2).
With regard to claim 6, Ma fails to teach:
The ADC of claim 1, wherein the controller is configured to incrementally generate the first digital value and the second digital value during the first conversion phase.
Lee discloses the above limitations in Figures 7-8. Figure 7 discloses a timing controller
and a timing adjustor; Figure 8 discloses a timing adjustor that generates the digital
signals (MSB and LSB for both converters) for the first DAC and second DACs in a
sampling period before period before the next sampling period. Therefore, it would have
been obvious to one having ordinary skill in the art before the effective filing date of the
application to apply the timing adjustment of the conversion of the first DAC and the
second DAC in one sampling period as taught by Lee in the converter of Ma for the
benefit to provide a semiconductor device with a reduced size so critical in electronic
devices.
With regard to claim 7, Ma fails to teach
The ADC of claim 1, wherein the controller is configured to input the first digital for determining a least significant bit (LSB) of an output digital value of the ADC into the second DAC before a second sampling phase, and input the second digital value for determining the LSB into the first DAC before the second sampling phase.
Lee discloses the above limitations in Figures 7-8. Lee discloses the above limitations in Figures 7-8. Figure 7 discloses a timing controller and a timing adjustor; Figure 8 discloses a timing adjustor that generates the digital signals (MSB and LSB for both converters) for the first and second DACs in a sampling period before period before the next sampling period. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to apply the timing adjustment of the conversion of the first DAC and the second DAC in one sampling period as taught by Lee in the converter of Ma for the benefit to provide a semiconductor device with a reduced size so critical in electronic devices.
With regard to claim 12, Ma discloses:
A method comprising: changing a signal level of a first node and a signal level of a second node separately based on a corresponding input analog signal of a first input analog signal and a second input analog signal (each SAR ADC is coupled to a node: node that SAR ADC performs digital to analog conversion ) ; comparing, using a comparator (12 Fig. 1A) , the signal level of the first node and the signal level of the second node; inputting, using a controller (13 Fig. 1A) , an input digital value of a first digital-to-analog converter (DAC) generated during a first conversion phase corresponding to a first sampling phase into a second DAC before a second sampling phase;
Ma fails to teach:
and inputting an input digital value of the second DAC generated during the first conversion phase into the first DAC before the second sampling phase, wherein the first DAC is coupled to the first node, and the second DAC is coupled to the second node.
Lee teaches:
(Figs. 7-8; para 108//the timing adjuster 56 generates a plurality of timing signals, and can select the timing signals in which the first and second SAR ADCs 10 and 20 can complete the analog-to-digital conversion operation…That is, the timing adjuster 56 can select the timing signals … in which the LSB of the second digital signal Dout2 can be determined, among the plurality of generated timing signals, before the sampling signal S is changed from the second level (e.g., a logic low level) to the first level (e.g., a logic high level).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to apply the timing adjustment or the conversion of the first DAC and the second DAC in one sampling period as taught by Lee in the converter of Ma for the benefit to provide a semiconductor device with a reduced size so critical in electronic devices.
With regard to claim 16, Ma fails to teach:
The method of claim 12, wherein the inputting of the input digital value of the first DAC generated during the first conversion phase into the second DAC before the second sampling phase comprises inputting the input digital value of the first DAC for determining a least significant bit (LSB) of an output digital value into the second DAC before the second sampling phase.
Lee discloses the above limitations in Figures 7-8. Lee discloses the above limitations in Figures 7-8. Figure 7 discloses a timing controller and a timing adjustor; Figure 8 discloses a timing adjustor that generates the digital signals (MSB and LSB for both converters) for the first DAC and second DAC in a sampling period before period before the next sampling period. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to apply the timing adjustment of the conversion of the first DAC and the second DAC in one sampling period as taught by Lee in the converter of Ma for the benefit to provide a semiconductor device with a reduced size so critical in electronic devices.
With regard to claim 17, Ma fails to discloses:
The method of claim 16, wherein the inputting of the input digital value of the second DAC generated during the first conversion phase into the first DAC before the second sampling phase comprises inputting the input digital value of the second DAC for determining the LSB into the first DAC before the second sampling phase.
Lee discloses the above limitations in Figures 7-8. Lee discloses the above limitations in Figures 7-8. Figure 7 discloses a timing controller and a timing adjustor; Figure 8 discloses a timing adjustor that generates the digital signals (MSB and LSB for both converters) for the first DAC and second DAC in a sampling period before period before the next sampling period. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to apply the timing adjustment of the conversion of the first DAC and the second DAC in one sampling period as taught by Lee in the converter of Ma for the benefit to provide a semiconductor device with a reduced size so critical in electronic devices.
Allowable Subject Matter
Claims 2, 4-5, 8-10, 13-15, 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 11 is allowed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEGUY JEAN PIERRE whose telephone number is (571) 272-1803. The examiner can normally be reached from 8:00-6:30 PM Monday-Thursday. The examiner’s fax phone number is (571) 273-1803. The Examiner email address is peguy.jeanpierre@uspto.gov. If attempts to reach the Examiner are unsuccessful, the Examiner’s supervisor Dameon E. Levi can be reached at (571) 272-2105.
/PEGUY JEAN PIERRE/Primary Examiner, Art Unit 2845
Prosecution Insights