Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
As per the instant application having Application No. 19/045,873, the amendment filed on 5/26/2026 is herein acknowledged. Claims 1 and 15-16 have been amended. Claims 1-19 are pending.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
CLAIM INTERPRETATION
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “processing unit… for storing…” in claim 16. The processing unit has been identified in paragraph 0068 of US 20the Specification as “a processing unit 104 and a memory unit 105. In this example, the bus controller 102 is a PCI Root Complex, the peripheral device 103 is a PCI device, the processing unit 104 is one CPU and the memory unit 105 is a memory and/or cache.”
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
CLAIM CONSTRUCTION
The present application contains contingent limitations. Applicant is reminded that “the broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” See MPEP 2111.04(II).
See Ex parte Schulhauser, Appeal No. 2013-007847, 2016 WL 6277792, at *9 (PTAB, Apr. 28, 2016) (precedential) (holding "The Examiner did not need to present evidence of the obviousness of the remaining method steps of the claim that are not required to be performed under a broadest reasonable interpretation of the claim"); see also Ex parte Katz, Appeal No. 2010-006083, 2011 WL 514314, at *4-5 (BPAI Jan. 27, 2011).” Board Decision pages 5-6, emphasis in original.
Note that the limitations “in response to determining that a trigger condition is fulfilled” (in claim 1) may never be reached within the scope of the claim under the broadest reasonable interpretation since trigger condition may never be fulfilled within the scope of the claim. Applicant is reminded that “the broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” See MPEP211.04(II).
It is suggested method claim 1 be amended to first require that a trigger condition is fulfilled and then in response to determining that the trigger condition is fulfilled, performing the rest of the steps.
Additionally, note that claim 15 has been written as a hybrid claim which recites both a computer program product… comprising a computer readable storage medium… to perform the method… and method steps within the body of the claim that also contain contingent limitations. It is suggested claim 15 be amended in the same manner as claim 1.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 6-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (US 2021/0271421) in view of Pope et al. (US 2006/0288129).
1. A method for storing data in a peripheral device, the method comprising: [Zhu teaches host 120 connected to memory sub-system 110 (fig. 1 and related text) “An example of a memory sub-system is a storage device that is coupled to a central processing unit (CPU) via a peripheral interconnect (e.g., an input/output bus, a storage area network)…” (pars. 0011-0012)]
providing a memory unit with a queue, wherein a processing subsystem comprises a processing unit and the memory unit; and [Zhu teaches controller 115 includes processor 117, local memory 119, sequencer 113 included queues 130 (fig. 1 and related text) “The memory commands in each category are assigned to a queue that is specifically dedicated to commands of that particular category. For example, all read commands may be routed to one queue, all write commands may be routed to another queue, etc. Since a command from only one of the queues may be executed at a time, the memory system services the various queues according to a defined scheduling scheme. “ (par. 0023)] repeatedly performing by the processing unit: receiving a store instruction to store data in the peripheral device; [Zhu teaches “[0034]… If the host command 212 is not a read command and is instead a write command 232, at operation 330, the processing device moves the write command 232 to write command queue 230. Thus… write command queue 230 includes a number of write commands 232 (i.e., a second subset of the host commands 212).” (figs. 2-3 and related text)]
adding an entry in the queue, the entry representing the store instruction; and [Zhu teaches “write command queue 230. In other implementations, multi-level queue structure 130 may include some other number and/or arrangement of queues. Each of the queues in multi-level queue structure 130 may include a collection of commands that are kept in order, such that the first command enqueued in (i.e., added to) a queue is also the first command to be dequeued (i.e. removed)” (par. 0024; see figs. 2-3 and related text)]
in response to determining that a trigger condition is fulfilled, … controller to access the store instructions in the queue for communication with the peripheral device, [Zhu teaches “[0035] At operation 335, the processing device executes commands from read command queue 220 and write command queue 230 using double threshold controlled scheduling. In one implementation, the first threshold is defined by a promotion threshold criterion pertaining to a number of pending commands in the associated queue. The second threshold is defined by an executed transaction threshold criterion pertaining to a number of commands that have been executed since an execution grant was given to the associated queue. In one implementation, sequencer 113 uses both thresholds together to determine when to switch the execution grant 260 from one queue to another, as will be described in more detail below with respect to FIG. 4 and FIG. 5.” (see figs. 3-5 and related text) where as Zhu teaches “An example of a memory sub-system is a storage device that is coupled to a central processing unit (CPU) via a peripheral interconnect (e.g., an input/output bus, a storage area network).” (par. 0011), the controller 115 is interpreted to correspond to bus controller accessing write commands in the queues 130 using sequencer as “[0027] In one implementation, sequencer 113 may begin executing requests from whichever of the read command queue 220 or the write command queue 230 has a number of pending commands that satisfy (e.g., exceed) a corresponding promotion threshold criterion.” “[0029] When write command queue 230 is the currently active queue, each time a write command 232 is executed from the write command queue 230, sequencer 113 may increment a value of counter 250 indicating the number of commands that have been executed since the execution grant 260 was given to the associated queue.” Thus, the memory sub-system corresponding to a peripheral device accessed by host system 120] but Zhu does not expressly disclose the controller as a separate bus controller to access the store instructions in the queue for communication with the peripheral device, the peripheral device configured to connect to the processing subsystem through the bus controller; however, regarding these limitations, Pope teaches [“[0002] A typical computer system includes a processor subsystem (including one or more processors), a memory subsystem (including main memory, cache memory, etc.; also sometimes referred to herein as "host memory"), and a variety of "peripheral devices" connected to the processor subsystem via a peripheral bus. Peripheral devices may include, for example, keyboard, mouse and display adapters, disk drives and CD-ROM drives, network interface devices, and so on.” Where “[0026]… The NIC 116 communicates with the computing device 114 over the bus 118” where bus 118 comprises a PCI Express bus (par. 0022) and “[0027] The NIC 116 has a bus interface controller 235“ (see figs. 1 and 2 and related text) “[0044]… Each such queue has an associated DMA command queue, not shown in FIG. 3, but maintained in the host memory 122…” “[0090] The techniques described herein have been described specifically with respect to the data transfer needs of NICs, but it will be understood that other kinds of peripheral devices aside from NICs can benefit as well. For example other types of peripheral devices might not designate their data transfer DMA queues as TX or RX queues; in a particular embodiment a queue can mix commands for the transfer of data from host memory to peripheral device with commands for the transfer of data in the opposite direction, as well as commands for other purposes entirely.”].
Zhu and Pope are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify Zhu to include the configuration of Pope including a separate bus controller to access the store instructions in the queue for communication with the peripheral device, the peripheral device configured to connect to the processing subsystem through the bus controller as taught by Pope, since doing so would [“reduce the amount of space required on an integrated circuit chip for holding address pointers for a DMA engine used to retrieve data transfer DMA commands from queues in host memory to local look-ahead command memories. This can be accomplished by, roughly described, implementing a mechanism for deriving write addresses into the local store algorithmically from the read pointer for the corresponding DMA command queue in host memory, instead of maintaining a separate write pointer for each local store” (par. 0010)], where one of ordinary skill in the art would have also found it obvious to have the queues and processor of Zhu relocated to host as taught by Pope since doing so would involve rearrangement of parts and it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70, where doing so would at least provide flexibility of design.
Therefore, it would have been obvious to combine Zhu and Pope for the benefit of creating a storage system/method to obtain the invention as specified in claim 1.
2. The method of claim 1, wherein enabling access to the store instructions comprises sending a delayed trigger to the bus controller, thereby triggering the bus controller to fetch the store instructions from the queue [Zhu teaches a delayed trigger may be sent to write queue based on the number of pending commands in the write queue not yet satisfying a first promotion threshold criterion as in steps 415 and 435 of (fig. 4 and related text) or based on the read queue not yet satisfying the first executed threshold criterion as in step 520 (fig. 5 and related text) note Zhu teaches “[0028] If sequencer 113 determines that value of the counter 250 satisfies (e.g., meets or exceeds) a corresponding executed transaction threshold criterion, sequencer 113 may switch the execution grant 260 from the read command queue 220 to the previously inactive write command queue 230 and begin executing the write commands 232. Sequencer 113 may also reset the value of the counter 250. While executing read commands 222 from read command queue 220 and incrementing the counter 250, sequencer 113 may continue to monitor the number of pending commands in each queue. If at any time prior to the value of the counter 250 satisfying the transaction threshold criterion for the read command queue 220, the number of pending write commands 232 in the write command queue 230 satisfies the corresponding promotion threshold criterion, sequencer 113 may switch the execution grant 260 to the write command queue 230 even though the transaction threshold criterion for the read command queue 220 has not yet been satisfied. Thus, responsive to either of the executed transaction threshold criterion for the read command queue 220 being satisfied or the promotion threshold criterion for the write command queue 230 being satisfied, sequencer 113 may switch the execution grant 260 from the read command queue 220 to the write command queue 230. Upon the execution grant 260 being switched to the write command queue 230, sequencer 113 may begin executing write commands 232 against memory component 112.”].
6. The method of claim 2, wherein the trigger condition is the queue being full [Zhu teaches “[0038]… In one implementation, sequencer 113 may continuously or periodically monitor the number of pending commands in both the active and inactive queues. Sequencer 113 may compare the number of pending commands in the inactive queue to the first promotion threshold criterion to determine whether the number of pending commands in the inactive queue satisfies (e.g., meets or exceeds) the corresponding promotion threshold criterion. Depending on the implementation, the first promotion criterion may be expressed as a discreet number of pending commands (e.g., 64 commands) or as a fraction or percentage of the capacity of the inactive queue (e.g., 50% full).”], where Zhu does not expressly set the threshold of the inactive queue to trigger switch of the active queue to the inactive queue as being full; however, it would have been obvious to one of ordinary skill in the art to set this threshold to any fullness value of the inactive queue since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980), and doing so would at least provide flexibility of design.
7. The method of claim 1, wherein the trigger condition is a reception of a signal from the bus controller, and wherein enabling access to the store instructions comprises sending the store instructions to the bus controller [Zhu teaches “the execution grant 260 functions as permission to execute commands from the queue with which it is currently associated. For example, execution grant may have one or more corresponding status bits (e.g., using one-hot encoding), the value of which indicates to sequencer 113 which of read command queue 220 and write command queue 230 is currently active. In such an implementation, a first value (e.g., 2′b01) may indicate that write command queue 230 is active, while a second value (e.g., 2′b10) may indicate that read command queue 220 is active. Sequencer 113 can switch the execution grant 260 to another queue (e.g., by modifying the value of the status bits) according to the double threshold controlled scheduling scheme described herein.” (par. 0027). Where modifying values of the status bits would include a signal from bus controller or sequencer (see par. 0054) where Zhu explains “It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.” Where “[0035] At operation 335, the processing device executes commands from read command queue 220 (thus, sending store instructions to the processing device or bus controller) and write command queue 230 using double threshold controlled scheduling. In one implementation, the first threshold is defined by a promotion threshold criterion pertaining to a number of pending commands in the associated queue. The second threshold is defined by an executed transaction threshold criterion pertaining to a number of commands that have been executed since an execution grant was given to the associated queue. In one implementation, sequencer 113 uses both thresholds together to determine when to switch the execution grant 260 from one queue to another, as will be described in more detail below with respect to FIG. 4 and FIG. 5.” (see figs. 3-5 and related text)].
8. The method of claim 7, wherein the processing unit is configured to set a first flag indicating a signal is required, and wherein the bus controller is configured to set a second flag and send the signal to the processing unit in response to determining that the first flag is set [Zhu teaches “the execution grant 260 functions as permission to execute commands from the queue with which it is currently associated. For example, execution grant may have one or more corresponding status bits (e.g., using one-hot encoding), the value of which indicates to sequencer 113 which of read command queue 220 and write command queue 230 is currently active. In such an implementation, a first value (e.g., 2′b01) may indicate that write command queue 230 is active, while a second value (e.g., 2′b10) may indicate that read command queue 220 is active. Sequencer 113 can switch the execution grant 260 to another queue (e.g., by modifying the value of the status bits) according to the double threshold controlled scheduling scheme described herein.” Where modifying values of the status bits would include a signal from bus controller or sequencer (see par. 0054) and explains “. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.” Thus teaching a first flag or second flag (corresponding to the status bits which may have a first value or second values, thus representing a first flag or second flag) where the active queue is selected according to the first flag or second flag].
9. The method of claim 8, wherein the processing unit is configured to set the first flag in response to determining that the queue has a filling status below a threshold [Zhu teaches “[0029] When write command queue 230 is the currently active queue, each time a write command 232 is executed from the write command queue 230, sequencer 113 may increment a value of counter 250 indicating the number of commands that have been executed since the execution grant 260 was given to the associated queue.” “[0035] At operation 335, the processing device executes commands from read command queue 220 and write command queue 230 using double threshold controlled scheduling. In one implementation, the first threshold is defined by a promotion threshold criterion pertaining to a number of pending commands in the associated queue. The second threshold is defined by an executed transaction threshold criterion pertaining to a number of commands that have been executed since an execution grant was given to the associated queue. In one implementation, sequencer 113 uses both thresholds together to determine when to switch the execution grant 260 from one queue to another, as will be described in more detail below with respect to FIG. 4 and FIG. 5.” where, as the number of commands executed in the active queue exceeds a threshold, the number of commands in the active queue goes below a threshold as well and the active queue is switched to the other queue (see step 520 in fig. 5 and related text) where switching includes setting a first flag or status bit (see par. 0027) thus, setting the first flag to switch the active based on the queue having a filling status below a threshold].
10. The method of claim 1, wherein the processing subsystem comprises multiple bus controllers each being associated with a peripheral device, the method further comprising providing the memory unit with a queue per bus controller, wherein the adding of the entry comprises selecting the queue based on the store instruction [Zhu teaches “[0048] FIG. 6 illustrates an example machine of a computer system 600 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed. In some embodiments, the computer system 600 can correspond to a host system (e.g., the host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system 110 of FIG. 1) or can be used to perform the operations of a controller (e.g., to execute an operating system to perform operations corresponding to sequencer 113 of FIG. 1).” multiple bus controllers may be provided as sequencer 113 in main memory 604 and sequencer 113 in data storage system 618 (fig. 6 and related text) where host computer 120 in fig. 1 accesses memory sub-system 110 and memory sub-system 110 includes queues 130 (fig. 1 and related text) “write command queue 230. In other implementations, multi-level queue structure 130 may include some other number and/or arrangement of queues. Each of the queues in multi-level queue structure 130 may include a collection of commands that are kept in order, such that the first command enqueued in (i.e., added to) a queue is also the first command to be dequeued (i.e. removed)” (par. 0024; see figs. 2-3 and related text)]. Note that it has been held that mere duplication of essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Therefore, one of ordinary still in the art would have found it obvious to duplicate include more than one memory sub-system and components to be accessed by host such as the host memory sub-system 110 of figure 1, since doing so would involve mere duplication of essential working parts and at least provide the benefits of allowing for additional data storage devices and provide flexibility of design. Doing so would include different peripheral devices with queues, which would be accessed according to instructions including addresses as Zhu teaches [“a write command includes instructions to write data to a particular address of the memory component 112.” (0025)].
11. The method of claim 1, wherein the processing subsystem comprises multiple bus controllers each being associated with a peripheral device, and wherein the entry further comprises an indication of the peripheral device, and of the bus controller [Zhu teaches “[0048] FIG. 6 illustrates an example machine of a computer system 600 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed. In some embodiments, the computer system 600 can correspond to a host system (e.g., the host system 120 of FIG. 1) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system 110 of FIG. 1) or can be used to perform the operations of a controller (e.g., to execute an operating system to perform operations corresponding to sequencer 113 of FIG. 1).” “An example of a memory sub-system is a storage device that is coupled to a central processing unit (CPU) via a peripheral interconnect (e.g., an input/output bus, a storage area network).” (par. 0011) where host computer 120 in fig. 1 accesses memory sub-system 110 and memory sub-system 110 includes queues 130 (fig. 1 and related text) and “write command queue 230. In other implementations, multi-level queue structure 130 may include some other number and/or arrangement of queues. Each of the queues in multi-level queue structure 130 may include a collection of commands that are kept in order, such that the first command enqueued in (i.e., added to) a queue is also the first command to be dequeued (i.e. removed)” (par. 0024; see figs. 2-3 and related text), “a write command includes instructions to write data to a particular address of the memory component 112.” (0025)]. Note that it has been held that mere duplication of essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8. Therefore, one of ordinary still in the art would have found it obvious to duplicate include more than one memory sub-system to be accessed by host such as the host memory sub-system 110 of figure 1, with respective components since doing so would involve mere duplication of essential working parts and at least provide the benefits of allowing for additional data storage devices and provide flexibility of design. In doing so, each write command would include address destination information as to which memory devices to access as well as which sequencer or queue the write commands are to be queued in.
12. The method of claim 1, wherein the entry is stored as cacheline in a cache of the memory unit [Zhu teaches “[0022] The memory sub-system 110 can also include additional circuitry or components that are not illustrated. In some embodiments, the memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., a row decoder and a column decoder) that can receive an address from the controller 115 and decode the address to access the memory components 112A to 112N.”].
13. The method of claim 2, further comprising: in response to receiving the delayed trigger by the bus controller: retrieving store instructions from the queue; forwarding the store instructions to the peripheral device; and … and storing the fetched data [“while a write command includes instructions to write data to a particular address of the memory component 112.” (par. 0025) “Upon the execution grant 260 being switched to the write command queue 230, sequencer 113 may begin executing write commands 232 against memory component 112. “ (par. 0028) “[0029] When write command queue 230 is the currently active queue, each time a write command 232 is executed from the write command queue 230, sequencer 113 may increment a value of counter 250 indicating the number of commands that have been executed since the execution grant 260 was given to the associated queue.”] but Zhu does not expressly disclose fetching by the peripheral device data from the memory unit through Direct Memory Access (DMA) requests; however, regarding these limitations, Pope teaches [“[0002]… Communication with peripheral devices can also take place via direct memory access (DMA), in which the peripheral devices (or another agent on the peripheral bus) transfers data directly between the memory subsystem and one of the preassigned regions of address space assigned to the peripheral devices.” “[0045] FIG. 5 is a block diagram of various data structures used by the system of FIGS. 1-3 in order to support separate transmit and receive queues for each of the VNICs. The diagram indicates which structures exist in host memory 122 and which exist on the NIC 116. The transmit and receive data buffers, the transmit and receive DMA descriptor queues, as well as one or more event queues, are all resident in host memory 122 and made up of generalized buffers which can be discontiguous and interspersed with each other in host memory 122. In FIG. 5, the buffers being used as transmit data buffers are identified as "TX DATA BUF #n", and the buffers being used for a TX DMA command queue (or more simply, a transmit queue) are identified as "TX QUEUE BUF #n". The buffers being used for the event queue are identified as "TX EV QUEUE BUF #n". Additional buffers in host memory 122, not shown explicitly in FIG. 5, are used for receive data buffers and for a RX DMA command queue (also called simply a receive queue). One process may have any number of transmit, receive and event queues, and all of them share the pool of generalized buffers that have been mapped into that process's virtual address space.” (See figs. 4 and 6-7 and related text) where “[0090] The techniques described herein have been described specifically with respect to the data transfer needs of NICs, but it will be understood that other kinds of peripheral devices aside from NICs can benefit as well. For example other types of peripheral devices might not designate their data transfer DMA queues as TX or RX queues; in a particular embodiment a queue can mix commands for the transfer of data from host memory to peripheral device with commands for the transfer of data in the opposite direction, as well as commands for other purposes entirely.”].
It would have been obvious to a person of ordinary skill in the art to modify Zhu to include fetching by the peripheral device data from the memory unit through Direct Memory Access (DMA) requests as taught by Pope since doing so would provide the benefits of [fast and efficient data accesses].
14. The method of claim 13, further comprising while or after processing the queue, the bus controller updating a fill state indicator of the queue [Zhu teaches “[0029] When write command queue 230 is the currently active queue, each time a write command 232 is executed from the write command queue 230, sequencer 113 may increment a value of counter 250 indicating the number of commands that have been executed since the execution grant 260 was given to the associated queue.” Where “ In one implementation, sequencer 113 queries the inactive queue to determine how many pending commands are stored in that queue. The number of pending commands may include commands stored in the queue but that have not yet been executed or scheduled for execution for sequencer 113. In another implementation, sequencer 113 maintains a counter (separate from counter 250) for each of read command queue 220 and write command queue 230 that is incremented each time a command is added to the queue and decremented each time a command is executed from the queue. Accordingly, the value of these counters at any point in time will represent the number of pending commands in the corresponding queue.” (par. 0037)].
15. A computer program product for storing data in a peripheral device, the computer program product comprising a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code executable by a system to cause the system to perform a method comprising: repeatedly performing by a processing unit, wherein a processing subsystem comprises the processing unit and a memory unit with a queue: receiving a store instruction to store data in the peripheral device; adding an entry in the queue, the entry representing the store instruction; and in response to determining that a trigger condition is fulfilled, enabling a separate bus controller to access the store instructions in the queue for communication with the peripheral device, the peripheral device configured to connect to the processing subsystem through the bus controller [The rationale in the rejection of claim 1 is herein incorporated].
16. A processing unit for a computer system for storing data in a peripheral device, the processing unit being configured for: repeatedly: receiving a store instruction to store data in the peripheral device; adding an entry in a queue, the entry representing the store instruction, wherein the queue is in a memory unit and a processing subsystem comprises the memory unit and a processing unit; and in response to determining that a trigger condition is fulfilled, enabling a bus controller to access the store instructions in the queue for communication with the peripheral device, the peripheral device configured to connect to the processing subsystem through the bus controller [The rationale in the rejection of claim 1 is herein incorporated].
17. The processing unit of claim 16, wherein the processing unit is further configured to receive a signal from the bus controller, wherein the trigger condition is the receiving of the signal [The rationale in the rejection of claim 7 is herein incorporated].
Claim(s) 3-5 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhu et al. (US 2021/0271421) in view of Pope et al. (US 2006/0288129) as applied above with respect to claims 1 and 16 and further in view of Sharma et al. (US 20250110666).
3. The combination of Zhu and Pope teaches The method of claim 2, but does not expressly disclose further comprising: upon receiving a first store instruction or a store instruction following the sending of the delayed trigger, setting a timer to a time delay and starting the timer, wherein the trigger condition is an expiration of the timer; however, regarding these limitations, Sharma teaches [“the controller 102 in the data storage device 100 can trace how long a given command has been pending in a queue in the data storage device 100 and consume the command just before the command is about to timeout (e.g., to give enough time for the data storage device to recover and still avoid command time out). Additionally, the data storage device 100 can attempt to prioritize a few commands over others and try to ensure that critical operations encounter higher performance even in a critical path.” (par. 0057) “such as by starting a timer or maintaining a counter regarding how many operations were issued within the data storage device 100 since a given command was received. Timer expiry is a logical point at which the controller 102 consumes data. In some cases where the controller 102 determines that the consumption of data is not possible, the controller 102 can override the worst-case performance (WCP) time request. This ensures the data storage device 100 can still perform more-critical internal operation while not timing out on a host command.”].
Zhu, Pope and Sharma are analogous art because they are from the same field of endeavor of memory access and control.
Before the effective filing date of the claimed inventions, it would have been obvious to a person of ordinary skill in the art to modify the combination of Zhu and Pope to include setting a timer to a time delay and starting the timer, wherein the trigger condition is an expiration of the timer as taught by Sharma since doing so would provide the benefits of [“delaying execution of each write command of the plurality of write commands provides the controller with time to perform a memory operation to increase an amount of available SLC blocks in the memory.” (par. 0012)].
Therefore, it would have been obvious to combine Zhu, Pope and Sharma for the benefit of creating a storage system/method to obtain the invention as specified in claim 3.
4. The method of claim 3, further comprising: determining using a fill state indicator whether the queue is full; and in response to determining that the queue is full, determining that the timer is prematurely expired for prematurely sending the delayed trigger [Zhu teaches “[0038]… In one implementation, sequencer 113 may continuously or periodically monitor the number of pending commands in both the active and inactive queues. Sequencer 113 may compare the number of pending commands in the inactive queue to the first promotion threshold criterion to determine whether the number of pending commands in the inactive queue satisfies (e.g., meets or exceeds) the corresponding promotion threshold criterion. Depending on the implementation, the first promotion criterion may be expressed as a discreet number of pending commands (e.g., 64 commands) or as a fraction or percentage of the capacity of the inactive queue (e.g., 50% full).”], where Zhu does not expressly set the threshold of the inactive queue to trigger switch of the active queue to the inactive queue as being full; however, it would have been obvious to one of ordinary skill in the art to set this threshold to any fullness value of the inactive queue since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980), and doing so would at least provide flexibility of design.] where upon reaching the queue threshold, which may be the queue being full, the system/method of Zhu immediately ends the delay in selecting the inactive queue. Zhu does not expressly teach expiring the timer; however, Sharma teaches [“such as by starting a timer or maintaining a counter regarding how many operations were issued within the data storage device 100 since a given command was received. Timer expiry is a logical point at which the controller 102 consumes data. In some cases where the controller 102 determines that the consumption of data is not possible, the controller 102 can override the worst-case performance (WCP) time request. This ensures the data storage device 100 can still perform more-critical internal operation while not timing out on a host command.”], where since timer expiry is defined as the time point at which they controller consumes data, consuming data upon a queue meeting the promotion threshold of Zhu to become the active queue includes prematurely expiring the timer.
5. The method of claim 3, wherein the time delay is a preset amount of time or an implicit delay of a communication between the processing unit and the bus controller [Sharma teaches “(If a host protocol defines a command timeout, the controller 102 can consume the command before the timeout). This gives the maximum amount of time for the data storage device 100 to recover from critical situations without timing out. In another embodiment, the controller 102 can prioritize some pending commands overs others based on criteria, such as, but not limited to, device type, partition, queue priority, and command type.” (par. 0061)].
18. The processing unit of claim 16, comprising a timer, the processing unit further configured to: upon receiving a first store instruction or a store instruction following a sending of a delayed trigger, set the timer to a time delay and start the timer, wherein the trigger condition is an expiration of the timer [The rationale in the rejection of claim 3 is herein incorporated].
19. The processing unit of claim 18, wherein the time delay is a preset amount of time or an implicit delay of a communication between the processing unit and the bus controller [The rationale in the rejection of claim 5 is herein incorporated].
ACKNOWLEDGEMENT OF ISSUES RAISED BY APPLICANT
Response to Amendment
Applicant's arguments filed on 5/26/2026 have been fully considered but are moot in view of new ground(s) of rejection.
CLOSING COMMENTS
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
a. STATUS OF CLAIMS IN THE APPLICATION
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-19 have received a first action on the merits and are subject of a final rejection.
b. DIRECTION OF FUTURE CORRESPONDENCES
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June 29, 2026
/YAIMA RIGOL/
Primary Examiner, Art Unit 2135
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