Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2/5/25 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 10, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Manganaro et al. (US 2022/0224347) in view of Schreier et al. (US 2007/0035426).
With regard to claim 1, Manganaro teaches:
A residue generation arrangement for use in a continuous-time stage of an analog-to-digital converter (ADC) (Fig. 1), the residue generation arrangement comprising:a forward path including a continuous-time filter (224 Fig. 2) , the forward path coupled with an analog input (Vin Fig. 2) and configured for receiving an analog input signal applied to the analog input and generating a delayed analog input signal (236 Fig. 2) ;a feedforward path coupled in parallel with the forward path, the feedforward path including: a quantizer for digitizing the analog input signal to generate a digital signal (212 Fig. 2); and a digital-to-analog converter (DAC) coupled with an output of the quantizer (216 Fig. 2) and configured for receiving the digital signal from the quantizer and generating a feedforward path analog output signal based on the digital signal generated by the quantizer; a summation node (218 Fig. 2) configured for generating a residue signal based on the delayed analog input signal (236 Fig. 2) and the feedforward path analog output signal (216 Fig. 2).
Manganaro fails to teach:
and a timing adjustment circuit configured for receiving a clock signal and an adjustment signal and, in response, generating a delayed or advanced clock signal that is applied to a clock input of one or both of the quantizer and the DAC to adjust a clock phase or clock delay of the feedforward path.
Schreier teaches:
A timing measurement circuit detects a difference in the timing of the ADC sampling time and the DAC update time and a timing adjustment circuit, responsive to the timing measurement circuit, adjusts the timing of at least one of the DAC and ADC clocks for aligning their respective update and sampling times. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to have applied the teaching of Schreier in the continuous time converter of Manganaro for the benefit to accurately adjust and synchronize the timing of the various circuit elements of the converter.
With regard to claim 2, Schreier discloses:
The residue generation arrangement of claim 1, wherein the timing adjustment circuit includes one or more of a phase interpolator, a delay lock loop (delay adjustment circuit), a tunable delay line, and a tunable delay circuit. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to have applied the teaching of Schreier in the continuous time converter of Manganaro for the benefit to accurately adjust and synchronize the timing of the various circuit elements of the converter.
With regard to claim 10 Mangarano discloses:
The residue generation arrangement of claim 1, wherein the continuous-time filter has a fixed delay (34 Fig. 2).
With regard to claim 11 Mangarano teaches:
A residue generation arrangement for use in a continuous-time analog-to- digital converter (ADC), the residue generation arrangement comprising:a first continuous-time stage including: a forward path including a continuous-time filter (224 Fig. 2), the forward path coupled with an analog input and configured for receiving an analog input signal (Vin Fig. 2) applied to the analog input and generating a delayed analog input signal (236 Fig.2) ;a feedforward path coupled in parallel with the forward path, the feedforward path including: a first quantizer for digitizing the analog input signal to generate a digital signal (212 Fig. 2) ; and a digital-to-analog converter (DAC) coupled with an output of the first quantizer (216 Fig.2) and configured for receiving the digital signal from the first quantizer and generating a feedforward path analog output signal based on the digital signal generated by the first quantizer; a summation node (218 Fig. 2) configured for generating a residue signal based on the delayed analog input signal (236 Fig. 2) and the feedforward path analog output signal (216 Fig. 2) ;
Manganaro fails to teach:
a timing adjustment circuit configured for receiving a clock signal and an adjustment signal and, in response, generating a delayed or advanced clock signal that is applied to a clock input of one or both of the first quantizer and the DAC to adjust a clock phase or clock delay of the feedforward path; and a calibration unit configured for controlling a relationship between the delayed clock signal and the clock signal applied to an input of the digital-to-analog converter (DAC).
Schreier teaches:
A timing measurement circuit detects a difference in the timing of the ADC sampling time and the DAC update time and a timing adjustment circuit, responsive to the timing measurement circuit, adjusts the timing of at least one of the DAC and ADC clocks for aligning their respective update and sampling times. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to have applied the teaching of Schreier in the continuous time converter of Manganaro for the benefit to accurately adjust and synchronize the timing of the various circuit elements of the converter.
With regard to claim 18, Manganaro discloses:
18. A method of using an analog-to-digital converter (ADC), the method comprising: receiving an analog input signal applied to an analog input (Vin Fig. 2) and generating a delayed analog input signal (236 Fig. 2) ; digitizing, via a feedforward path, the analog input signal to generate a digital signal (232 Fig. 2) ; receiving the digital signal and generating a feedforward path analog output signal (216 Fig. 2) based on the digital signal; generating a residue signal (Vres Fig.2) based on the delayed analog input signal and the feedforward path analog output signal;
and receiving a clock signal and an adjustment signal and, in response, generating a delayed or advanced clock signal that is applied to a clock input of one or both of a quantizer and a digital-to-analog converter to adjust a clock phase or clock delay of the feedforward path.
Manganaro fails to teach:
and receiving a clock signal and an adjustment signal and, in response, generating a delayed or advanced clock signal that is applied to a clock input of one or both of a quantizer and a digital-to-analog converter to adjust a clock phase or clock delay of the feedforward path.
Schreier discloses:
A timing measurement circuit detects a difference in the timing of the ADC sampling time and the DAC update time and a timing adjustment circuit, responsive to the timing measurement circuit, adjusts the timing of at least one of the DAC (24a Fig.2) and ADC (20a Fig. 2) clocks for aligning their respective update and sampling times (Fig.2 the clock input CKIN to the CKD signal (or one with a fixed delay 34 as explained) and an adjustable or programmable delay line from the master clock CKIN to the adjustment delay circuit 30 from the master clock CKIN to the CKA signal.). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to have applied the teaching of Schreier in the continuous time converter of Manganaro for the benefit to accurately adjust and synchronize the timing of the various circuit elements of the converter.
With regard to claim 19, Mangarano fails to teach:
19. The method of claim 18, further comprising: controlling a relationship between the delayed clock signal and the clock signal applied to an input of the digital-to-analog converter.
Schreier teaches:
the clock input CKIN to the CKD signal (or one with a fixed delay 34 as explained) and an adjustable or programmable delay line from the master clock CKIN to the adjustment delay circuit 30 from the master clock CKIN to the CKA signal. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to have applied the teaching of Schreier in the continuous time converter of Manganaro for the benefit to accurately adjust and synchronize the timing of the various circuit elements of the converter.
With regard to claim 20, Mangarano fails to teach:
The method of claim 19, wherein controlling the relationship between the delayed clock signal and the clock signal applied to the input of the digital-to- analog converter includes: comparing the clock signal and a representation of the delayed clock signal; and generating, based on the comparison, a phase detector output signal representing an update to the adjustment signal applied to a timing adjustment circuit.
Schreier teaches:
(Thus, when provided with the same clock signals CKD and CKA, replica DAC 24aa and replica ADC 20aa should provide signals whose alignment is similar to that of DAC 24a and ADC 20a, namely, signals CKF and CKS. These signals are submitted to a phase comparator, for example, phase detector 36 which detects any difference in the timing between the CKF and CKS signals). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the application to have applied the teaching of Schreier in the continuous time converter of Manganaro for the benefit to accurately adjust and synchronize the timing of the various circuit elements of the converter.
Allowable Subject Matter
Claims 3-9 and 11-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PEGUY JEAN PIERRE whose telephone number is (571) 272-1803. The examiner can normally be reached from 8:00-6:30 PM Monday-Thursday. The examiner’s fax phone number is (571) 273-1803. The Examiner email address is peguy.jeanpierre@uspto.gov. If attempts to reach the Examiner are unsuccessful, the Examiner’s supervisor Dameon E. Levi can be reached at (571) 272-2105.
/PEGUY JEAN PIERRE/Primary Examiner, Art Unit 2845
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