Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3 and 5-20 are rejected under 35 U.S.C. 103 as being unpatentable over Mizyuabu et al. U.S. PGPUB No. 2003/0131269 (cited in IDS dated 9/2/2025) in view of Hunkins et al. U.S. PGPUB No. 2010/0013840.
Per Claim 1, Mizyuabu discloses
an apparatus for display processing (Paragraph 12; System 100 is described in reference to a display data processing portion of a PDA or other information handling system.), comprising:
a memory (Paragraphs 16 and 17, Fig. 1; RAM 160 comprises an instruction buffer 162); and a processor coupled to the memory and, based on information stored in the memory, the processor is configured to (Paragraphs 16, 19, and 20; Power module operates according to instructions from RAM 160.):
determine that an application processor is to transition from a first power mode to a second power mode based on a change in a refresh rate of a display panel (Paragraphs 16, 27, 33, and 40, The power module 300 initiate power modes within system 100 based on a required display setting such as frame rate or refresh rate.); and
switch, based on the determination and during a transmission of a control signal, a source of a clock associated with the external HSYNC signal from being generated via a phased lock loop clock to being generated via a resistor- capacitor oscillator clock (Paragraphs 31 and 34; Upon determining reduced operation mode, an operation clock of the system is switched from a clock generated from the PLL 130 in normal operating mode, to one generated from the oscillator 110 in power conservation mode. Paragraph 13 teaches that oscillator 110 can be embodied as a resistor-capacitor (RC) oscillator. Paragraph 27 teaches that the Display Module 170 generates data and transmits control signals at the set frame rate for control of the display 195, i.e. continuously, based on the selected clock. The selected clock is used to generate all signals generated by the display module 170).
Mizyuabu does not explicitly mention that the control signal is an “external horizontal synchronization (HSYNC) signal”, but teaches the display interface 190 utilizing a transition minimized differential signaling protocol/transceiver (Paragraph 27).
However, Hunkins, of a common assignee and field of endeavor, teaches an interlink module 812 interfacing VPU cards 860/862 with a display module 830 via a TMDS interface (Paragraph 112, Fig. 9). Hunkins further teaches that the TMDS interface supports the transmission of HSync and VSync signals (Paragraphs 112, 126, 156, and 187).
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention for the TMDS protocol/interface of Mizyuabu to support and utilize the HSync and VSync signals, as taught by Hunkins, because TMDS is well-known in the art to support such signals over connectors such as HDMI and DVI (Hunkins; Paragraphs 112, 116, 126, 175 and 187).
Per Claim 2, Mizyuabu discloses the apparatus of claim 1, wherein the clock is configured to generate the external HSYNC signal (Paragraphs 15 and 21; The clock selected at the multiplexers 121/122 is used to generate all of the transmitted signals. Please see the above rejection of claim 1 for Hunkins’ teaching of the HSync signal.).
Per Claim 3, Mizyuabu discloses the apparatus of claim 1, wherein the processor is further configured to: transmit, to a display driver integrated circuit (DDIC), the continuous external HSYNC signal (Display device 195 comprises integrated circuits for driving signals. Please see the above rejection of claim 1 for Hunkins’ teaching of the HSYNC signal.).
Per Claim 5, Mizyuabu discloses the apparatus of claim 1, wherein the switch of the source of the clock is associated with a power mode transition associated with a frame rate variation (Paragraph 27; Frame or refresh rate associated with display data being sent to display device 195 can be reduced to conserve power.).
Per Claim 6, Mizyuabu discloses ethe apparatus of claim 1, wherein the display panel supports variable refresh rates (Paragraph 27; The display device is able to support different refresh rates; i.e. variable refresh rates.).
Per Claim 7, Mizyuabu discloses the apparatus of claim 1, wherein the processor is further configured to: inactivate, based on the switch of the source of the clock from being generated via the PLL clock to being generated via the RC oscillator clock, a set of resources associated with the PLL clock (Paragraphs 22 and 23; “To conserve power, power module 300 can also set the PLL 130 into a power down mode during the power conservation mode”.).
Per Claim 8, Mizyuabu discloses the apparatus of claim 7, wherein the set of resources associated with the PLL clock includes at least one of a power source of the PLL clock, a reference crystal clock associated with the PLL clock, or a circuit for reference current and reference voltage generation associated with the PLL clock (Paragraph 23; “"PLL 130 is powered down by disabling clock signals input into the PLL 130. A switch (not shown) can be provided to disable input of the raw clock signal generated
through oscillator 110 to the PLL 130. Alternatively, PLL 130 can be shut off by
cutting power to the PLL 130.”).
Per Claim 9, Mizyuabu discloses the apparatus of claim 7, wherein the processor is further configured to: determine that the AP is to transition from the second power mode to the first power mode based on a second change in the refresh rate of the display panel; and switch, based on the determination that the AP is to transition from the second power mode to the first power mode and during the transmission of the continuous external HSYNC signal, the source of the clock from being generated via the RC oscillator clock to being generated via the PLL clock (Paragraph 25; “In one embodiment, power module 300 monitors display content. For example, power module 300 monitors received display data, or compares a new set of display data to an old set of display data, to determine if the display content has changed. If the display content has not changed recently, power module 300 initiates a power conservation mode. If the display content has changed, the power module 300 may switch to, or remain in, the normal mode.”; Paragraph 31; upon switching to the normal mode, the source of the clock is reverted to the PLL.).
Per Claim 10, Mizyuabu discloses the apparatus of claim 9, wherein the processor is further configured to: activate, based on the switch of the source of the clock from being generated via the RC oscillator clock to being generated via the PLL oscillator clock, the set of resources associated with the PLL clock (Paragraph 31; Reverting to the PLL clock includes re-enabling the PLL 130.).
Per Claim 11, Mizyuabu discloses the apparatus of claim 1, wherein the continuous external HSYNC signal is associated with a set of emission pulses, and wherein each pulse in the set of emission pulses corresponds to multiple lines of the display panel (Paragraphs 26, 27, 34, 40, and 51; Interface/communications lines are used to transfer all display data, including the HSYNC signals as taught by Hunkins in claim 1.).
Per Claim 12, Mizyuabu discloses the apparatus of claim 1, wherein the PLL clock is associated with a first power consumption and a first clock accuracy, wherein the RC oscillator clock is associated with a second power consumption and a second clock accuracy, wherein the first power consumption is greater than the second power consumption, and wherein the first clock accuracy is greater than the second clock accuracy (Paragraphs 13 and 22; The PLL clock is faster and more stable than the row clock. The raw clock produced by the oscillator is slower and less stable than the PLL clock. Paragraph 23; The mode in which the raw clock only is used is a conservation power mode, i.e. it is associated with lower power consumption than the normal mode which uses the PLL.).
Per Claim 13, Mizyuabu discloses the apparatus of claim 1, wherein the processor is further configured to: receive, from software, an indication of the change in the refresh rate of the display panel, wherein the determination that the AP is to transition from the first power mode to the second power mode is based on the indication (Paragraphs 16, 27, 33, and 40, The power module 300 initiate power modes within system 100 based on a required display setting such as frame rate or refresh rate. Paragraph 42 and Table 1 disclose Registers 310 of power module 300, including a POWER MODE REQUEST register described as “Software transition between power conservation modes if different from current”.).
Per Claim 14, Mizyuabu discloses the apparatus of claim 1, wherein the processor is further configured to: output an indication of the switch of the source of the clock, wherein to output the indication of the switch of the source of the clock, the processor is configured to: transmit the indication of the switch of the source of the clock; or store the indication of the switch of the source of the clock (Paragraph 34; “In one embodiment, the power module sets a PLL indicator to notify other portions of the subsystem that the PLL is disabled.”).
Per Claim 15, Mizyuabu discloses the apparatus of claim 1, wherein the apparatus comprises a wireless communication device comprising at least one of a transceiver or an antenna coupled to the processor (Paragraph 52; “cellular phone”).
Per Claims 16 and 20, please refer to the above rejection of claim 1 as the limitations are substantially similar and the mapping of the references to the limitations is equally applicable. Additionally, with respect to claim 20, Mizyuabu further teaches a computer readable medium embodiment (See claim 38).
Per Claims 17-19, please refer to the above rejection of claims 7, 9, and 10, respectively, as the limitations are substantially similar and the mapping of the references to the limitations is equally applicable.
* * * * * * * *
Claims 1-4, 16, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over WO 2023/108461, hereafter, Zhang, (cited in the IDS dated 9/2/2025), in view of Mizyuabu et al. U.S. PGPUB No. 2003/0131269 (cited in IDS dated 9/2/2025).
Per Claim 1, Zhang discloses:
an apparatus for display processing (Paragraphs 34 and 35, Figure 1; apparatus 100), comprising:
a memory (Paragraph 36, memory 114); and a processor coupled to the memory and, based on information stored in the memory, the processor is configured to (Figures 1 and 8; processor 112/802):
determine that an application processor is to transition from a first power mode to a second power mode based on a change in a refresh rate of a display panel (Paragraphs 72 and 80; The processor controls, for power reduction purposes, the AP 802 to switch from a normal mode into a low power mode by selecting a lower frequency of operation based on display mode, i.e., based on a set frame refresh rate.); and
switch, based on the determination and during a transmission of a control signal, a source of a clock associated with the external HSYNC signal from being generated via a phased lock loop clock to being generated via a resistor- capacitor oscillator clock (Paragraphs 73, 74, and 80; The processor controls the application processor to switch from a frequency of operation of e.g. 1.8 GHz to a lower-frequency of operation of e.g. 150 MHz, by controlling the Switch 808 to switch from the higher-frequency to the lower-frequency Clock Generator/DSI branch. The switching is in response to the aforementioned determination that a low-power mode is to be set based on display mode. That is, switching to the lower-frequency of operation means switching between a clock generated from the higher-frequency clock generator, between 804a and 804b, to the lower clock generated from of the lower-frequency clock generator. Examiner’s note: The selected generated clock is used by the corresponding DSI block 806a/b to generate the video/control signals for transmission from the wire interface 810 to the DDIC 822, signals which are defined by the DSI protocol and which implicitly comprise, in the video mode of the DSI protocol, an HSYNC signal that is continuously provided from the selected Clock Generator/DSI branch via the wire interface 810 to the DDIC 822.).
Zhang does not specifically disclose that clock generators 804a/b represent PLL and RC clocks, as claimed.
However, Mizyuabu similarly teaches switching between different source clocks based on an operating/power mode of a display device (See detailed rejection of claim 1 above) and further teaches the clocks being one of an RC oscillator clock or a PLL clock (Paragraphs 31 and 34; Upon determining reduced operation mode, an operation clock of the system is switched from a clock generated from the PLL 130 in normal operating mode, to one generated from the oscillator 110 in power conservation mode. Paragraph 13 teaches that oscillator 110 can be embodied as a resistor-capacitor (RC) oscillator. Paragraph 27 teaches that the Display Module 170 generates data and transmits control signals at the set frame rate for control of the display 195, i.e. continuously, based on the selected clock. The selected clock is used to generate all signals generated by the display module 170.)
- It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention for the clocks of Zhang to be RC oscillator and PLL clocks as taught by Mizyuabu because each clock offers different features of either power saving via the raw RC clock or faster and more stable clock signals via the PLL (Mizyuabu; Paragraphs 13 and 22; The PLL clock is faster and more stable than the row clock. The raw clock produced by the oscillator is slower and less stable than the PLL clock. Paragraph 23; The mode in which the raw clock only is used is a conservation power mode, i.e. it is associated with lower power consumption than the normal mode which uses the PLL)
Per Claim 2, Zhang discloses the apparatus of claim 1, wherein the clock is configured to generate the external HSYNC signal (The clocks of the clock generators 804 are used to generate all of the transmitted signals to the display driver IC 822.).
Per Claim 3, Zhang discloses the apparatus of claim 1, wherein the processor is further configured to: transmit, to a display driver integrated circuit (DDIC), the continuous external HSYNC signal (Figure 8; display driver IC 822).
Per Claim 4, Zhang discloses the apparatus of claim 3, wherein, to transmit the continuous external HSYNC signal to the DDIC, the processor is configured to: transmit the continuous external HSYNC signal to the DDIC via a display serial interface (DSI) (Paragraphs 31 and 72 and Fig. 8; The selected one DSI-1/DSI-2 communicate via the serial data link 820).
Per Claims 16 and 20, please refer to the above rejection of claim 1 as the limitations are substantially similar and the mapping of the references to the limitations is equally applicable. Additionally, with respect to claim 20, Mizyuabu further teaches a computer readable medium embodiment (See paragraph 87).
Prior Art
- The prior art made of record but not used in the rejection is considered pertinent to the disclosure due to various teachings including refresh rates for display devices, HSYNC/VSYNC signals, and/or power saving for components related to display devices.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN T MISIURA whose telephone number is (571)272-0889 - (Direct Fax: 571-273-0889). The examiner can normally be reached on M-F: 8-4:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached on (571) 272-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Brian T Misiura/
Primary Examiner, Art Unit 2175
Prosecution Insights