DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment/Argument
This office action is in response to the amendment filed on 06/11/2026.
Claims 1-20 are presented for further examination.
Applicant's argument concerning newly added claim limitation is not taught in the cited prior art has been fully considered but moot in view of the new ground(s) of rejection as set forth below. It is noted that Applicant's arguments are directed towards limitations newly added via amendments.
Claim Rejections - 35 USC § 103
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1- 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2008/0034153; hereinafter Lee) in view of Lin et al. (US 2013/0262745; hereinafter Lin) and Kuzmin et al. (US 9400749; hereinafter Kuzmin).
Regarding independent claims 1, 11 and 17, taking claim 1 as exemplary analysis, Lee teaches A computing system comprising:
a host device configured to output a write operation request for a plurality of pieces of data corresponding to a plurality of consecutive logical addresses ([0006], Host PC 10 generates logical sector addresses (LSA) of a 512-byte block of data to be read or written from a mass storage device…Flash memory mapper 12 converts LSA logical addresses from host PC 10 into physical block addresses (PBA) that identify a physical block of data in flash memory 14); and
a storage device including a plurality of memory areas to be operated according to an interleaving scheme ([0040], FIG. 6 highlights address translation with plane interleaving;
[0046]-[0049], FIG. 7 highlights plane interleaving with a sequence of writes. Each 4K-byte physical page has 8 sectors… one flash chip may support 4 planes, or tow flash chips may be used, each supporting 2 planes. The chip-select bits may be used for extended chip interleaving when each flash chip can support all 4 planes …A sequential stream of host data is written across the four planes in plane order),
the storage device configured to, when the write operation request is received from the host device (Fig. 1 & [0006], Host PC 10 generates logical sector addresses (LSA) of a 512-byte block of data to be read or written from a mass storage device),
Lee teaches a sequential stream of host data is written across the four planes in plane order ([0040]-[0042], FIG. 6 highlights address translation with plane interleaving. A logical sector address (LSA) from the host is translated into a physical address for the flash-memory modules; [0042], the physical block index (PBI) identifies a physical block within a chip and a plane. The bits of the PBI and the physical page number are generated by the RAM mapping table from the LBI; [0043], The physical address has interleave bits in the upper bit-positions. The 2 plane-interleave bits are extracted from the middle of the logical sector address and moved to the upper bit-positions in the logical address. The 2 plane interleave bits select one of four planes within the flash-memory modules; [0047], A sequential stream of host data is written across the four planes in plane order. Planes 0, 1, 2, 3 are written, then planes 0, 1, 2, 3 are written again, with further writes continuing to loop through the four planes. The first write may be to one of planes 1, 2, 3 rather than to plane 0;
[0030], RAM mapping table 40 stores LSA to PBA mappings for sectors in flash-memory modules 50. RAM mapping table 40 provides a fast way to determine which PBA in flash-memory modules 50 to access; [0057], FIG. 10 shows a RAM mapping table for a plane-interleaved flash system. RAM mapping table 40 converts a logical sector address (LSA) from a host into a physical address for the flash-memory modules),
Lee does not expressly teach the write order is determined based on a specific interleaving read command reordering sequence to be performed later, nor does it expressly state that issuing explicit data transmission requests to the host to control transmission order.
Kuzmin teaches a storage device controller that determines an optimized write order/placement for parallel/interleaved media and provides explicit data transmission requests (or metadata directing order) to the host so that data is received in the order needed for efficient physical placement (Abstract, col. 10, ll. 20–45, col. 11, ll. 10–40, col. 12, ll. 1–30;
col. 35, ll. 30-56, C. Shared Responsibility for Physical Address Management … for the memory controller to assign physical addresses for new data writes and then report these addresses back to the host; this is to say, in such an implementation, the host might not have architectural features required to assign physical addresses on its end so as to account for in-flight IO operations and to ensure maximum attainable device bandwidth utilization…provide physical addressing assigned by the memory controller back to the host, in order that the host can associate physical addressing with file-level and other logical addressing structures and appropriately update its L2P translation tables;
col. 36, ll. 5-8, 19-23, That metadata, in particular, can contain a physical-to-logical mapping allowing for the physical block address as returned by the controller to be translated to the logical block address used by the host storage software).
Lin teaches a flash memory controller that reorders read commands received from the host into a second (interleaved) execution order across dies/planes for parallel access, executes the reads in that interleaved order, and then reorders the responses back into the original host logical order for delivery to the host (Lin, [0039]–[0043], [0047]–[0049], Fig. 4C; claims 1, 16–19. Particularly, [0039], read commands are rearranged into a second execution order; [0041], commands directed to different dies/planes are executed in parallel; [0047], responses are reordered into the original host order; Fig. 4C illustrates: Host order - execution order - response order. The controller thus has knowledge of interleaving read execution patterns and the host’s required delivery order). Thus, Lin’s controller has explicit knowledge of, and actively manages, the read execution order of an interleaving read operation.
It would have been obvious to a person of ordinary skill in the art before the effective filing date to determine Lee’s write order / physical placement using Lin's predetermined interleaving read execution sequence as the design constraint for physical placement.
Once Lin teaches the execution order of an interleaving read and Lee teaches selectable physical placement across planes, selecting the placement order in view of the known execution order constitutes optimization of one known variable (physical placement) using known execution order to obtain the predictable result of preserving host-visible logical order while maximizing parallelism.
Lin explicitly teaches two distinct orderings: a host-visible logical order, and an internal interleaving execution order, the controller therefore possesses complete knowledge of both the order in which the host expects the data and the order in which the flash devices will actually execute the reads (Lin, [0039]–[0049], Fig. 4C).
Because Lee already controls the mapping of logical addresses to physical planes through the PSAC and plane-interleaving algorithm, a person of ordinary skill in the art would have recognized that Lee's physical placement algorithm could be selected in view of Lin's known interleaving execution sequence so that the controller can execute interleaved reads while naturally reconstructing the host-visible logical order with reduced response reordering overhead.
This represents the predictable use of known address-mapping techniques (Lee) in combination with known interleaving read command scheduling/reordering techniques (Lin) to improve flash read throughput and reduce controller-side data reordering.
Additionally, one of ordinary skill would have been motivated to incorporate Kuzmin’s host-cooperative data transmission requests into the Lee/Lin system to reduce controller buffering requirements and improve I/O pipelining when implementing the determined write order (Kuzmin, col. 2 ll. 30–50).
The combination of Lee, Lin and Kuzmin would have rendered obvious
provide, to the host device, data transmission requests corresponding to each of the plurality of pieces of data, based on the determined write order, wherein the write order corresponds to a physical placement order of the plurality of pieces of data in the plurality of memory areas, and is determined such that the plurality of pieces of data are sequentially read according to an order of the plurality of consecutive logical addresses during the interleaving read operation (
Lee teaches determining the physical placement order of data among interleaved flash planes through the PSAC and plane-interleaving mapping. Lee, Abstract; Fig. 7; Fig. 8A–8B.
Lin teaches a deterministic interleaving read execution sequence in which commands are reordered for execution across different dies/planes and responses are subsequently restored to the host's logical order. Lin, [0039]–[0043], [0047]–[0049], Fig. 4C.
A person of ordinary skill in the art would have recognized that Lee's physical placement order could be selected using Lin's known interleaving read execution sequence as the governing scheduling constraint so that the interleaving read naturally returns the data in the order of the consecutive logical addresses while maximizing plane-level parallelism.
Kuzmin teaches controller-generated physical-address assignments and associated metadata communicated to the host that direct the host regarding the order in which write data are associated with the assigned physical locations. Under the broadest reasonable interpretation, such controller-generated metadata directing host-side transfer ordering constitutes the claimed data transmission requests.
Accordingly, the combined teachings render obvious determining a write order corresponding to the physical placement order and providing data transmission requests based on that write order).
Additionally, the combination of Lee, Lin and Kuzmin would render obvious sequentially receiving, from the host device, the plurality of pieces of data corresponding to the data transmission requests according to the determined write order; and storing the plurality of pieces of data in the plurality of memory areas according to the determined write order, required in claim 11.
Regarding Claim 2, the combination of Lee, Lin and Kuzmin further teaches wherein the host device is configured to provide the plurality of pieces of data to the storage device according to an order in which the data transmission requests corresponding to each of the plurality of pieces of data are received from the storage device (Kuzmin, col. 11 ll. 35–52 and col. 13 ll. 1–16: host responds to controller metadata/requests by sending data in the order prompted, enabling controller-optimized placement;
With the modification of Kuzmin, wherein the host device responds to controller metadata/requests, the host device then provides pieces of data in the requested/modified order by the memory controller, as shown in Lin [0039], instead of sending them in the order 0, 1, 2, 3…the commands are sent in the order 0, 2, 1, 3, as a result of a reordering of the commands by the memory controller).
Regarding Claim 3, the combination of Lee, Lin and Kuzmin further teaches wherein the storage device is configured to perform the write operation of storing the plurality of pieces of data in the plurality of memory areas according to an order in which the pieces of data are received from the host device (Lee, [0047], sequential stream written across planes in plane order; writes occur in received sequence after interleaving mapping, storing across planes per derived physical order; Lin, [0012], The flash memory may include a first memory plane and a second memory plane, and the command reordering module may modify the order of the commands so that the commands are interleaved between the first memory plane and the second memory plane).
Regarding Claim 20, Claim recites substantially the same limitations as in claims 2 and 3, and is therefore rejected for the same reasons set forth in the analysis of claims 2 and 3.
Regarding Claims 4 and 18, the combination of Lee, Lin and Kuzmin further teaches wherein each of the plurality of memory areas comprises a plurality of logical pages corresponding to one word line (Lee, [0035]–[0040] in related context: planes with pages/word-line groups in restricted-write NAND flash; Kuzmin, col. 8, ll. 13-20).
Regarding Claim 5, the combination of Lee, Lin and Kuzmin further teaches wherein the storage device is configured to store the plurality of pieces of data in the plurality of logical pages included in each of the plurality of memory areas according to the interleaving scheme (Lee, Abstract, [0047]; Lin, Fig. 3).
Regarding Claim 6, the combination of Lee, Lin and Kuzmin further teaches wherein, during the write operation, the storage device is configured to store at least two pieces of data among the plurality of pieces of data in the plurality of logical pages included in one of the plurality of memory areas (Lee, [0047]-[0048]; Lin, Fig. 3).
Regarding Claim 7, the combination of Lee, Lin and Kuzmin further teaches wherein the storage device is configured to determine the write order so that a plurality of pieces of first data are stored in the plurality of logical pages included in a first memory area among the plurality of memory areas, the plurality of pieces of first data corresponding to a plurality of first logical addresses that are not consecutive to each other among the plurality of pieces of data (Lee, [0046]–[0048]: interleaved bit manipulation groups non-consecutive logical addresses (e.g., low-high sequence jumping by 4096) to same plane for grouped writes).
Regarding Claim 8, the combination of Lee, Lin and Kuzmin further teaches wherein the storage device is configured to determine the write order so that a plurality of pieces of second data are stored in the plurality of logical pages included in a second memory area operating consecutively to the first memory area among the plurality of memory areas, the plurality of pieces of second data corresponding to a plurality of second logical addresses consecutive to each of the plurality of first logical addresses, among the plurality of pieces of data (Lee, [0046]-[0048]: sequencing pairs consecutive logical groups to consecutive planes in loop; e.g., planes 0 then 1 receive logically adjacent after interleaving adjustment).
Regarding Claims 9 and 19, the combination of Lee, Lin and Kuzmin further teaches wherein the interleaving read operation is performed to consecutively read the plurality of pieces of data stored in each of the plurality of logical pages from each of the plurality of memory areas, according to the interleaving scheme (Lee, [0046]–[0048]: interleaved layout enables parallel/sequential logical reads via plane access; Lin [0039], instead of sending them in the order 0, 1, 2, 3, …the commands are sent in the order 0, 2, 1, 3, as a result of a reordering of the commands by the memory controller … the memory controller identifies that Cmd 0 and Cmd 2 are directed to planes 0 and 1 respectively, and thus can be executed in parallel. Note that, the order 0, 2, 1, 3 is executed consecutively (i.e. these commands in order 0, 2, 1, 3 are executed first because there is no other command received between them).
Regarding Claim 10, the combination of Lee, Lin and Kuzmin further teaches wherein each of the data transmission requests includes offset information indicating a logical address corresponding to each of the plurality of pieces of data among the plurality of logical addresses, and size information of each of the plurality of pieces of data (Kuzmin, col. 21 ll. 9-50, metadata/requests include address offsets and transfer sizes for targeted host responses).
Regarding Claim 12, the combination of Lee, Lin and Kuzmin further teaches wherein sequentially receiving the plurality of pieces of data comprises sequentially receiving the plurality of pieces of data from the host device according to an order in which the data transmission requests corresponding to each of the plurality of pieces of data are provided by the storage device (Kuzmin, col. 11 ll. 35–52 and col. 13 ll. 1–16: host responds to controller metadata/requests by sending data in the order prompted, enabling controller-optimized placement;
With the modification of Kuzmin, wherein the host device responds to controller metadata/requests, the host device then provides pieces of data in the requested/ modified order by the memory controller, as shown in Lin [0039], instead of sending them in the order 0, 1, 2, 3…the commands are sent in the order 0, 2, 1, 3, as a result of a reordering of the commands by the memory controller … the memory controller identifies that Cmd 0 and Cmd 2 are directed to planes 0 and 1 respectively, and thus can be executed in parallel).
Regarding Claim 13, the combination of Lee, Lin and Kuzmin further teaches wherein determining the write order comprises: determining the write order so that data corresponding to a first logical address and data corresponding to a second logical address, among the plurality of pieces of data are stored in a plurality of logical pages included in a first memory area among the plurality of memory areas (Lin, Fig. 3, wherein logical address 0 and 1 are stored in plane 0); and
determining the write order so that data corresponding to a third logical address consecutive to the first logical address and data corresponding to a fourth logical address consecutive to the second logical address, among the plurality of pieces of data are stored in a plurality of logical pages included in a second memory area to be operated consecutively to the first memory area among the plurality of memory areas (Lin, Fig. 3, wherein logical address 2 and 3 are stored in plane 1).
Regarding Claim 14, the combination of Lee, Lin and Kuzmin further teaches wherein the second logical address is consecutive to the third logical address (Lin [0039], instead of sending them in the order 0, 1, 2, 3 {logical address}…the commands are sent in the order 0, 2, 1, 3, as a result of a reordering of the commands by the memory controller … the memory controller identifies that Cmd 0 and Cmd 2 are directed to planes 0 and 1 respectively, and thus can be executed in parallel).
Regarding Claim 15, the combination of Lee, Lin and Kuzmin further teaches receiving, from the host device, a read operation request corresponding to the plurality of logical addresses; reading pieces of data stored in a plurality of logical pages included in each of the plurality of memory areas according to the interleaving scheme (Lin, Fig. 3, wherein logical address 0 and 1 are read from plane 0, logical address 2 and 3 are read from plane 1); and providing the read pieces of data to the host device (Lin, [0040], In many cases it is necessary to return responses to the host in an order that corresponds to the order in which commands were received).
Regarding Claim 16, the combination of Lee, Lin and Kuzmin further teaches wherein reading the pieces of data comprises: reading data corresponding to the first logical address from the first memory area; reading data corresponding to the third logical address from the second memory area; reading data corresponding to the second logical address from the first memory area; and reading data corresponding to the fourth logical address from the second memory area (Lin, Fig. 3, wherein logical address 0 and 1 are read from plane 0, logical address 2 and 3 are read from plane 1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/TRACY C CHAN/ Primary Examiner, Art Unit 2138
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