DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Application
This office action is in response to the Application filed on 02/06/2025.
Claims 1-20 are presented for examination.
Drawings
The drawings submitted on 02/06/2025 are accepted.
Specification
The title of the invention is objected to because the title is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Currently, the title recites a generic “Computing system for storing data and method of operating the same”, but the specification describes Controller-Directed Interleaved Write Scheduling for Sequential Logical Address Readout.
Claim Rejections - 35 USC § 103
In the event a determination of the status of the application as subject to AIA 35 U.S.C. 102, 103, and 112 (or as subject to pre-AIA 35 U.S.C. 102, 103, and 112) is incorrect, any correction of the statutory basis for a rejection will not be considered a new ground of rejection if the prior art relied upon and/or the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1- 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US; hereinafter Lee) in view of Lin et al. (US 2013/0262745; hereinafter Lin), further in view of Kuzmin et al. (US 9400749; hereinafter Kuzmin).
Regarding independent claims 1, 11 and 17, taking claim 1 as exemplary analysis, Lee teaches A computing system comprising:
a host device configured to output a write operation request for a plurality of pieces of data corresponding to a plurality of consecutive logical addresses ([0006], Host PC 10 generates logical sector addresses (LSA) of a 512-byte block of data to be read or written from a mass storage device…Flash memory mapper 12 converts LSA logical addresses from host PC 10 into physical block addresses (PBA) that identify a physical block of data in flash memory 14); and
a storage device including a plurality of memory areas to be operated according to an interleaving scheme (
[0040], FIG. 6 highlights address translation with plane interleaving;
[0046]-[0049], FIG. 7 highlights plane interleaving with a sequence of writes. Each 4K-byte physical page has 8 sectors… one flash chip may support 4 planes, or tow flash chips may be used, each supporting 2 planes. The chip-select bits may be used for extended chip interleaving when each flash chip can support all 4 planes …A sequential stream of host data is written across the four planes in plane order), the storage device configured to,
when the write operation request is received from the host device (Fig. 1 & [0006], Host PC 10 generates logical sector addresses (LSA) of a 512-byte block of data to be read or written from a mass storage device),
Lee teaches a sequential stream of host data is written across the four planes in plane order ([0040]-[0042], FIG. 6 highlights address translation with plane interleaving. A logical sector address (LSA) from the host is translated into a physical address for the flash-memory modules; [0042], the physical block index (PBI) identifies a physical block within a chip and a plane. The bits of the PBI and the physical page number are generated by the RAM mapping table from the LBI; [0043], The physical address has interleave bits in the upper bit-positions. The 2 plane-interleave bits are extracted from the middle of the logical sector address and moved to the upper bit-positions in the logical address. The 2 plane interleave bits select one of four planes within the flash-memory modules; [0047], A sequential stream of host data is written across the four planes in plane order. Planes 0, 1, 2, 3 are written, then planes 0, 1, 2, 3 are written again, with further writes continuing to loop through the four planes. The first write may be to one of planes 1, 2, 3 rather than to plane 0;
[0030], RAM mapping table 40 stores LSA to PBA mappings for sectors in flash-memory modules 50. RAM mapping table 40 provides a fast way to determine which PBA in flash-memory modules 50 to access; [0057], FIG. 10 shows a RAM mapping table for a plane-interleaved flash system. RAM mapping table 40 converts a logical sector address (LSA) from a host into a physical address for the flash-memory modules),
Lee does not expressly teach determine a write order of the plurality of pieces of data. In an analogous art of interleave operation, Lin teaches determine a write order of the plurality of pieces of data (Lin Abstract, a non-volatile memory system includes a memory controller that receives commands from a host and identifies commands that can be executed in parallel. The order in which commands are received is recorded so that responses may be provided to the host in the same order in which the commands were received;
[0008], The commands are reordered so that the two commands are sent to the nonvolatile memory in sequence and are executed in parallel, even where they were not received sequentially from the host;
[0012], The flash memory may include a first memory plane and a second memory plane, and the command reordering module may modify the order of the commands so that the commands are interleaved between the first memory plane and the second memory plane. The flash memory may include a first memory die and a second memory die, and the command reordering module may modify the order of the commands so that the commands are interleaved between the first memory die and the second memory die).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention was made, with the teachings of Lee and Lin before them, to incorporate Lin’s determining reordering execution order of memory commands and sending reordered write command to memory device for the motivation to increase parallelism and optimize execution (Lin, [0008], Then the commands are examined to see if any commands can be executed in parallel, or if execution can otherwise be made faster, by reordering the execution of the commands).
The combination of Lee and Lin further teaches
so that the pieces of data are read from the plurality of memory areas according to a sequential order of the plurality of logical addresses during a read operation (Lin
[0037], FIG. 4A shows a timing diagram for a first way that a memory controller may deal with the four commands, read 0, read 1, read 2, read 3. The four commands may be received together, or separately, from the host;
[0039], instead of sending them in the order 0, 1, 2, 3, sent by the host, the commands are sent in the order 0, 2, 1, 3, as a result of a reordering of the commands by the memory controller. In this case, the memory controller identifies that Cmd 0 and Cmd 2 are directed to planes 0 and 1 respectively, and thus can be executed in parallel. By reordering the commands so that Cmd 2 is sent immediately after Cmd 0 (or by combining commands), the two commands are executed substantially in parallel, i.e. RdSense 0 and RdSense 1 are performed substantially in parallel; [0040], return responses to the host in an order that corresponds to the order in which commands were received. So, for example, in the case above, responses would have to be sent in ascending order, 0, 1, 2, 3 … commands are received from the host may be recorded and referred to before any response is sent to the host), and Lin teaches memory controller determines the preferred write order and provides the reordered requests to memory dies/planes for parallel operation (
[0039], the commands are sent to the nonvolatile memory in a different order to the order in which they were received from the host. Specifically, instead of sending them in the order 0, 1, 2, 3, sent by the host, the commands are sent in the order 0, 2, 1, 3, as a result of a reordering of the commands by the memory controller;
[0036], A host may issue instructions to the memory system to access pages in any order; [0041], The command reordering module 552 may examine the queue of commands to be executed at any time to try to identify which commands are amenable to parallel execution, or interleaving. For example, before a particular command is sent to the nonvolatile memory 554, the command reordering module 552 may look through the queue to see if there is another command in the queue that could be performed in parallel with the particular command. If there is such a command, then it may be moved up in the queue so that it is executed in parallel with the particular command in question), however, Lee and Lin do not disclose memory controller provides the preferred write order to host.
In an analogous art of interleave operation, Kuzmin teaches memory controller providing metadata to host for host to issue targeted requests (col. 35, ll. 30-46, C. Shared Responsibility for Physical Address Management … for the memory controller to assign physical addresses for new data writes and then report these addresses back to the host; this is to say, in such an implementation, the host might not have architectural features required to assign physical addresses on its end so as to account for in-flight IO operations and to ensure maximum attainable device bandwidth utilization…provide physical addressing assigned by the memory controller back to the host, in order that the host can associate physical addressing with file-level and other logical addressing structures and appropriately update its L2P translation tables; col. 36, ll. 5-8, 19-23, That metadata, in particular, can contain a physical-to-logical mapping allowing for the physical block address as returned by the controller to be translated to the logical block address used by the host storage software).
It would have been obvious to one of ordinary skill in the art before the effective filing date to improve Lee and Lin’s storage controller examine the queue of commands to identify which commands are amenable for parallel execution (Lin [0041]) and determine a preferred write order based on plane-interleaved write ordering with Kuzmin's host-cooperative mechanism where the storage controller issues requests to the host with the determined order, so that storage controller directs host to send requests according to the determined write order for the motivation that as this leverages host bandwidth efficiently, reduces controller buffering needs, and improves overall I/O pipelining in interleaved NAND systems (motivation from Kuzmin, col. 14 ll. 30–50: reducing FTL overhead via host involvement; and reduce wait time and buffering described in Lin [0037] host commands are received one-at-a-time, with the host awaiting a response before sending the next command; [0040] data 2 may be buffered), therefore, storage-controller determination of write order for plane/die interleaving to preserve sequential read performance in NAND flash, with host following storage-issued transmission requests for data—a predictable enhancement to reduce overhead and improve parallelism in high-performance SSDs.
Thus, the combination of Lee, Lin and Kuzmin teaches provide, to the host device, data transmission requests corresponding to each of the plurality of pieces of data, based on the determined write order.
Additionally, the combination of Lee, Lin and Kuzmin further teaches sequentially receiving, from the host device, the plurality of pieces of data corresponding to the data transmission requests according to the determined write order; and storing the plurality of pieces of data in the plurality of memory areas according to the determined write order, required in claim 11.
Regarding Claim 2, the combination of Lee, Lin and Kuzmin further teaches wherein the host device is configured to provide the plurality of pieces of data to the storage device according to an order in which the data transmission requests corresponding to each of the plurality of pieces of data are received from the storage device (Kuzmin, col. 11 ll. 35–52 and col. 13 ll. 1–16: host responds to controller metadata/requests by sending data in the order prompted, enabling controller-optimized placement;
With the modification of Kuzmin, wherein the host device responds to controller metadata/requests, the host device then provides pieces of data in the requested/modified order by the memory controller, as shown in Lin [0039], instead of sending them in the order 0, 1, 2, 3…the commands are sent in the order 0, 2, 1, 3, as a result of a reordering of the commands by the memory controller).
Regarding Claim 3, the combination of Lee, Lin and Kuzmin further teaches wherein the storage device is configured to perform a write operation of storing the plurality of pieces of data in the plurality of memory areas according to an order in which the pieces of data are received from the host device (Lee [0047]: sequential stream written across planes in plane order; writes occur in received sequence after interleaving mapping, storing across planes per derived physical order; Lin, [0012], The flash memory may include a first memory plane and a second memory plane, and the command reordering module may modify the order of the commands so that the commands are interleaved between the first memory plane and the second memory plane).
Regarding Claim 20, Claim recites substantially the same limitations as in claims 2 and 3, and is therefore rejected for the same reasons set forth in the analysis of claims 2 and 3.
Regarding Claims 4 and 18, the combination of Lee, Lin and Kuzmin further teaches wherein each of the plurality of memory areas comprises a plurality of logical pages corresponding to one word line (Lee, [0035]–[0040] in related context: planes with pages/word-line groups in restricted-write NAND flash; Kuzmin, col. 8, ll. 13-20).
Regarding Claim 5, the combination of Lee, Lin and Kuzmin further teaches wherein the storage device is configured to store the plurality of pieces of data in the plurality of logical pages included in each of the plurality of memory areas according to the interleaving scheme (Lee, Abstract, [0047]; Lin, Fig. 3).
Regarding Claim 6, the combination of Lee, Lin and Kuzmin further teaches wherein, during the write operation, the storage device is configured to store at least two pieces of data among the plurality of pieces of data in the plurality of logical pages included in one of the plurality of memory areas (Lee, [0047]-[0048]; Lin, Fig. 3).
Regarding Claim 7, the combination of Lee, Lin and Kuzmin further teaches wherein the storage device is configured to determine the write order so that a plurality of pieces of first data are stored in the plurality of logical pages included in a first memory area among the plurality of memory areas, the plurality of pieces of first data corresponding to a plurality of first logical addresses that are not consecutive to each other among the plurality of pieces of data (Lee, [0046]–[0048]: interleaved bit manipulation groups non-consecutive logical addresses (e.g., low-high sequence jumping by 4096) to same plane for grouped writes).
Regarding Claim 8, the combination of Lee, Lin and Kuzmin further teaches wherein the storage device is configured to determine the write order so that a plurality of pieces of second data are stored in the plurality of logical pages included in a second memory area operating consecutively to the first memory area among the plurality of memory areas, the plurality of pieces of second data corresponding to a plurality of second logical addresses consecutive to each of the plurality of first logical addresses, among the plurality of pieces of data (Lee, [0046]-[0048]: sequencing pairs consecutive logical groups to consecutive planes in loop; e.g., planes 0 then 1 receive logically adjacent after interleaving adjustment).
Regarding Claims 9 and 19, the combination of Lee, Lin and Kuzmin further teaches wherein the read operation is performed to consecutively read the plurality of pieces of data stored in each of the plurality of logical pages from each of the plurality of memory areas, according to the interleaving scheme (Lee, [0046]–[0048]: interleaved layout enables parallel/sequential logical reads via plane access; Lin [0039], instead of sending them in the order 0, 1, 2, 3, …the commands are sent in the order 0, 2, 1, 3, as a result of a reordering of the commands by the memory controller … the memory controller identifies that Cmd 0 and Cmd 2 are directed to planes 0 and 1 respectively, and thus can be executed in parallel. Note that, the order 0, 2, 1, 3 is executed consecutively (i.e. these commands in order 0, 2, 1, 3 are executed first because there is no other command received between them).
Regarding Claim 10, the combination of Lee, Lin and Kuzmin further teaches wherein each of the data transmission requests includes offset information indicating a logical address corresponding to each of the plurality of pieces of data among the plurality of logical addresses, and size information of each of the plurality of pieces of data (Kuzmin, col. 21 ll. 9-50, metadata/requests include address offsets and transfer sizes for targeted host responses).
Regarding Claim 12, the combination of Lee, Lin and Kuzmin further teaches wherein sequentially receiving the plurality of pieces of data comprises sequentially receiving the plurality of pieces of data from the host device according to an order in which the data transmission requests corresponding to each of the plurality of pieces of data are provided by the storage device (Kuzmin, col. 11 ll. 35–52 and col. 13 ll. 1–16: host responds to controller metadata/requests by sending data in the order prompted, enabling controller-optimized placement;
With the modification of Kuzmin, wherein the host device responds to controller metadata/requests, the host device then provides pieces of data in the requested/ modified order by the memory controller, as shown in Lin [0039], instead of sending them in the order 0, 1, 2, 3…the commands are sent in the order 0, 2, 1, 3, as a result of a reordering of the commands by the memory controller … the memory controller identifies that Cmd 0 and Cmd 2 are directed to planes 0 and 1 respectively, and thus can be executed in parallel).
Regarding Claim 13, the combination of Lee, Lin and Kuzmin further teaches wherein determining the write order comprises: determining the write order so that data corresponding to a first logical address and data corresponding to a second logical address, among the plurality of pieces of data are stored in a plurality of logical pages included in a first memory area among the plurality of memory areas (Lin, Fig. 3, wherein logical address 0 and 1 are stored in plane 0); and
determining the write order so that data corresponding to a third logical address consecutive to the first logical address and data corresponding to a fourth logical address consecutive to the second logical address, among the plurality of pieces of data are stored in a plurality of logical pages included in a second memory area to be operated consecutively to the first memory area among the plurality of memory areas (Lin, Fig. 3, wherein logical address 2 and 3 are stored in plane 1).
Regarding Claim 14, the combination of Lee, Lin and Kuzmin further teaches wherein the second logical address is consecutive to the third logical address (Lin [0039], instead of sending them in the order 0, 1, 2, 3 {logical address}…the commands are sent in the order 0, 2, 1, 3, as a result of a reordering of the commands by the memory controller … the memory controller identifies that Cmd 0 and Cmd 2 are directed to planes 0 and 1 respectively, and thus can be executed in parallel).
Regarding Claim 15, the combination of Lee, Lin and Kuzmin further teaches receiving, from the host device, a read operation request corresponding to the plurality of logical addresses; reading pieces of data stored in a plurality of logical pages included in each of the plurality of memory areas according to the interleaving scheme (Lin, Fig. 3, wherein logical address 0 and 1 are read from plane 0, logical address 2 and 3 are read from plane 1); and providing the read pieces of data to the host device (Lin, [0040], In many cases it is necessary to return responses to the host in an order that corresponds to the order in which commands were received).
Regarding Claim 16, the combination of Lee, Lin and Kuzmin further teaches wherein reading the pieces of data comprises: reading data corresponding to the first logical address from the first memory area; reading data corresponding to the third logical address from the second memory area; reading data corresponding to the second logical address from the first memory area; and reading data corresponding to the fourth logical address from the second memory area (Lin, Fig. 3, wherein logical address 0 and 1 are read from plane 0, logical address 2 and 3 are read from plane 1).
Conclusion
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/TRACY C CHAN/ Primary Examiner, Art Unit 2138