DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in response to amendment filed 7/2/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6, 9-15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Talagala et al. (US 2013/0275656 A1, hereinafter Talagala) in view of Kunimatsu et al. (WO 2011/007599 A1, hereinafter Kunimatsu).
Regarding claim 1, Talagala discloses a data storage device (figure 1A, 102) comprising: a memory device (figure 1A, 110); and a memory controller (figure 1A, 104) configured to extract a key value from a modified logic address ([0062] and [0067], one or more clients 114 are in communication with the non-volatile memory device 102 through the key-value store module 116, wherein key-value store module 116 maintains one or more key-value stores 118 that associate data values with unique keys, and provides the data values to the clients 114 in exchange for the corresponding keys, and the key-value store module 116 may divide a logical address space into a key portion and a data value portion to share a single logical address space between keys and data values), and map, to a physical address of the memory device, an index generated based on the modified logic address and the key value ([0067], using a single logical address space, a single mapping structure, or the like for mapping keys to data values and for mapping logical addresses to physical locations on the non-volatile memory media 110). Talagala differs from the claimed invention in not specifically disclosing that a memory controller configured to generate a modified logic address by modification of a source logic address externally provided, extract a portion of a subsequently modified logic address to generate a key value independent of the modified logic address. However, Kunimatsu teaches a network address conversion unit N34 extracts a value at n bit intervals from the combination of the upper address N4u and the middle address N4m of the network logical address N4 (read as a source logic address external provided), and sets the extracted value as the upper address P4u of the processor logical address Pr4, wherein the upper address P4u of the processor logical address Pr4 having a smaller number of bits than the upper address N4u and the middle address N4m of the network logical address N1 is obtained by this conversion and the upper address P4u of the processor logical address Pr4 is used as a key in conversion from the processor logical address Pr4 to the network logical address N4 (figure 94 and Translation copy, page 82, 3rd paragraph). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Talagala in having a memory controller configured to generate a modified logic address by modification of a source logic address externally provided, extract a portion of a subsequently modified logic address to generate a key value independent of the modified logic address, as per teaching of Kunimatsu, in order to prevent access delay.
Regarding claim 2, Talagala discloses that the memory controller is configured to generate, as the modified logic address, a converted logic address by converting the source logic address at least once ([0224], the key-value mapping module 602 converts or maps a key to a logical address without a key-value index or another key-value specific mapping structure), as well as Kunimatsu (figure 94 and Translation copy, page 82, 3rd paragraph).
Regarding claim 3, Talagala discloses that the memory controller is configured to generate the converted logic address by performing a shift operation on the source logic address ([0225], key-value mapping module 602 may divide a logical address space by separating logical addresses of the logical address space into a key address portion and a value address portion, and allows the key-value store module 116 to efficiently store data values of variable lengths while still using consecutive keys), as well as Kunimatsu (figure 94 and Translation copy, page 82, 3rd paragraph).
Regarding claim 4, Talagala discloses that the memory controller is configured to convert the source logic address at least once to generate a converted logic address, and combine the source logic address with the converted logic address to generate the modified logic address ([0227], the key-value mapping module 602 maps or converts a key into a logical address or key address portion of a logical address, and perform a predefined transform, such as a hash function, on a key to convert the key to a logical address or key address portion of a logical address), as well as Kunimatsu (figure 94 and Translation copy, page 82, 3rd and 4th paragraph).
Regarding claim 5, Talagala discloses that the memory controller is configured to generate the converted logic address by performing a shift operation on the source logic address ([0225], key-value mapping module 602 may divide a logical address space by separating logical addresses of the logical address space into a key address portion and a value address portion, and allows the key-value store module 116 to efficiently store data values of variable lengths while still using consecutive keys).
Regarding claim 6, Talagala discloses that the memory controller is configured to combine, by at least one of an arithmetic summation, a logic summation and a logic multiplication, the source logic address with the converted logic address to generate the modified logic address ([0176], storage bus controller 348 will cause the one or more commands to multiplied to each of the each of the storage I/O buses 210a-n with the logical address of the command mapped to a first physical addresses for storage I/O bus 210a, and mapped to a second physical address for storage I/O bus 210b).
Regarding claim 9, Talagala discloses that the memory controller is configured to generate the index by performing a hash function set based on the modified logic address and the key value ([0227], the key-value mapping module 602 may perform a predefined transform, such as a hash function, on a key to convert the key to a logical address or key address portion of a logical address).
Regarding claim 10, Talagala discloses a method of operating a data storage device (figure 1A, 102) including a memory device (figure 1A, 110) and a memory controller (figure 1A, 104), the method comprising: generating, by the memory controller, a modified logic address based on a source logic address externally provided ([0063], the key-value store module 116 stores data values in a restricted set of logical block addresses of the non-volatile memory device 102, so that the data values are only available to clients 114 through the key-value store module 116); extracting, by the memory controller, a key value based on the modified logic address ([0062] and [0067], one or more clients 114 are in communication with the non-volatile memory device 102 through the key-value store module 116, wherein key-value store module 116 maintains one or more key-value stores 118 that associate data values with unique keys, and provides the data values to the clients 114 in exchange for the corresponding keys, and the key-value store module 116 may divide a logical address space into a key portion and a data value portion to share a single logical address space between keys and data values); generating, by the memory controller, an index based on the modified logic address and the key value ([0066], sparse logical address space allows the non-volatile memory device 102 to use a single logical address space for keys and for the associated data values); and mapping, by the memory controller, the index to a physical address of the memory device ([0067], using a single logical address space, a single mapping structure, or the like for mapping keys to data values and for mapping logical addresses to physical locations on the non-volatile memory media 110).
Regarding claim 11, the limitations of the claim are rejected as the same reasons as set forth in claim 2.
Regarding claim 12, the limitations of the claim are rejected as the same reasons as set forth in claim 3.
Regarding claim 13, the limitations of the claim are rejected as the same reasons as set forth in claim 4.
Regarding claim 14, the limitations of the claim are rejected as the same reasons as set forth in claim 5.
Regarding claim 15, the limitations of the claim are rejected as the same reasons as set forth in claim 6.
Regarding claim 18, the limitations of the claim are rejected as the same reasons as set forth in claim 9.
Claims 7-8, 16-17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Talagala et al. (US 2013/0275656 A1, hereinafter Talagala) in view of in view of Kunimatsu et al. (WO 2011/007599 A1, hereinafter Kunimatsu) as applied in claims above, and further in view of Shen et al. (US 2007/0088919 A1, hereinafter Shen).
Regarding claim 7, the combination of Talagala and Kunimatsu differs from the claimed invention in not specifically teaching that the memory controller is configured to generate the modified logic address when workloads of stride patterns with a uniform difference between adjacent source logic addresses are detected in requests of a same type, which are externally and continuously received. However, Shen teaches an effective mechanism with appropriate architecture support that enables software to specify data access patterns that are to be passed to underlying hardware comprising a load/store unit in the CPU compares the effective addresses specified in the memory access instructions to the contents of the pattern registers to see if there is a match, and the load/store unit copies memory access pattern hints from the pattern register if there is a match ([0043]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Talagala and Kunimatsu in having that the memory controller is configured to generate the modified logic address when workloads of stride patterns with a uniform difference between adjacent source logic addresses are detected in requests of a same type, which are externally and continuously received, as per teaching of Shen in order to enable software to specify data access patterns that are to be passed to underlying hardware.
Regarding claim 8, Shen discloses the memory controller is configured to extract a first key value from the source logic address, and map a first index generated based on the source logic address and the first key value to a physical address of the memory device when the workloads of the stride patterns are not detected (figure 2 and [0043], the load/store unit uses the default memory hints when there is not match) such that the operations will revert to normal load and store operations when the operations will revert to normal load and store operations in order to optimize the system's performance for the specific memory access pattern.
Regarding claim 16, the limitations of the claim are rejected as the same reasons as set forth in claim 7.
Regarding claim 17, the limitations of the claim are rejected as the same reasons as set forth in claim 8.
Regarding claim 20, Talagala discloses a data storage device (figure 1A, 102) comprising: a memory device (figure 1A, 110); and a memory controller (figure 1A, 104) configured to generate a physical address corresponding to a source logic address based on a key value extracted from a modified logic address generated from the source logic address included in a write request in response to the write request externally provided ([0063], the key-value store module 116 stores data values in a restricted set of logical block addresses of the non-volatile memory device 102, so that the data values are only available to clients 114 through the key-value store module 116). The combination of Talagala and Kunimatsu differs from the claimed invention in not specifically teaching that when the memory controller receives a stride patterned access request in which a difference between the source logic addresses included in continuously provided write requests is uniform, the key values extracted from the source logic addresses are identical, and the key values extracted from modified logic addresses generated based on the source logic addresses are different. However, Shen teaches an effective mechanism with appropriate architecture support that enables software to specify data access patterns that are to be passed to underlying hardware comprising a load/store unit in the CPU compares the effective addresses specified in the memory access instructions to the contents of the pattern registers to see if there is a match, and the load/store unit copies memory access pattern hints from the pattern register if there is a match ([0043]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Talagala and Kunimatsu in having that when the memory controller receives a stride patterned access request in which a difference between the source logic addresses included in continuously provided write requests is uniform, the key values extracted from the source logic addresses are identical, and the key values extracted from modified logic addresses generated based on the source logic addresses are different, as per teaching of Shen, in order to enable software to specify data access patterns that are to be passed to underlying hardware.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Talagala et al. (US 2013/0275656 A1, hereinafter Talagala) in view of in view of Kunimatsu et al. (WO 2011/007599 A1, hereinafter Kunimatsu) as applied in claims above, and further in view of Durham et al. (US 2017/0285976 A1, Durham).
Regarding claim 19, Talagala discloses a data storage device comprising: (figure 1A, 102) comprising: a memory device (figure 1A, 110); and a memory controller (figure 1A, 104) configured to control the memory device, wherein the memory controller comprises: a mapping manager configured to generate an index based on a key value and a modified logic address ([0063], the key-value store module 116 stores data values in a restricted set of logical block addresses of the non-volatile memory device 102, so that the data values are only available to clients 114 through the key-value store module 116), and generate mapping information by mapping the index and a physical address of the memory device, the key value being generated by extracting from the modified logic address generated by converting a source logic address externally provided at least once ([0062] and [0067], one or more clients 114 are in communication with the non-volatile memory device 102 through the key-value store module 116, wherein key-value store module 116 maintains one or more key-value stores 118 that associate data values with unique keys, and provides the data values to the clients 114 in exchange for the corresponding keys, and the key-value store module 116 may divide a logical address space into a key portion and a data value portion to share a single logical address space between keys and data values); and a processor configured to control the memory device to program write data into a position of the memory device, corresponding to the mapping information in response to a write request externally provided ([0146], the write data pipeline 106 includes a write buffer 320 that buffers data for efficient write operations, and allows a write operation to send an entire page of data to the non-volatile memory media). The combination of Talagala and Kunimatsu differs from the claimed invention in not specifically teaching that the key value extracted from specified bit digit values of the modified logic address, is generated with a random distribution, and wherein the write data is distributed and stored in the memory device based on the key value with the random distribution. However, Durham teaches a memory controller including an address scrambler to scramble a physical memory address utilized to access the memory such that the scrambler may generate a random number per power-up of a computing platform, which may be XORed with the physical address and causing corresponding unencrypted data to include a random distribution of the plurality of bits ([0035]-[0036]) in order to provide memory integrity. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Talagala and Kunimatsu in having that the key value extracted from specified bit digit values of the modified logic address, is generated with a random distribution, and wherein the write data is distributed and stored in the memory device based on the key value with the random distribution, as per teaching of Durham, in order to provide memory integrity.
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Son et al. (US 2026/0111153 A1) discloses a data storage apparatus includes a memory controller configured to access a memory device based on an address mapping table such that an address conversion circuit configured to generate a first virtual address corresponding to a first logical address of data to be written in a memory device, the first virtual address comprising a pair consisting of a first virtual block address and a first physical page address, store the first virtual address in the logical-virtual address table mapping the first virtual address to the first logical address when a logical address is not allocated to the first virtual address (abstract and [0008]-[0010]).
Yeom et al. (US 2025/0061057 A1) discloses a computing system and an operating method configured to distribute and allocate process data associated with a plurality of processes to a plurality of logic addresses (abstract and figure 5).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHUO H LI whose telephone number is (571)272-4183. The examiner can normally be reached Mon. Tue. and Thurs. 8:00-4:00 PM.
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/ZHUO H LI/Primary Examiner, Art Unit 2133
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