DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shibasaki et al (U.S. 2023/0297239).
Regarding claim 1:
An apparatus comprising: a first memory die comprising first corresponding initialization information; and a memory controller coupled to the first memory die, the memory controller comprising a copy of the first corresponding initialization information, Shibasaki, Fig. 1, a memory controller communicates with a plurality of memory chips via memory interface 27. Fig. 2, memory chip comprises memory cell array 111,which further includes a user area and a read only memory (ROM) fuse area as the memory area. The user area is an area that stores the user data. The ROM fuse area is an area that stores various system data including the chip start-up data (¶0085).
the memory controller configured to: selectively initialize the first memory die using either the first corresponding initialization information from the first memory die or the copied first corresponding initialization information from the memory controller. The memory chip includes a storage region that stores setup data used for setup of the memory chip during power on thereof. The memory controller is configured to determine whether or not the memory controller has the setup data, when determining that the memory controller does not have the setup data, instruct the memory chip to read the setup data from the storage region and perform a first setup operation based on the read setup data, and when determining that the memory controller has the setup data, transmit the setup data to the memory chip and instruct the memory chip to perform a second setup operation based on the setup data received from the memory controller (¶0028, ¶0047-¶0050, ¶0113). Fig. 5, ¶0047-¶0049, ¶0113-115 when the memory chip 11 executes the power-on read operation during the low power consumption mode, the sequencer 105 executes the setup operation by using the chip start-up data received from the memory controller 20. On the other hand, when the memory chip executes the normal power-on read operation, the memory chip executes the setup operation by using the chip start-up data read from the memory cell array 111.
Regarding claim 2:
The apparatus of claim 1, wherein the first memory die comprises a first plurality of non-volatile memory cells comprising the first corresponding initialization information. Fig. 2, memory cell array 111 comprises ROM fuse area.
Regarding claim 3:
The apparatus of claim 1, wherein the first memory die comprises a first block of non-volatile memory cells comprising a block of non-volatile memory cells dedicated to storing the first corresponding initialization information. Fig. 2, the memory cell array 111 includes a user area and a read only memory (ROM) fuse area as the memory area. The user area is an area that stores the user data. The ROM fuse area is an area that stores various system data including the chip start-up data.
Regarding claim 4:
The apparatus of claim 1, wherein the memory controller comprises a storage device that comprises the copied first corresponding initialization information. The RAM 24, according to the present embodiment stores the chip start-up data of each memory chip 11. The chip start-up data may be stored in a memory area other than the RAM 24 (¶0057).
Regarding claim 5:
The apparatus of claim 4, wherein the storage device comprises one or more of fuse circuitry, MRAM, SRAM. DRAM, non-volatile memory and volatile memory. The RAM 24, according to the present embodiment stores the chip start-up data of each memory chip 11. The chip start-up data may be stored in a memory area other than the RAM 24 (¶0057).
Regarding claim 6:
The apparatus of claim 1, wherein: the first memory die further comprises a first interface latch configured to store data from the memory controller; and the memory controller is further configured to selectively transfer the first corresponding initialization information from the first memory die or the copied first corresponding initialization information from the memory controller to the first interface latch. Shibasaki discloses the controller (CPU 22 of the controller) transmits start-up data to XDL latch of the memory chip (¶0197).
Regarding claim 7:
The apparatus of claim 1, wherein the first corresponding initialization information comprises one or more parameter information, trimming information, and bad block/bad column information for the first memory die. Shibasaki, the chip start-up data includes parameter information, defective block information, and defective column information (¶0051).
Regarding claim 8:
The apparatus of claim 1, wherein the first corresponding initialization information is unique to the first memory die. Shibasaki, the chip start-up data includes parameter information, defective block information, and defective column information. These kinds of information is different for each memory chip 11. For that reason, the CPU 22 executes the reading operation of reading the chip start-up data for each memory chip 11. (¶0051).
Regarding claim 9:
The apparatus of claim 1, wherein the first corresponding initialization information is determined when the first memory die is first manufactured and tested. Shibasaki, the chip start-up data includes parameter information, defective block information, and defective column information. These kinds of information is different for each memory chip 11 (¶0051). The defective block information includes information on a block determined to be unusable during a shipping inspection of the memory chip 11 (¶0053).
Regarding claim 10:
The apparatus of claim 1, further comprising: a second memory die comprising second corresponding initialization information, wherein the memory controller is coupled to the second memory die and comprises a copy of the second corresponding initialization information, and is further configured to: selectively initialize the second memory die using either the second corresponding initialization information from the second memory die or the copied second corresponding initialization information from the memory controller. Shibasaki, the chip start-up data includes parameter information, defective block information, and defective column information. These kinds of information is different for each memory chip 11. For that reason, the CPU 22 executes the reading operation of reading the chip start-up data for each memory chip 11. (¶0051). The memory chip includes a storage region that stores setup data used for setup of the memory chip during power on thereof. The memory controller is configured to determine whether or not the memory controller has the setup data, when determining that the memory controller does not have the setup data, instruct the memory chip to read the setup data from the storage region and perform a first setup operation based on the read setup data, and when determining that the memory controller has the setup data, transmit the setup data to the memory chip and instruct the memory chip to perform a second setup operation based on the setup data received from the memory controller (¶0028, ¶0047). Shibasaki also discloses a power-on read operation by plurality of memory chips (¶0156). It is noted that the controller can initialize each memory chip, as suggested by Shibasaki (¶0028, ¶0047, ¶0051), and presented in claim 1 above. Because there is no significant difference between first chip/die and second chip/die, the initialization process is just a repeated steps that are suggested by Shibasaki.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Shibasaki et al (U.S. 2023/0297239), and in view of Hansen et al (U.S. 2022/0059173).
Regarding claim 11:
The apparatus of claim 1, wherein the memory controller is further configured to: selectively initialize the first memory die using the copied first corresponding initialization information from the memory controller; determine that the first memory die correctly initialized. Shibasaki does not teach the claimed limitation above. However, in an analogous art of memory initialization routine, Hansen (abstract), discloses a technique to determine whether an initialization process of a memory die was successful, by comparing data and code for initialization at power on and the inverse of the data and code (¶0054). One of ordinary skill in the art, before the effective filing data of the claimed invention, would have been motivated to incorporate the teaching of Hansen into the apparatus of Shibasaki to obtain the claimed limitations above. The motivation for doing so is to apply a known technique into an apparatus, ready for improvement of Shibasaki, to yield predictable result.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Shibasaki et al (U.S. 2023/0297239), and in view of Sandhu et al (U.S. 2026/0147674).
Regarding claim 12:
The apparatus of claim 1, wherein the memory controller is further configured to: selectively initialize the first memory die using the copied first corresponding initialization information from the memory controller; determine that the first memory die did not correctly initialize; selectively initialize the first memory die using the first corresponding initialization information from the first memory die; and determine that the first memory die correctly initialized. Shibasaki does not teach the claimed limitations above. However, in an analogous art of memory management, Sandhu discloses a technique for recovering a memory die that fails to initialize in response to a power on read command. The initialization parameters for a memory die are stored on the memory die, and a backup copy of the initialization parameters is also stored in a storage location outside the first memory die, such as a memory on a memory controller (¶0033). If the memory die fails to initialize in response to a power on read command, the backup copy of the initialization parameters is retrieved from the storage location, and loaded into a data register on the memory die to attempt to initialize the memory die; a test memory operation (e.g., a read operation) is performed on the memory die to determine if the memory die successfully initialized (¶0034). The storage location outside of the first memory die maybe a second memory die, a memory controller coupled to the first memory die, or some other location outside the first memory die (¶0219). Both of Sandhu and Shibasaki are analogous because they both perform memory die initialization. One of ordinary skill in the art, before the effective filing data of the claimed invention, would have been motivated to incorporate the teaching of Sandhu into the teaching of obtain the claimed limitations above. The motivation for doing so is to apply a known technique into an apparatus, ready for improvement of Shibasaki, to yield predictable result.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sicilliani et al (U.S. 2022/0405182) discloses a memory device comprises a control logic configured to perform, during chip initialization, a first attempt of a chip initialization process to be performed based on a first configuration, wherein the first configuration comprises a first set of control settings for reading a block of a memory array during the first attempt; determining that the first attempt has failed; and in response to determining that the first attempt has failed, causing an automatic chip initialization retry process to be performed, wherein causing the automatic chip initialization retry process to be performed comprises causing a second attempt of the chip initialization process to be performed using a second configuration different from the fist configuration.
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/KHOA D DOAN/Primary Examiner, Art Unit 2133
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