DETAILED ACTION
This Office action is in response to the application filed on 06 February 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4, 9-12, and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hatano (US 2022/0014090).
In re claim 1, Hatano discloses a switching stage of a Switched Mode Power Supply (SMPS) (see Figs. 1, 2, 4, 6), the switching stage comprising:
a switching element comprising a GaN transistor (Fig. 6: 11a) connected in series with a Metal-Oxide-Semiconductor (MOS) Field Effect Transistor (FET) (11b), thereby defining a mid-node (Vs) in between the GaN transistor and the MOSFET;
a controller (12 and 13; see also Fig. 2) arranged for driving a gate terminal of the MOSFET based on an Pulse Width Modulation (PWM) input signal ([0043]);
wherein the controller comprises:
first switch circuitry (Fig. 6: 13a) arranged for providing a low ohmic path between the mid-node and the gate terminal of the MOSFET (switch 13a provides low ohmic path from Vs to supply voltage Vcc, which is used to power controller 12 (Figs. 1, 6); within controller 12, driver 12f (Fig. 2, [0050], [0063]), powered by Vcc, provides a high signal SG to turn on MOSFET 11b—this is understood to teach that the driver 12f applies supply voltage Vcc, including through the low-ohmic path of switch 13a, to control terminal of MOSFET 11b); and
control circuitry (Fig. 2: 12d, 12e) arranged for controlling the switch circuitry based on the PWM input signal ([0048]-[0050]).
In re claim 2, Hatano discloses wherein the switching stage further comprises:
a buffer capacitor (Fig. 6: 52);
a rectifying device (13c) connected in between the mid-node (Vs) and the buffer capacitor, so that the buffer capacitor is charged from the mid-node ([0080]);
a voltage regulator (13a, 13b) connected to the buffer capacitor, and arranged for providing a supply voltage (Vcc);
wherein the controller further comprises:
second switch circuitry (Fig. 2: driver 12f) arranged for providing a low ohmic path between the supply voltage and the gate terminal of the MOSFET of the switching element ([0050]: the driver 12f is understood to function as a switch to supply either of Vcc (high) or ground (low) to the gate signal SG);
wherein the control circuitry is further arranged for controlling the second switch circuitry based on a voltage level of the mid-node and based on the PWM input signal (Fig. 2: latch 12e operates driver/switch 12f, also based on supply voltage Vcc per [0063]).
In re claim 4, Hatano discloses wherein the first switch circuitry (see Fig. 6) comprises:
a first control MOSFET (13a/a1), wherein the first control MOSFET has a drain terminal that is connected to the mid-node (Vs), and a source terminal of the first control MOSFET is connected to the gate terminal of the MOSFET of the switching element (via Vcc->controller 12-> driver 12f (Fig. 2); see [0050], [0063]).
In re claims 9 and 10, Hatano discloses a flyback converter Switched Mode Power Supply (SMPS) (Fig. 1) comprising a switching stage in accordance with claim 1 (as explained above).
In re claims 11 and 12, Hatano discloses a method of operating a switching stage in accordance with claim 1 (as explained above), wherein the method comprises the steps of:
controlling, by the control circuity, the switch circuitry based on the PWM input signal (see PWM control circuit Fig. 2; see [0048]-[0050]).
In re claim 14, Hatano discloses wherein the method further comprises the step of:
controlling, by the control circuity, the second switch circuitry based on the voltage of the mid-node and based on the PWM input signal ([0048]-[0050], [0077]-[0085]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hatano in view of Gandhi et al. (US 2021/0391795; hereinafter “Gandhi”).
In re claim 5, Hatano discloses the invention according to claim 4 as explained above, but does not further disclose wherein the first control MOSFET has a body that is connected to ground.
Whereas Gandhi discloses a MOSFET gate driving circuit (Fig. 4) with dynamic bulk/body terminal biasing including connecting the bulk/body terminal to ground (Fig. 4: bulk/body of MPb connected to ground through MP0) in order to prevent forward biasing of any parasitic diodes within the MOSFET switch ([0057]-[0058]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the switching stage of Hatano by using dynamic bulk/body biasing as taught by Gandhi, including connecting the body of the first control MOSFET to ground in order to prevent forward biasing of any parasitic diodes within the MOSFET switch.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hatano in view of “Semiconductor selection,” chapter 7 in Demystifying Switching Power Supplies by R. A. Mack, Jr. (hereinafter “Mack”).
In re claim 6, Hatano discloses the invention according to claim 2 as explained above, but does not further disclose wherein the second switch circuitry comprises: a second control MOSFET, wherein the second control MOSFET has a source terminal that is connected to the supply voltage, and a drain terminal of the second control MOSFET is connected to the gate terminal of the MOSFET of the switching element.
However, the use of a MOSFET connected in such a configuration for use as a gate driving circuit of a power switching MOSFET was well-known and widely practiced in the art. For instance, Mack discloses a common CMOS gate drive circuit (p. 213: Fig. 7-17, rightmost circuit), useful for providing low impedance and high current drive (bottom p. 212).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the second switch circuitry by using a conventional CMOS gate driver circuit as shown in Mack, such that it would comprise a second control MOSFET, wherein the second control MOSFET has a source terminal that is connected to the supply voltage, and a drain terminal of the second control MOSFET is connected to the gate terminal of the MOSFET of the switching element. The motivation for this modification would have been the low impedance and high current driving ability offered by the CMOS gate driver, as taught by Mack.
Claim(s) 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hatano.
In re claims 16-18, Hatano discloses the invention according to claims 11-13 as explained above, but does not further disclose a computer program product comprising a non-transitory computer readable medium having instructions stored thereon which, when executed by a controller of a Switched Mode Power Supply (SMPS), cause the SMPS to implement the claimed method.
However, the use of digital controllers, such as microprocessors, digital signal processors (DSP), field-programmable gate arrays (FPGA), or the like, to execute control instructions for controlling SMPS power converters was notoriously well known and widely practiced in the art. It was common knowledge that the use of digital processing devices for such purposes enables versatility through the programmability and re-programmability of the control devices to suit any particular application. To implement the method taught in Hatano in such a manner would have been a routine task for the person of ordinary skill in the art.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have used a computer program product comprising a non-transitory computer readable medium having instructions stored thereon which, when executed by a controller of a Switched Mode Power Supply (SMPS), cause the SMPS to implement the method in Hatano, because such use of digital controllers to execute control instructions was a routine and conventional practice in the art, and was known to be useful due to the ease of programming the controller in any desired manner for a given application.
Allowable Subject Matter
Claims 3, 7-8, 13 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 3, the closest prior art in Hatano discloses the invention according to claim 2 as explained above, but does not further disclose wherein the controller further comprises: a first comparator arranged for comparing the voltage at the mid-node with a predefined first reference voltage, wherein the control circuitry is arranged for controlling the second switch circuitry based on the comparison.
Rather, Hatano discloses a comparator (Figs. 4, 6: 13b) that compares the voltage Vcc to a reference, rather than the mid node Vs as claimed. Moreover, because the purpose of Hatano’s circuit is to ensure the Vcc does not fall below a minimum low voltage threshold, any hypothetical modification according to the features of claim 3 would have rendered it unsuitable for its intended purpose.
With respect to claim 7, the closest prior art in Hatano discloses the invention according to claim 2 as explained above, but does not further disclose wherein the control circuitry is further arranged for controlling the first switch circuitry based on the PWM input signal and based on a voltage level at the gate terminal of the MOSFET of the switching element.
Similarly to claim 3 above, if one were to modify the control of the first switch 13a/a1 in Hatano, the circuit would cease to function for its intended purpose of maintaining at least a minimum voltage on the Vcc node.
Claim 8 depends from claim 7 and so would be allowable for the same reasons.
With respect to claim 13, the closest prior art in Hatano discloses the invention according to claim 11 as explained above, but does not further disclose wherein the step of controlling comprises: enabling, by the control circuitry, the switch circuitry so that the switch circuitry provides the low ohmic path between the mid-node and the gate terminal of the MOSFET upon a transition in the PWM input signal.
With respect to claim 15, the closest prior art in Hatano discloses the invention according to claim 14 as explained above, but does not further disclose wherein the controller further comprises a first comparator, wherein the method further comprises the step of: comparing, by the first comparator the voltage at the mid-node with a predefined first reference voltage, and wherein the step of controlling comprises: controlling, by the control circuitry, the second switch circuitry based on the comparison.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2007/0070659 discloses a Cascode Switch Power Supply for controlling a MOSFET in series with a cascode protection transistor.
US 2015/0171750 discloses a POWER CIRCUIT, CONTROL METHOD, POWER SYSTEM, AND PACKAGE STRUCTURE OF POWER CIRCUIT for series connected switching transistors.
US 2017/0222573 discloses a Resonant Decoupled Auxiliary Supply For A Switched-Mode Power Supply Controller including for a depletion mode protection transistor in series with a controlled MOSFET switch (Fig. 10).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRED E FINCH III whose telephone number is (571)270-7883. The examiner can normally be reached Monday-Friday, 8:00 AM - 4:30 PM ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838
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