DETAILED ACTION
This Office action is in response to the application filed on 06 February 2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites “The method of claim 10” however, claim 10 is an apparatus claim. Thus the scope of claim 12 is unclear, though it appears that it should instead be written as dependent on “The method of claim 11”, and it will be interpreted in this manner for examination purposes.
Claim 13 depends from claim 12 and therefore inherits this deficiency.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-8, 11-12, 14-15, 17 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kudo et al. (US 2012/0086416; hereinafter “Kudo”).
In re claims 1, 11 and 17, Kudo discloses an electronic power system (Figs. 1-2) comprising a conversion circuit coupled between a power source (VIN) and a load circuit (LOD), the conversion circuit comprises
a multi-phase voltage regulator (Figs. 1-2) and its corresponding method of operation1 comprising:
an output capacitor (Cld1) coupled to a voltage output (VO1) and charged by an output current (Io being the output current to load, it being understood that at steady-state, the DC current through Cld1 is zero) comprising a plurality of sub-currents (individual output currents of PSIP11-PSIP14) to provide an output voltage (ex. 1.0V) at the voltage output (VO1);
a voltage control circuit (PCTLIC1) configured to:
receive a feedback voltage (Fig. 2: any of the signals VSENp1, DFO1 or FB1 may be considered the feedback voltage) indicating a present level of the output voltage at the voltage output ([0085]: “VSENp1, VSENn1, DFO1 and FB1 are respectively a positive-polarity side output voltage detection signal, a negative-polarity side output voltage detection signal, an output voltage detection signal and a feedback signal at the load LOD on the channel 1”); and
determine a target voltage indicating an expected level of the output voltage based on the feedback voltage and a reference voltage (Fig. 2 and [0054]: error amplifier EA1 generates error or target voltage based on feedback and reference voltage VR1); and
a plurality of sub-current generators each coupled to the voltage output (PSIP11-PSIP14) and configured to:
receive the target voltage from the voltage control circuit (Fig. 2: target voltage EO1 is received, e.g., by PSIP11 at pin P39[1]);
extrapolate the expected level of the output current at the voltage output from the target voltage ([0117]2: “the magnitude of the error amp signal EO1 is proportional to the magnitude of the [output] current value because the peak current control system is used”); and
regulate the respective one of the plurality of sub-currents based on the expected level of the output current such that the respective one of the plurality of sub-currents is substantially identical to each other one of the plurality of sub-currents comprised in the output current (Fig. 2, [0047] and [0067]: the PWM controllers PSIP1x perform peak current mode control by comparing individual sub-currents from sensors ACS[n] to the common target voltage EO1, thus each individual sub-current is regulated to the identical peak value based on the common EO1 signal).
In re claims 2 and 12, Kudo discloses wherein the voltage control circuit is further configured to determine the target voltage as a function of the output current ([0117]: “the magnitude of the error amp signal EO1 is proportional to the magnitude of the [output] current value because the peak current control system is used”).
In re claims 4-5, 14-15 and 19, Kudo discloses an output voltage feedback loop configured to provide the feedback voltage indicating the present level of the output voltage at the voltage output (Fig. 2: feedback loop including Vsenp1, AMP11, R11); and
a plurality of current sensing circuits each configured to generate a respective one of a plurality of sense currents indicating the respective one of the plurality of sub-currents at the voltage output (Fig. 2: current sense circuits ACS[n], RCS[n] for each of PSIP1n);
wherein each of the plurality of sub-current generators (Figs. 1, 2: PSIP11-14) comprises a respective one of a plurality of current regulating circuits coupled to a respective one of the plurality of current sensing circuits (Fig. 2: example PSIP11 current regulating circuit PWM_CTL[1] and current sensing circuit ACS[1], Rcs[1]) and configured to:
extrapolate the expected level of the output current at the voltage output from the target voltage ([0079]: "the level of the error amp signal EO1 is proportional to the consumption current Io of the load LOD");
determine the expected level of the respective one of the plurality of sub-currents (Fig. 2 and [0067]: the target voltage EO1 is divided by resistors R1/R2 according to the number of sub-current generators);
compare the expected level of the respective one of the plurality of sub- currents against the present level of the respective one of the plurality of sub-currents as indicated by the respective one of the plurality of sense currents to determine an adjustment value to the respective one of the plurality of sub-currents (Fig. 2 and [0067]: PWM comparator CMPp[1] compares sensed current to the expected level from the divider resistors R1/R2); and
adjust the respective one of the plurality of sub-currents to the expected level based on the determined adjustment value (Fig. 2 and [0067]: PWM comparator and logic circuit LGC[1] control the transistors QH and QL to adjust the actual current).
In re claim 6, Kudo discloses wherein each of the plurality of current regulating circuits comprises (see Fig. 2: an example current regulating circuit in PSIP11 is shown, with identical circuitries being in additional PSIP12, etc.):
a respective voltage converter configured to generate a respective sub- voltage based on the target voltage (voltage converter including QH, QL generating sub-voltage at node SW[1]); and
a respective power inductor configured to induce the respective one of the plurality of sub-currents based on the respective sub-voltage (L11 induces output sub-current for PSIP11, likewise with inductors L12, etc. for PSIP12, etc.).
In re claim 7, Kudo discloses wherein the respective voltage converter is one of a buck converter, a boost converter, and a buck-boost converter (Fig. 2: voltage converter shown as a buck converter).
In re claim 8, Kudo discloses wherein each of the plurality of current regulating circuits further comprises a respective switching device coupled between the respective voltage converter and the respective power inductor (Fig. 2: switching device QH or QL for PSIP11, likewise switches (not shown) within PSIP12, etc.).
Claim(s) 3, 9-10, 13, 16, 18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kudo, as evidenced by “Paralleling Power ...” by L. Balogh (hereinafter “Balogh”)3.
In re claims 3, 13 and 18, Kudo discloses wherein the target voltage is expressed as: VTGT = Vo - RLL * IOUT, wherein:
VTGT represents the target voltage;
Vo represents the output voltage when the output current is zero;
RLL represents a load line of the multi-phase voltage regulator; and
IOUT represents the expected level of the output current.
That is, Kudo describes the droop control at [0117]-[0119]. Specifically, the droop control causes the error/target voltage EO1 to be proportional to the load current, and therefore that “as the error amp signal EO1 becomes larger, the value of the output voltage detection signal DFO1 is reduced, is performed, this droop function can be implemented” ([0117]). Further, “a voltage drop across the resistor R11 increases ... as the output current increases” and “as a result, the voltage value of the output voltage detection signal DFO1 is reduced (i.e., the output voltage is reduced). Thus, the droop function can be achieved” (id.).
In addition, “in this droop, the tilt of the inverse proportional characteristic between the output current and voltage is prescribed in advance” and “the output voltage is reduced by "feedback current ΔI1 x resistor R11" according to the output current I1” ([0118]). Finally, it is understood that the droop function has an initial value being a voltage Vo when the output current equals zero, and to this point Kudo teaches “since an offset component actually exists in the relation between the voltage value of the error amp signal EO1 and the output current, the amplifier circuit AM12 bears the elimination of the offset component and like. Consequently, the voltage value of the output current detection signal RLL1 also becomes zero when the output current is zero” ([0119]).
The droop control disclosed in Kudo is conventionally known in the prior art, and is understood, based on the knowledge of the ordinary artisan and the above-cited teachings to implement a droop function represented by a load-line equation of the type recited in the claim. This is evidenced by Balogh, which teaches various control schemes for parallel or multiphase power supplies, including the droop method (p. 6-11, sec. B. The droop method), which is shown to implement the droop equation VO (IO )=VO (0) − RO ⋅ IO (p. 6-12, middle left column), wherein VO (IO ) is the target output voltage (corresponding to VTGT) expressed as a function of output current IO, VO (0) is the output voltage at zero output current, RO is the load line (i.e., output droop impedance, RLL) of the power supply.
Therefore, it is respectfully submitted that the person of ordinary skill in the art would understand the disclosure of Kudo as teaching the droop function in terms of load line as recited in claim 3.
In re claims 9, 16 and 20, Kudo discloses a current determination circuit (Fig. 10 showing further detail of the control circuit: FBBK includes current determination circuit comprising AMP12, AMP13) configured to calculate the output current expressed as: IOUT = (Vo - VOUT-FB)/ RLL, wherein:
IOUT represents the output current calculated by the current determination circuit;
Vo represents a level of the output voltage when the output current is equal to zero;
VOUT-FB represents the feedback voltage indicating the present level of the output voltage at the voltage output; and RLL represents a load line of the multi-phase voltage regulator.
That is, as explained above, the droop control taught by Kudo at [0117]-[0119], wherein the output current is determined as signal RLL1 such that “the voltage value of the output current detection signal RLL1 obtained via the amplifier circuits AMP12 and AMP13, based on it also has a magnitude proportional to the output current. Here, however, the voltage value of the output current detection signal RLL1 is generated after it has been corrected via the amplifier circuit AMP12 of a gain 1 to which the signal COR1 is inputted. That is, since an offset component actually exists in the relation between the voltage value of the error amp signal EO1 and the output current, the amplifier circuit AM12 bears the elimination of the offset component and like. Consequently, the voltage value of the output current detection signal RLL1 also becomes zero when the output current is zero. Subsequently, there is obtained such a characteristic that the voltage value of the output current detection signal RLL1 will increase in proportion to the magnitude of the output current.” ([0119]).
Thus, as understood according to the knowledge of the person of ordinary skill in the art regarding the droop control function as evidenced by Balogh, the droop equation VO (IO )=VO (0) − RO ⋅ IO (p. 6-12, middle left column), rearranged to solve for the output current yields IO=( VO (0)-VO (IO) )/ RO, where VO (0) is the initial output voltage at zero output current (corresponding to the claimed Vo), VO(IO) is the actual output voltage value at actual outpout current Io (corresponding to claimed VOUT-FB), and RO is the load line (i.e., output droop impedance, RLL) of the power supply.
In re claim 10, Kudo discloses wherein the current determination circuit comprises:
a configuration circuit configured to store the level of the output voltage when the output current is equal to zero and the load line of the multi-phase voltage regulator ([0118]: “in this droop, the tilt of the inverse proportional characteristic between the output current and voltage is prescribed in advance”); and
a processing circuit configured to calculate the output current based on the level of the output voltage when the output current is equal to zero, the load line of the multi-phase voltage regulator, and the feedback voltage indicating the present level of the output voltage at the voltage output (AMP12, AMP13 calculates output current as signal RLL1 based on the factors as explained above; see [0119]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2015/0263614 discloses AVERAGE CURRENT MODE CONTROL OF MULTI-PHASE SWITCHING POWER CONVERTERS.
US 2021/0034084 discloses a LOAD LINE CIRCUIT FOR VOLTAGE REGULATORS.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FRED E FINCH III whose telephone number is (571)270-7883. The examiner can normally be reached Monday-Friday, 8:00 AM - 4:30 PM ET.
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/FRED E FINCH III/Primary Examiner, Art Unit 2838
1 The method of claim 11 being the functional operational steps corresponding to the limitations of apparatus claims 1 and 17.
2 While the cited paragraph describes the circuit of Fig. 10 in Kudo, it is noted that Fig. 10 is taught as showing detail from Fig. 5 ([0105]), and that Fig. 5 is itself showing further detail of the embodiment of Fig. 1 ([0081]).
3 Balogh is cited only as evidence to support the understanding by one of ordinary skill in the art of specific teachings in Kudo. Thus Kudo alone still anticipates the claim under rejection. See MPEP 2131.01.
Prosecution Insights