Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 02/06/2025.
Drawings
Figures 1 and 2 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because of the following informalities. Regarding Fig. 6, the Capacitor Energy Balance Control block 604 shows receiving VUMa twice, while paragraph [0049] of the specification describes that block as monitoring the voltages of the upper and lower arm capacitors (VUMa and VLMa). It appears that one VUMa should read as VLMa.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: Regarding paragraph [0003], “significant reduced” appears that it should read as “significantly reduced”, because of grammar.
Regarding paragraphs [0012]-[0015], “FIG. 4a”, “FIG. 4b”, “FIG. 4c” and “FIG. 4d” appear that they should read as “FIG. 4A”, “FIG. 4B”, “FIG. 4C” and “FIG. 4D”, because of inconsistency with the drawings and with paragraph [0034].
Regarding paragraph [0050], “its reference (Vac*)” appears that it should read as “an alternating current (AC) voltage reference (Vac*)”, because Vac* is not a reference of the DC voltage (Vdc).
Regarding paragraph [0053], “the Modulation Scheme block 612 implements” appears that it should read as “The Modulation Scheme block 612 implements”, because of grammar.
Regarding paragraph [0058], “the resulting line-to-neutral voltage (Vab)” appears that it should read as “the resulting line-to-line voltage (Vab)”, because of inconsistency with paragraph [0018]. Appropriate correction is required.
Claim Objections
Claims 1, 2, 3, 5, 6, 7, 11, 12, and 14 are objected to because of the following informalities: Regarding claim 1, in line 2, “a DC side” appears that it should read as “a direct current (DC) side”, because of use of an abbreviation before it is defined;
in lines 6-7, “an AC output terminal” appears that it should read as “an alternating current (AC) output terminal”, because of use of an abbreviation before it is defined;
in line 8, “the full DC voltage” appears that it should read as “the DC voltage”, because of antecedent basis;
in line 9, “the full DC voltage” appears that it should read as “the DC voltage”, because of antecedent basis.
Regarding claim 2, in lines 1-2, “N series-connected submodules” appears that it should read as “the N series-connected submodules”, because of antecedent basis;
in lines 2-3, “N series-connected submodules” appears that it should read as “the N series-connected submodules”, because of antecedent basis;
in line 4, “the full direct current (DC) voltage” appears that it should read as “the DC voltage”, because of antecedent basis.
Regarding claim 3, in line 1, “comprises” appears that it should read as “comprise”;
in line 3, “the alternating current (AC) output voltage” appears that it should read as “an alternating current (AC) output voltage”, because of antecedent basis;in lines 3-4, “wherein the switches may be implemented as single switches or series-connected switches” appears that it should read as “wherein the switches are be implemented as single switches or series-connected switches”, for positive recitation.
Regarding claim 5, in lines 2-3, “any type of fully controllable switches selected from the group consisting of” appears that it should read as “fully controllable switches selected from the group consisting of”, because of inconsistency between the open-ended phrase and the closed Markush form;
in line 4, “any types of semiconductor materials selected from the group consisting of” appears that it should read as “semiconductor materials selected from the group consisting of”, because of inconsistency between the open-ended phrase and the closed Markush form.
Regarding claim 6, in line 3, “synthesizing alternating current (AC) output voltage” appears that it should read as “synthesizing an alternating current (AC) output voltage”.
Regarding claim 7, in line 3, “when upper switch is conducting” appears that it should read as “when an upper switch of the high-voltage switches is conducting”, because of antecedent basis;
in line 5, “when lower switch is conducting” appears that it should read as “when a lower switch of the high-voltage switches is conducting”, because of antecedent basis.
Regarding claim 11, in line 2, “voltages of the MMC” appears that it should read as “voltages of the MMC arms”, because of antecedent basis;
in lines 2-3, “a compensating current components” appears that it should read as “compensating current components”.
Regarding claim 12, in lines 1-3, “the current references generated by the AC Power Control block and the Capacitor Energy Balance Control block” appears that it should read as “the current references generated by the AC power control block and the compensating current components generated by the Capacitor Energy Balance Control block”, because of antecedent basis.
Regarding claim 14, in line 1, “wherein a modulation scheme block which receives” appears that it should read as “wherein a modulation scheme block receives”;
in line 2, “the Arm Control Current block” appears that it should read as “the Arm Current Control block”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 8 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 8, the recitation “conventional submodule sorting methods” renders the claim indefinite because “conventional” is a relative term and the specification does not provide a standard for ascertaining which sorting methods are conventional (see [0065] of the instant specification). For purposes of examination, “conventional submodule sorting methods” is interpreted as a method that sorts submodule capacitor voltages in order to select submodules for insertion or bypass.
Regarding claim 9, the recitations “when number of submodules is high” and “when number of submodules is limited” render the claim indefinite because “high” and “limited” are relative terms of degree and the specification does not provide a standard for ascertaining the number of submodules at which each recited mode of operation is used (see [0066] of the instant specification). For purposes of examination, “operating submodules in fundamental frequency mode generating staircase waveforms when number of submodules is high or pulse width modulation mode at selected switching frequency when number of submodules is limited” is interpreted as operating the submodules in either the recited fundamental frequency mode or the recited pulse width modulation mode, without regard to the number of submodules.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Vozikis et al. (“An Improved Alternate Arm Converter for HVDC applications,” IECON 2018 – 44th Annual Conference of the IEEE Industrial Electronics Society, IEEE, 2018, hereinafter “Vozikis-IECON”) in view of Liu et al. (US Patent Application Publication US 2023/0026670 A1, hereinafter “Liu”).
Regarding claim 1, Vozikis-IECON discloses (see Fig. 1) a modular multilevel flying capacitor (MMFC) converter (Improved Alternate Arm Converter (IAAC)) comprising: a DC side (the dc-link of the phase leg) having positive and negative terminals (the positive and negative dc rails) with a DC voltage (Vdc); an upper modular multilevel converter (MMC) arm (upper arm comprising Cellj,u1-Cellj,uN and Larm) and a lower MMC arm (lower arm comprising Cellj,l1-Cellj,lN and Larm), each arm comprising N series-connected submodules (Cellj,u1-Cellj,uN and Cellj,l1-Cellj,lN) (see Section II.A of Vozikis-IECON “Each arm of the IAAC consists of series-connected FB cells (FB chain-link) and a Director Switch (DS).”); a flying capacitor (Cfc); and two high-voltage switches (DSj,u and DSj,l) positioned between the MMC arms and an AC output terminal (the node between DSj,u and DSj,l that is connected to Lac), wherein the flying capacitor is connected between junction points of the high-voltage switches (the junction of DSj,u with the upper arm and the junction of DSj,l with the lower arm) (see Section II.A of Vozikis-IECON “A flying capacitor is connected across the director switches of the upper and lower arms of each phase leg.”), and wherein each high-voltage switch is configured to sustain half of the full DC voltage (see Section I of Vozikis-IECON “FC based director switches are rated for a half of the dc-link voltage”; see also equation (13) of Vozikis-IECON, VDS = Vdc/2 + dVfc).
Vozikis-IECON does not disclose wherein the MMC arms are configured to handle half of the full DC voltage.
However, Liu teaches (see Fig. 1A) wherein the MMC arms (p-arm comprising submodule chain link 121 and arm inductor 124; n-arm comprising arm inductor 112 and submodule chain link 115) are configured to handle half of the full DC voltage (see [0038] of Liu “the maximum chain-link voltage across the submodule chain link 121 in P state becomes half of Vdc instead of the full DC bus voltage in typical modular multilevel converters”; see also [0034] of Liu, equation (2), v*na = Vdc - VFC = 0.5Vdc).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the modular multilevel flying capacitor (MMFC) converter of Vozikis-IECON to include wherein the MMC arms are configured to handle half of the full DC voltage, as taught by Liu, because it can help reduce the number of submodules by half for the same DC bus voltage and reduce the total number of capacitors and transistor devices by 25% in comparison to a traditional modular multilevel converter (see [0038] of Liu “the number of submodules is reduced by half for the same DC bus voltage”). Examiner’s Note: Vozikis-IECON states that “the FB chain-link of each arm is utilized to synthesize voltage levels below” Vdc/2, and that the chain-link of each arm is sized to block (2/π)Vdc only “To extend the modulation index linear range to 1.27 p.u. as in the conventional AAC”, such that the voltage that the arms are configured to handle is a design parameter expressly contemplated by Vozikis-IECON itself (see Section II.A of Vozikis-IECON).
Regarding claim 2, Vozikis-IECON discloses (see Fig. 1) wherein the upper MMC arm includes N series-connected submodules (Cellj,u1-Cellj,uN) and an upper arm inductor (Larm of the upper arm), wherein the lower MMC arm includes N series-connected submodules (Cellj,l1-Cellj,lN) and a lower arm inductor (Larm of the lower arm), and wherein the flying capacitor (Cfc) maintains a voltage of approximately half of the full direct current (DC) voltage (Vcfc) (see Section II.A of Vozikis-IECON “The FC in each phase leg is rated for half of the dc-link voltage Vdc.”).
Regarding claim 3, Vozikis-IECON discloses (see Fig. 1) wherein the high-voltage switches comprises an upper switch (SUa) (DSj,u) and a lower switch (SLa) (DSj,l), wherein the switches operate in complementary fashion (see Section II.A of Vozikis-IECON “The DS in each phase leg operate in a complementary manner, i.e. turning on the upper arm DS precludes the lower arm DS from being turned on”) and wherein the switches may be implemented as single switches or series-connected switches (see Section III of Vozikis-IECON “which necessitates the series connection of IGBTs in the DS”).
Vozikis-IECON does not disclose, as best understood, wherein the switches operate at fundamental frequency of the alternating current (AC) output voltage.
However, Liu teaches (see Fig. 1A) wherein the switches (Q1a and Q2a) operate at fundamental frequency of the alternating current (AC) output voltage (Va) (see [0028] of Liu “the switches Q1a and Q2a can include high voltage devices for fundamental switching”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the modular multilevel flying capacitor (MMFC) converter of Vozikis-IECON to include wherein the switches operate at fundamental frequency of the alternating current (AC) output voltage, as taught by Liu, because it can help enable the submodules of the arms, which are relatively low voltage devices in comparison to the high-voltage switches, to have comparatively high speed chopping (see [0028] of Liu “This can enable the half-bridge submodules 118 to have comparatively high speed chopping.”).
Regarding claim 4, Vozikis-IECON discloses (see Fig. 1) wherein the submodules (Cellj,u1-Cellj,uN and Cellj,l1-Cellj,lN) comprise at least one of: half-bridge submodules; full-bridge submodules (FB cells); T-type converter submodules; or full-bridge T-type converter submodules (see Section II.A of Vozikis-IECON “Each arm of the IAAC consists of series-connected FB cells (FB chain-link) and a Director Switch (DS).”).
Regarding claim 15, Vozikis-IECON discloses (see Fig. 1) a power conversion system (the HVDC system in which the IAAC is connected to a stiff dc source and a strong ac network) comprising the MMFC converter of claim 1, wherein the system is configured for at least one of: High Voltage DC (HVDC) power transmission; asynchronous grid connection; power distribution; renewable energy integration; motor drives; energy storage integration; or electric vehicle charging infrastructure (see Section III of Vozikis-IECON “This section assesses the viability of the IAAC when it is connected to a stiff dc source and a strong ac network”; see also Section IV of Vozikis-IECON “the proposed IAAC is promising for HVDC applications”).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Vozikis-IECON in view of Liu, and further in view of Zhang et al. (US Patent Application Publication US 2016/0141949 A1, hereinafter “Zhang”). Regarding claim 5, Vozikis-IECON does not disclose wherein each submodule comprises: semiconductor switches implemented with any type of fully controllable switches selected from the group consisting of IGBTs, IGCTs, MOSFETs, and HEMTs, and wherein the semiconductor switches are made of any types of semiconductor materials selected from the group consisting of Si, SiC, GaN, and ultrawide bandgap semiconductors.
However, Zhang teaches (see Fig. 2) wherein each submodule (switching units S1 through S12) comprises: semiconductor switches implemented with any type of fully controllable switches selected from the group consisting of IGBTs, IGCTs, MOSFETs, and HEMTs (insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and insulated gate commutated thyristors (IGCTs)), and wherein the semiconductor switches are made of any types of semiconductor materials selected from the group consisting of Si, SiC, GaN, and ultrawide bandgap semiconductors (silicon carbide based switches and gallium nitride based switches) (see [0003] of Zhang “MMCs and MEMCs employ large numbers of fully controllable semiconductor switches, such as insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), field effect transistors (FETs), gate turn-off thyristors, insulated gate commutated thyristors (IGCTs), injection enhance gate transistors (IEGTs), silicon carbide based switches, gallium nitride based switches, and gallium arsenide based switches”; see also [0026] of Zhang “Switching units S1 through S12 conduct current in either direction and may be constructed with unidirectional or bidirectional voltage topologies, or a combination of both.”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the modular multilevel flying capacitor (MMFC) converter of Vozikis-IECON to include wherein each submodule comprises: semiconductor switches implemented with any type of fully controllable switches selected from the group consisting of IGBTs, IGCTs, MOSFETs, and HEMTs, and wherein the semiconductor switches are made of any types of semiconductor materials selected from the group consisting of Si, SiC, GaN, and ultrawide bandgap semiconductors, as taught by Zhang, because it can help implement the submodules with fully controllable switching devices that are arranged in stacks to couple the branches to the direct current (DC) side of the converter (see [0003] of Zhang “arranged in stacks that variously couple branches to a direct current (DC) side of the multi-level converter”), and thereby help scale the converter to various power and voltage levels (see [0003] of Zhang “The modular structure facilitates stacking of such known multi-level converters scaling to various power and voltage levels.”).
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Vozikis-IECON. Regarding claim 6, Liu discloses (see Fig. 1A) a method of operating a modular multilevel flying capacitor (MMFC) converter (flying capacitor type hybrid modular multilevel converter 100), comprising: synthesizing alternating current (AC) output voltage (Va) by coordinating switching states between high-voltage switches (Q1a and Q2a) operating at fundamental frequency (see [0028] of Liu “the switches Q1a and Q2a can include high voltage devices for fundamental switching”) and modular multilevel converter (MMC) arms (p-arm comprising submodule chain link 121 and arm inductor 124; n-arm comprising arm inductor 112 and submodule chain link 115) (see [0030] of Liu “A controller device can control Q1a, Q2a, the submodule chain link 121, and the submodule chain link 115 according to Va.”); and implementing submodule voltage balancing control (the submodule voltage balancing included in the low-level arm control) (see [0060] of Liu “the submodule voltage balancing and multilevel-level modulation is included in the low-level arm control”).
Liu does not disclose modular multilevel converter (MMC) arms operating using selective submodule insertion.
However, Vozikis-IECON teaches (see Fig. 1) modular multilevel converter (MMC) arms (upper arm comprising Cellj,u1-Cellj,uN and Larm; lower arm comprising Cellj,l1-Cellj,lN and Larm) operating using selective submodule insertion (each arm voltage vstackj,k is formed from the individual cell voltages vcell-nj,k in accordance with the switching function scell-nj,k of equations (9) and (11)) (see Section II.B of Vozikis-IECON “The cell capacitor current in each individual cell can be described in terms of arm current ij,k and the switching function scell-nj,k {-1,0,1} as stated in (9)”; see also Section III of Vozikis-IECON “the positive/negative voltage insertion of the FB cells”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Liu to include modular multilevel converter (MMC) arms operating using selective submodule insertion, as taught by Vozikis-IECON, because it can help synthesize each arm voltage from the individual cell voltages so that capacitor voltage balancing techniques can be applied to the chain-links (see Section II.A of Vozikis-IECON “Conventional capacitor voltage balancing techniques such as sorting, tolerance band and cell reference modulation methods can be applied to the chain-links.”).
Regarding claim 7, Liu discloses (see Fig. 1A) wherein synthesizing AC output voltage (Va) further comprises: generating output voltage as difference between half direct current (DC) voltage (Vdcp = 0.5Vdc) and upper MMC arm voltage (vpa across submodule chain link 121) when upper switch (Q1a) is conducting (see [0031] of Liu “In P state, where Va>0, Q1a is turned on or closed, and Q2a is turned off or open.”; see also equation (1) of Liu, v*pa = Vdcp - Va - Vmid, and see [0037] of Liu “If the midpoint voltage Vmid is controlled at zero, then Vdcp=Vdcn=0.5Vdc.”); and generating output voltage as sum of negative half DC voltage (-Vdcn = -0.5Vdc) and lower MMC arm voltage (vna across submodule chain link 115) when lower switch (Q2a) is conducting (see [0031] of Liu “N state corresponds to the situation where Va<0, Q2a is turned on or closed, and Q1a is turned off or open.”; see also equation (4) of Liu, v*na = Vdcn + Vmid + Va).
Regarding claim 8, as best understood, Liu does not disclose wherein the MMC arms are controlled using at least one of: staircase modulation; phase-shifted carrier-based modulation; level-shifted carrier-based modulation; or conventional submodule sorting methods.
However, Vozikis-IECON teaches (see Fig. 1) wherein the MMC arms (upper arm comprising Cellj,u1-Cellj,uN and Larm; lower arm comprising Cellj,l1-Cellj,lN and Larm) are controlled using at least one of: staircase modulation; phase-shifted carrier-based modulation; level-shifted carrier-based modulation; or conventional submodule sorting methods (sorting) (see Section II.A of Vozikis-IECON “Conventional capacitor voltage balancing techniques such as sorting, tolerance band and cell reference modulation methods can be applied to the chain-links.”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Liu to include wherein the MMC arms are controlled using at least one of: staircase modulation; phase-shifted carrier-based modulation; level-shifted carrier-based modulation; or conventional submodule sorting methods, as taught by Vozikis-IECON, because it can help keep the cell capacitor voltages of the chain-links balanced during operation (see Section II.A of Vozikis-IECON “Conventional capacitor voltage balancing techniques such as sorting, tolerance band and cell reference modulation methods can be applied to the chain-links.”).
Claims 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Liu in view of Vozikis-IECON, and further in view of Vozikis et al. (“Steady-state performance of state-of-the-art Modular Multilevel and Alternate Arm Converters with DC fault-blocking capability,” International Journal of Electrical Power and Energy Systems, vol. 99, pp. 618-629, 2018, hereinafter “Vozikis-IJEPES”).
Regarding claim 9, as best understood, Liu does not disclose further comprising operating submodules in fundamental frequency mode generating staircase waveforms when number of submodules is high or pulse width modulation mode at selected switching frequency when number of submodules is limited.
However, Vozikis-IJEPES teaches (see Fig. 1(b)) further comprising operating submodules (cells Cellj,u1-Cellj,uN and Cellj,l1-Cellj,lN) in fundamental frequency mode generating staircase waveforms when number of submodules is high or pulse width modulation mode at selected switching frequency when number of submodules is limited (PWM employed for a reduced number of levels, with the cells switching according to the carrier switching frequency) (see Section 4.2 of Vozikis-IJEPES “for a reduced number of levels, PWM is employed, which may lead to even higher switching losses as the cells switch according to the carrier switching frequency”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Liu to include further comprising operating submodules in fundamental frequency mode generating staircase waveforms when number of submodules is high or pulse width modulation mode at selected switching frequency when number of submodules is limited, as taught by Vozikis-IJEPES, because it can help operate the converter with a reduced number of cells per arm, and thereby reduce the power circuit and control complexity and the creepage and clearance requirements (see Section 3.1 of Vozikis-IJEPES “series connection reduces the number of cells, and hence power circuit and control complexity, and creepage and clearance requirements”).
Regarding claim 10, Liu discloses (see Fig. 6) wherein an AC power control block (output control component 603) generates current references for the converter (ia*) (see [0062] of Liu “The output control component 603 can take inputs including Va* and va, to calculate and generate ia*.”).
Liu does not disclose wherein an AC power control block receives active power reference (P*) and reactive power reference (Q*) commands.
However, Vozikis-IJEPES teaches (see Fig. 7) wherein an AC power control block (outer controller of the set-point controller) receives active power reference (P*) and reactive power reference (Q*) commands (see Section 2.6 of Vozikis-IJEPES “Set-point controller determines the references for power, DC voltage, active and reactive current components as shown in Fig. 7.”).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Liu to include wherein an AC power control block receives active power reference (P*) and reactive power reference (Q*) commands, as taught by Vozikis-IJEPES, because it can help determine the references for power, DC voltage, and active and reactive current components using a single set-point controller that can be applied to any converter topology (see Section 2.6 of Vozikis-IJEPES “The same set-point controller may be applied to any converter topology.”).
Regarding claim 11, Liu discloses (see Fig. 6) wherein a Capacitor Energy Balance Control block (capacitor voltage control component 606) monitors voltages of the MMC (vCpa and vCna) and a flying capacitor voltage (VC) (VFC) to generate a compensating current components (I*dcp and I*dcn) to maintain balanced energy distribution among all capacitors in the converter (see [0063] of Liu “The capacitor voltage control component 606 can take inputs including vCpa, vCna, and VFC. The capacitor voltage control component 606 can calculate and generate I*dcp, I*dcn, and V*mid.”).
Regarding claim 12, Liu discloses (see Fig. 6) wherein an Arm Current Control block (current synthesis control component 609 together with controller component 615) processes the current references generated by the AC Power Control block (ia*) and the Capacitor Energy Balance Control block (I*dcp and I*dcn) to produce voltage correction terms (the regulated ipa* and ina* provided to the difference component 618) (see [0064] of Liu “The current synthesis control component 609 can take inputs including ia*, I*dcp, and I*dcn.”; see also [0066] of Liu “The controller component 615 can take inputs including ipa* and ina*. The controller component 615 can regulate these currents, and can provide them, or corresponding parameter values, to the difference component 618.”).
Regarding claim 13, Liu discloses (see Fig. 6) wherein an Arm Voltage Synthesis block (arm voltage calculation component 612) receives a DC voltage (Vdc) and an associated reference (Vac*) (Va*) and determines arm voltage references (vpa* and vna*) (see [0065] of Liu “The arm voltage calculation component 612 can take inputs including V*mid, Vdc, and Va*. The arm voltage calculation component 612 can calculate and generate vpa* and vna*.”).
Regarding claim 14, Liu discloses (see Fig. 6) wherein a modulation scheme block (low-level submodule control component 621) which receives summed outputs from the Arm Control Current block (ipa* and ina* output by the controller component 615) and the Arm Voltage Synthesis block (vpa* and vna* output by the arm voltage calculation component 612) to determine appropriate switching patterns for submodule switches within each MMC arm (control signals for the transistors of the half-bridge submodules 118) (see [0066] of Liu “The difference component 618 can take inputs including vpa*, vna*, ipa*, and ina*. The difference component can difference any two of these values, providing the result to the low-level submodule control component 621.”; see also [0067] of Liu “in order to generate control signals that control the transistors or others switches”). Examiner’s Note: as shown in Fig. 6 of Liu, the difference component 618 is a summation node that receives one subtractive input from the controller component 615 and one additive input from the arm voltage calculation component 612, in the same manner as summation node 610 of Fig. 6 of the instant application.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2016/0141876 A1 discloses an alternate arm converter in which each limb portion includes a director switch connected in series with a chain-link converter between a respective DC terminal and the AC terminal, and in which a controller switches both limb portions into circuit concurrently during an overlap period to transfer energy between the chain-link converters.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JYE-JUNE LEE whose telephone number is (571)270-7726. The examiner can normally be reached on M-F 9 AM - 5 PM.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
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