DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed 02/06/2025 fails to comply with the provisions of 37 CFR 1.97(a) because it lacks the appropriate size fee set forth in 37 CFR 1.17(v). It has been placed in the application file, but the information referred to therein has not been considered as to the merits.
Claim Objections
The claims (12-14) are objected to because they include reference characters which are not enclosed within parentheses.
Reference characters corresponding to elements recited in the detailed description of the drawings and used in conjunction with the recitation of the same element or group of elements in the claims should be enclosed within parentheses so as to avoid confusion with other numbers or characters which may appear in the claims. See MPEP § 608.01(m).
Election/Restrictions
Applicant's election with traverse of Species II -Fig.4a (Claims 1-3, 9-14) in the reply filed on 02/19/2026 is acknowledged. The traversal is on the ground(s) that “Species II (Fig. 4a) and Species III (Fig. 8a) are related in design and reflect alternative circuit implementations directed to the same technical objective. In particular, the timing operation of the embodiments of Figures 4a and 8a is substantially the same. As illustrated in the corresponding timing diagrams of Figures 4b and 8b, the sequences of signal transitions are substantially the same, with the only difference being the polarity of the row signals (ROW_S1 and ROW_S2). Further, both Species II and III are directed to the same technical objective, namely reducing the column-line enable signal (EN signal) transitions”
This is not found persuasive because as depicted and described in the specification Species of Fig.4a is directed to a 7T SRAM-based pixel that includes a first inverter including a first subset of the seven transistors and a second inverter including a second subset of the seven transistor. The Species Species Fig.8a is directed to a 3T1C DRAM based pixel circuit that requires a transistor having a drain electrode connected to high voltage and a source electrode connected to a capacitor, and do not require the particulars of a first inverter and a second inverter as in Fig.4a. Therefore, there is a serious search and/or examination burden for the patentably distinct species, since the different species require different field of search (e.g., searching different classes/subclasses or electronic resources, or employing different search strategies or search queries) and non-prior art issues (i.e. 112) that may be relevant to one species may not be relevant to the other species or grouping(s) of patentably indistinct species.
The requirement is still deemed proper and is therefore made FINAL.
Claims 4-8, 15-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 12/19/2025.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 9-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miyasaka et al. (US 2019/0259132) in view of Li et al. (US 2019/0114987).
As to Claim 1, Miyasaka et al. discloses A system for power consumption reduction in a display comprising: a column driver for driving a set of column lines (fig.5, data line driver 53, para.0090), a row driver for driving a set of row lines (fig.5, scan line driver 52; para.0087); and
a set of 7T static random-access memory (SRAM)-based pixels, one of the set of 7T SRAM-based pixels associated with an intersection of one of the set of column lines and one of the set of row lines (fig.5,9,15; subpixels 58 each including pixel circuit 41; para.0071,0134);
wherein each of the set of 7T SRAM-based pixels (fig.15, subpixels 58) includes a set of seven transistors (fig.9, transistors 32A, 33A, 34A, 35-38), a driver transistor (fig.9,15; drive transistor 31A; para.0150,0231) and a light emitting diode (fig.9,15; light emitting element 20; para.0146-0147,0223) ; and
wherein each of the set of 7T SRAM-based pixels (fig.15, subpixels 58) includes: a first inverter including a first subset of the seven transistors (fig.9,15; inverter 61 including transistors 35,37; para.0134, 0140);
a second inverter including a second subset of the seven transistors, the second subset of transistors being different than the first subset of the seven transistors (fig.9,15; inverter 62, transistors 36,38; para.0134, 0141);
wherein the first and second inverters are connected to form a latch to hold data for the pixel (fig.9,15; para.0134, 0137, 0139).
Miyasaka et al. disclose where the memory circuit 60 is configured to include the two inverters 61 and 62 electrically connected together in a circle to form a so-called static memory to store a digital signal, which is an image signal (0134).
Miyasaki et al. does not expressly disclose where the pixels (58) are 7T static random-access memory (SRAM) based pixels, and where the inverters are connected to form a latch.
Li et al. discloses a pixel circuit comprises SRAM memory cell (401) that includes two inverters connected to form a latch (fig.2B) and where although a 6T SRAM memory is depicted, other SRAM memory cells with different numbers of transistors may be used (para.0033, 0052,0061).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Miyasaka et al. with the teachings of Li et al., the motivation being to improve the emissive display by providing a backplane and modulation system that enables fabrication of multi-color or monochrome LED display systems that operate efficiently and without objectionable image artifacts.
As to Claim 2, Miyasaka et al. in view of Li et al. disclose wherein a gate of the driver transistor is connected to an output of the first inverter (Miyasaka-fig.15; para.0237-gate of drive transistor 31A may be connected to output terminal 26 of inverter 61), and a source of the driver transistor is connected to low voltage (Miyasaka-fig.15, source of drive transistor 31A connected to VSS), and a drain of the driver transistor is connected to a cathode of the light emitting diode (Miyasaka-fig.15, drain of drive transistor 31A connected to cathode 23) and an anode of the light emitting diode is connected to high voltage (fig.15, anode 21 connected to VDD).
As to Claim 3, Miyasaka et al. in view of Li et al. disclose wherein the first inverter comprises two transistors from the set of seven transistors (Miyasaka-fig.15; inverter 61 including transistors 35,37; para.0134, 0140).
As to Claim 9, Miyasaka et al. in view of Li et al. disclose wherein the second inverter comprises two transistors from the set of seven transistors, the two transistors different from the two transistors of the first inverter (Miyasaka-fig.15; inverter 62, transistors 36,38; para.0134, 0141);
As to Claim 10, Miyasaka et al. in view of Li et al. disclose wherein three transistors from the set of seven transistors act as switches, wherein the three transistors acting as switches are different than the transistors in the first and second inverters (Miyasaka-fig.15, transistors 32A, 33A, 34A)
As to Claim 11, Miyasaka et al. in view of Li et al. disclose wherein two of the transistors acting as switches are row switches (Miyasaka-fig.15, transistor 32A connected to Scan 42; transistor 33A connected to XScan 45; para.0155, 0158) and one of the transistors acting as switches is an enable signal switch (Miyasak-fig.15, transistor 34A connected to enable signal Enb).
Allowable Subject Matter
Claims 12-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 12 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “wherein a gate of the row switch, Swr, is connected to row line, ROW_r of the associated row, a source of the row switch Swr is connected to low voltage, and a drain of the row switch Swr is connected to the source of switch Swe” in combination with the other limitations in the claim.
Claim 13 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “wherein a gate of the row switch Sws is connected to row line ROW_s of the associated row, a source of the row switch Sws is connected to low voltage, and a drain of the row switch Sws is connected to the output of second inverter” in combination with the other limitations in the claim.
Claim 14 is allowable over the prior art of record since the cited references taken alone or in combination do not teach or suggest “wherein a gate of the enable signal Swe switch is connected to a column line enable signal, a source of the switch Swe is connected to the drain of row-switch Swr, and a drain of the switch Swe is connected to the output of first inverter” in combination with the other limitations in the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure see PTO-892 form.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DISMERY E. MERCEDES whose telephone number is (571)272-7558. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571-272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DISMERY MERCEDES/ Primary Examiner, Art Unit 2627