DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This Office action is in response to communications dated 2/6/2025.
Claims 1-20 are pending.
Claims 1-20 are rejected.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/9/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 1 recites “…determining that at least one of the start logical address or the end logical address is not aligned with a respective indirection unit (IU); responsive to determining that the at least one of the start logical address or the end logical address is not aligned with the respective indirection unit (IU), storing a corresponding misaligned portion of the data item in a cache line…” (independent claim 1, lines 7-13).
The Examiner is uncertain if “determining that at least one of the start logical address or the end logical address is not aligned with a respective indirection unit (IU)” means any of the following:
a determination is made whether “the start logical address or the end logical address” are not aligned with “the memory device” with use of “a respective indirection unit (IU)”;
a determination is made whether “the start logical address or the end logical address” are not aligned with respect to “a respective indirection unit (IU)”;
using “a respective indirection unit (IU),” a determination is made whether “the start logical address or the end logical address” are not aligned; or
some other, unconsidered interpretation.
Similarly, the Examiner is uncertain if “responsive to determining that the at least one of the start logical address or the end logical address is not aligned with the respective indirection unit (IU), storing a corresponding misaligned portion of the data item in a cache line…” means any of the following:
a determination is made whether “the start logical address or the end logical address” are not aligned with “the memory device” with use of “a respective indirection unit (IU),” and “a corresponding misaligned portion of the data item” is “stor[ed]…in a cache line” based on the determination with use of “a respective indirection unit (IU)”;
a determination is made whether “the start logical address or the end logical address” are not aligned with respect to “a respective indirection unit (IU),” and “a corresponding misaligned portion of the data item” is “stor[ed]…in a cache line” based on the alignment determination performed with respect to “a respective indirection unit (IU)”;
using “a respective indirection unit (IU),” a determination is made whether “the start logical address or the end logical address” are not aligned, and “a corresponding misaligned portion of the data item” is “stor[ed]…in a cache line” based on the determination made by using “a respective indirection unit (IU)”; or
some other, unconsidered interpretation.
For the sake of examination, the Examiner has interpreted “…determining that at least one of the start logical address or the end logical address is not aligned with a respective indirection unit (IU); responsive to determining that the at least one of the start logical address or the end logical address is not aligned with the respective indirection unit (IU), storing a corresponding misaligned portion of the data item in a cache line…” to read “…determining that at least one of the start logical address or the end logical address is not aligned with respect to an alignment of an indirection unit (IU); responsive to determining that the at least one of the start logical address or the end logical address is not aligned with the alignment of the IU, storing, in a cache line, a portion of the data item that is not aligned with the alignment of the IU…”
Dependent claims 2-7, which ultimately depend from independent claim 1, are rejected for carrying the same deficiencies.
Claims 8-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 8 recites “…determining that at least one of the start logical address or the end logical address is not aligned with a respective indirection unit (IU); responsive to determining that the at least one of the start logical address or the end logical address is not aligned with the respective indirection unit (IU), storing a corresponding misaligned portion of the data item in a cache line…” (independent claim 8, lines 6-10).
The Examiner is uncertain if “determining that at least one of the start logical address or the end logical address is not aligned with a respective indirection unit (IU)” means any of the following:
a determination is made whether “the start logical address or the end logical address” are not aligned with “the memory device” with use of “a respective indirection unit (IU)”;
a determination is made whether “the start logical address or the end logical address” are not aligned with respect to “a respective indirection unit (IU)”;
using “a respective indirection unit (IU),” a determination is made whether “the start logical address or the end logical address” are not aligned; or
some other, unconsidered interpretation.
Similarly, the Examiner is uncertain if “responsive to determining that the at least one of the start logical address or the end logical address is not aligned with the respective indirection unit (IU), storing a corresponding misaligned portion of the data item in a cache line…” means any of the following:
a determination is made whether “the start logical address or the end logical address” are not aligned with “the memory device” with use of “a respective indirection unit (IU),” and “a corresponding misaligned portion of the data item” is “stor[ed]…in a cache line” based on the determination with use of “a respective indirection unit (IU)”;
a determination is made whether “the start logical address or the end logical address” are not aligned with respect to “a respective indirection unit (IU),” and “a corresponding misaligned portion of the data item” is “stor[ed]…in a cache line” based on the alignment determination performed with respect to “a respective indirection unit (IU)”;
using “a respective indirection unit (IU),” a determination is made whether “the start logical address or the end logical address” are not aligned, and “a corresponding misaligned portion of the data item” is “stor[ed]…in a cache line” based on the determination made by using “a respective indirection unit (IU)”; or
some other, unconsidered interpretation.
For the sake of examination, the Examiner has interpreted “…determining that at least one of the start logical address or the end logical address is not aligned with a respective indirection unit (IU); responsive to determining that the at least one of the start logical address or the end logical address is not aligned with the respective indirection unit (IU), storing a corresponding misaligned portion of the data item in a cache line…” to read “…determining that at least one of the start logical address or the end logical address is not aligned with respect to an alignment of an indirection unit (IU); responsive to determining that the at least one of the start logical address or the end logical address is not aligned with the alignment of the IU, storing, in a cache line, a portion of the data item that is not aligned with the alignment of the IU…”
Dependent claims 9-14, which ultimately depend from independent claim 8, are rejected for carrying the same deficiencies.
Claims 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Independent claim 15 recites “…determining that at least one of the start logical address or the end logical address is not aligned with a respective indirection unit (IU); responsive to determining that the at least one of the start logical address or the end logical address is not aligned with the respective indirection unit (IU), storing a corresponding misaligned portion of the data item in a cache line…” (independent claim 15, lines 8-12).
The Examiner is uncertain if “determining that at least one of the start logical address or the end logical address is not aligned with a respective indirection unit (IU)” means any of the following:
a determination is made whether “the start logical address or the end logical address” are not aligned with “the memory device” with use of “a respective indirection unit (IU)”;
a determination is made whether “the start logical address or the end logical address” are not aligned with respect to “a respective indirection unit (IU)”;
using “a respective indirection unit (IU),” a determination is made whether “the start logical address or the end logical address” are not aligned; or
some other, unconsidered interpretation.
Similarly, the Examiner is uncertain if “responsive to determining that the at least one of the start logical address or the end logical address is not aligned with the respective indirection unit (IU), storing a corresponding misaligned portion of the data item in a cache line…” means any of the following:
a determination is made whether “the start logical address or the end logical address” are not aligned with “the memory device” with use of “a respective indirection unit (IU),” and “a corresponding misaligned portion of the data item” is “stor[ed]…in a cache line” based on the determination with use of “a respective indirection unit (IU)”;
a determination is made whether “the start logical address or the end logical address” are not aligned with respect to “a respective indirection unit (IU),” and “a corresponding misaligned portion of the data item” is “stor[ed]…in a cache line” based on the alignment determination performed with respect to “a respective indirection unit (IU)”;
using “a respective indirection unit (IU),” a determination is made whether “the start logical address or the end logical address” are not aligned, and “a corresponding misaligned portion of the data item” is “stor[ed]…in a cache line” based on the determination made by using “a respective indirection unit (IU)”; or
some other, unconsidered interpretation.
For the sake of examination, the Examiner has interpreted “…determining that at least one of the start logical address or the end logical address is not aligned with a respective indirection unit (IU); responsive to determining that the at least one of the start logical address or the end logical address is not aligned with the respective indirection unit (IU), storing a corresponding misaligned portion of the data item in a cache line…” to read “…determining that at least one of the start logical address or the end logical address is not aligned with respect to an alignment of an indirection unit (IU); responsive to determining that the at least one of the start logical address or the end logical address is not aligned with the alignment of the IU, storing, in a cache line, a portion of the data item that is not aligned with the alignment of the IU…”
Dependent claims 16-20, which ultimately depend from independent claim 15, are rejected for carrying the same deficiencies.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 8-12, and 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by USPGPUB 2020/0117397 (“Li”).
As per claim 1, Li substantially teaches a system (Li, FIG. 1), comprising:
a memory device; a processing device, operatively coupled to the memory device, to perform operations, comprising: (Li, Abstract; FIG. 1, reference numerals 150, 152, 160, and 168; and paragraphs 0018-0022, where the system of Li comprises storage system 150 (i.e., a memory device), which comprises memory 160 and storage controller 152 (i.e., a processing device operatively coupled to the memory) that controls operations of memory 160. Li therefore substantially teaches a memory device; a processing device, operatively coupled to the memory device, to perform operations, comprising);
receiving, from a host system, a memory write request specifying a data item to be stored on the memory device; identifying a start logical address and an end logical address associated with the data item; determining that at least one of the start logical address or the end logical address is not aligned with a respective indirection unit (IU); responsive to determining that the at least one of the start logical address or the end logical address is not aligned with the respective indirection unit (IU), storing a corresponding misaligned portion of the data item in a cache line; and storing an identifier of the respective IU in a metadata item associated with the cache line: (Li, Abstract; FIG. 1, reference numerals 150, 152, 160, and 168; FIG. 3, reference numerals 302 and 304; and paragraphs 0018-0024 and 0030-0044, where the system of Li may receive a write request specifying data to be stored to media 168 of storage system 150. When the write request is received, the write request is divided into an aligned portion and an unaligned portion based on a starting Logical Block Address (LBA) of the write request and a size of the write request, which means that both a starting LBA of the write request and an ending LBA of the write request are determined. The aligned portion may be written directly to storage (e.g., media 168), but the unaligned portion is written to a buffer (i.e., a line of cache) in order to be written to storage (e.g., media 168) at a later time. When the unaligned portion is written to the buffer, a token (i.e., a metadata item associated with the cache line) may be written to an index table in order to indicate that unaligned data associated with given LBAs are stored in the buffer. Li therefore substantially teaches receiving, from a host system, a memory write request specifying a data item to be stored on the memory device; identifying a start logical address and an end logical address associated with the data item; determining that at least one of the start logical address or the end logical address is not aligned with a respective indirection unit (IU); responsive to determining that the at least one of the start logical address or the end logical address is not aligned with the respective indirection unit (IU), storing a corresponding misaligned portion of the data item in a cache line; and storing an identifier of the respective IU in a metadata item associated with the cache line).
As per claim 2, the rejection of claim 1 is incorporated, and Li further substantially teaches:
wherein a size of the respective IU is a multiple of a size of a system page utilized by the host system: (Li, Abstract; and paragraphs 0023 and 0035, where content to be written may be aligned to aligned to a segment of storage (e.g., LBA intervals of 8 bytes, 16, bytes, or any other multiples of 8 bytes) that may be 4 KiB in size. Since 4 KiB is a multiple of 8 bytes, an IU may be of size 4 KiB (i.e., a multiple of a size of a system page utilized by the host system). Li therefore substantially teaches wherein a size of the respective IU is a multiple of a size of a system page utilized by the host system).
As per claim 3, the rejection of claim 1 is incorporated, and Li further substantially teaches:
wherein the memory write request is comprised by a sequence of memory access requests that is associated with a corresponding processing thread running on the host system: (Li, Abstract; and paragraph 0022, where storage controller 152 is used by storage system 150 to control read access and write access of media 168. Transport layer processor 154 of Li may decode or encode communications from or two host system 100 in response to requests from host system 100. The Examiner notes that requests from host system 100 must originate from processing threads executing on host system 100. Li therefore substantially teaches wherein the memory write request is comprised by a sequence of memory access requests that is associated with a corresponding processing thread running on the host system).
As per claim 4, the rejection of claim 1 is incorporated, and Li further substantially teaches:
wherein the memory write request is comprised by a sequence of memory access requests that is associated with a corresponding submission queue: (Li, Abstract; and paragraphs 0021-0022, (Li, Abstract; and paragraph 0022, where storage controller 152 is used by storage system 150 to control read access and write access of media 168. Transport layer processor 154 of Li may decode or encode communications from or two host system 100 via connection 120 in response to requests from host system 100. Connection 120 may be implemented using Non-Volatile Memory express (NVMe). As evidenced by page 79, section “3.3 NVM QUEUE MODELS,” of the attached non-patent literature “NVM Express® Base Specification,” which is not relied upon by the Examiner for any rejection but is merely and only provided as evidence, NVMe by definition uses submission queues to make requests of devices that use NVMe. Write requests received from host system 100 are thus associated with a corresponding submission queue. Li therefore substantially teaches wherein the memory write request is comprised by a sequence of memory access requests that is associated with a corresponding submission queue).
As per claim 5, the rejection of claim 1 is incorporated, and Li further substantially teaches:
wherein the identifier of the respective IU is determined by applying a predefined mathematical transformation to a corresponding logical address represented by one of: the start logical address or the end logical address: (Li, Abstract; and paragraph 0031, where modulo division (i.e., a predefined mathematical transformation) is applied to a beginning LBA in order to determine a starting Physical Block Address (PBA) of an IU )i.e., an identifier associated with the IU. Li therefore substantially teaches wherein the identifier of the respective IU is determined by applying a predefined mathematical transformation to a corresponding logical address represented by one of: the start logical address or the end logical address).
As per claim 8, Li substantially teaches a method (Li, FIG. 3), comprising:
receiving, by a processing device, from a host system, a memory write request specifying a data item to be stored on a memory device managed by the processing device; identifying a start logical address and an end logical address associated with the data item; determining that at least one of the start logical address or the end logical address is not aligned with a respective indirection unit (IU); responsive to determining that the at least one of the start logical address or the end logical address is not aligned with the respective indirection unit (IU), storing a corresponding misaligned portion of the data item in a cache line; and storing an identifier of the respective IU in a metadata item associated with the cache line: (Li, Abstract; FIG. 1, reference numerals 150, 152, 160, and 168; FIG. 3, reference numerals 302 and 304; and paragraphs 0018-0024 and 0030-0044, where the system of Li comprises storage system 150 (i.e., a memory device), which comprises memory 160 and storage controller 152 (i.e., a processing device operatively coupled to the memory) that controls operations of memory 160. The system of Li may receive a write request specifying data to be stored to media 168 of storage system 150. When the write request is received, the write request is divided into an aligned portion and an unaligned portion based on a starting Logical Block Address (LBA) of the write request and a size of the write request, which means that both a starting LBA of the write request and an ending LBA of the write request are determined. The aligned portion may be written directly to storage (e.g., media 168), but the unaligned portion is written to a buffer (i.e., a line of cache) in order to be written to storage (e.g., media 168) at a later time. When the unaligned portion is written to the buffer, a token (i.e., a metadata item associated with the cache line) may be written to an index table in order to indicate that unaligned data associated with given LBAs are stored in the buffer. Li therefore substantially teaches receiving, by a processing device, from a host system, a memory write request specifying a data item to be stored on a memory device managed by the processing device; identifying a start logical address and an end logical address associated with the data item; determining that at least one of the start logical address or the end logical address is not aligned with a respective indirection unit (IU); responsive to determining that the at least one of the start logical address or the end logical address is not aligned with the respective indirection unit (IU), storing a corresponding misaligned portion of the data item in a cache line; and storing an identifier of the respective IU in a metadata item associated with the cache line).
As per claim 9, the rejection of claim 8 is incorporated, and the Examiner notes that the language of dependent claim 9 is substantially similar to the language of dependent claim 2. Dependent claim 9 is therefore rejected using the same references and reasoning, mutatis mutandis, as used in the above rejection of dependent claim 2.
As per claim 10, the rejection of claim 8 is incorporated, and the Examiner notes that the language of dependent claim 10 is substantially similar to the language of dependent claim 3. Dependent claim 10 is therefore rejected using the same references and reasoning, mutatis mutandis, as used in the above rejection of dependent claim 3.
As per claim 11, the rejection of claim 8 is incorporated, and the Examiner notes that the language of dependent claim 11 is substantially similar to the language of dependent claim 4. Dependent claim 11 is therefore rejected using the same references and reasoning, mutatis mutandis, as used in the above rejection of dependent claim 4.
As per claim 12, the rejection of claim 8 is incorporated, and the Examiner notes that the language of dependent claim 12 is substantially similar to the language of dependent claim 5. Dependent claim 12 is therefore rejected using the same references and reasoning, mutatis mutandis, as used in the above rejection of dependent claim 5.
As per claim 15, Li substantially teaches a non-transitory computer-readable storage medium comprising executable instructions that, when executing by a processing device, cause the processing device to perform operations (Li, FIG. 1; FIG. 3; and paragraphs 0072-0073), comprising:
receiving, from a host system, a memory write request specifying a data item to be stored on a memory device managed by the processing device; identifying a start logical address and an end logical address associated with the data item; determining that at least one of the start logical address or the end logical address is not aligned with a respective indirection unit (IU); responsive to determining that the at least one of the start logical address or the end logical address is not aligned with the respective indirection unit (IU), storing a corresponding misaligned portion of the data item in a cache line; and storing an identifier of the respective IU in a metadata item associated with the cache line: (Li, Abstract; FIG. 1, reference numerals 150, 152, 160, and 168; FIG. 3, reference numerals 302 and 304; and paragraphs 0018-0024 and 0030-0044, where the system of Li comprises storage system 150 (i.e., a memory device), which comprises memory 160 and storage controller 152 (i.e., a processing device operatively coupled to the memory) that controls operations of memory 160. The system of Li may receive a write request specifying data to be stored to media 168 of storage system 150. When the write request is received, the write request is divided into an aligned portion and an unaligned portion based on a starting Logical Block Address (LBA) of the write request and a size of the write request, which means that both a starting LBA of the write request and an ending LBA of the write request are determined. The aligned portion may be written directly to storage (e.g., media 168), but the unaligned portion is written to a buffer (i.e., a line of cache) in order to be written to storage (e.g., media 168) at a later time. When the unaligned portion is written to the buffer, a token (i.e., a metadata item associated with the cache line) may be written to an index table in order to indicate that unaligned data associated with given LBAs are stored in the buffer. Li therefore substantially teaches receiving, from a host system, a memory write request specifying a data item to be stored on a memory device managed by the processing device; identifying a start logical address and an end logical address associated with the data item; determining that at least one of the start logical address or the end logical address is not aligned with a respective indirection unit (IU); responsive to determining that the at least one of the start logical address or the end logical address is not aligned with the respective indirection unit (IU), storing a corresponding misaligned portion of the data item in a cache line; and storing an identifier of the respective IU in a metadata item associated with the cache line).
As per claim 16, the rejection of claim 15 is incorporated, and the Examiner notes that the language of dependent claim 16 is substantially similar to the language of dependent claim 2. Dependent claim 16 is therefore rejected using the same references and reasoning, mutatis mutandis, as used in the above rejection of dependent claim 2.
As per claim 17, the rejection of claim 15 is incorporated, and the Examiner notes that the language of dependent claim 17 is substantially similar to the language of dependent claim 3. Dependent claim 18 is therefore rejected using the same references and reasoning, mutatis mutandis, as used in the above rejection of dependent claim 3.
As per claim 18, the rejection of claim 15 is incorporated, and the Examiner notes that the language of dependent claim 18 is substantially similar to the language of dependent claim 4. Dependent claim 18 is therefore rejected using the same references and reasoning, mutatis mutandis, as used in the above rejection of dependent claim 4.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 6-7, 13-14, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over USPGPUB 2020/0117397 (“Li”) in view of USPGPUB 2019/0121730 (“Palmer”).
As per claim 6, the rejection of claim 1 is incorporated, but Li does not appear to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Palmer teaches unaligned data coalescing.
As per claim 6, Palmer particularly teaches wherein the operations further comprise:
identifying, among a set of metadata items, a first metadata item and a second metadata item, wherein each of the first metadata item and the second metadata item stores a same IU identifier; responsive to determining that a combination of a first portion of host data stored by a first cache line associated with the first metadata item and a second portion of host data stored by a second cache line associated with the second metadata item forms an entire IU: storing, on the memory device, the combination of the first portion of the host data and the second portion of host data; and invalidating the first cache line and the second cache line: (Palmer, Abstract; Fig. 2; and paragraphs 0021-0029, where the system of Palmer includes coalescing identification data structure 209 that stores indicators (i.e., metadata items) that associate unaligned portions of data, a logical page to which the unaligned data pertains, and an LBA range for the unaligned data. When multiple entries in the coalescing identification data structure 209 can be combined to fill an entire page or block, the multiple entries are combined and written to storage. Although Palmer does not appear to explicitly teach that the entries to be coalesced share a same IU identifier, it would have been obvious to a person having ordinary skill in the art before the instant application was effectively filed that Ius associated with entries in coalescing identification data structure 209 may be the same or different and would still be combinable because identified entries fill a block. Palmer therefore particularly teaches identifying, among a set of metadata items, a first metadata item and a second metadata item, wherein each of the first metadata item and the second metadata item stores a same IU identifier; responsive to determining that a combination of a first portion of host data stored by a first cache line associated with the first metadata item and a second portion of host data stored by a second cache line associated with the second metadata item forms an entire IU: storing, on the memory device, the combination of the first portion of the host data and the second portion of host data; and invalidating the first cache line and the second cache line).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Palmer and Li before them before the instant application was effectively filed, to modify the invention of Li to include the principles of Palmer of coalescing unaligned data based on metadata associated with the unaligned data.
The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system performance and reliability by implementing techniques for coalescing unaligned data in order to reduce wear and performance reductions associated with read-modify-write (RMW) operations (Palmer, paragraphs 0002 and 0006).
As per claim 7, the rejection of claim 1 is incorporated, but Li does not appear to explicitly teach the other limitations of this claim beyond those taught above; however, in an analogous art, Palmer teaches unaligned data coalescing.
As per claim 7, Palmer particularly teaches wherein the operations further comprise:
identifying, among a set of metadata items, a first metadata item and a second metadata item, wherein each of the first metadata item and the second metadata item stores a same IU identifier; responsive to determining that a combination of a first portion of host data stored by a first cache line associated with the first metadata item and a second portion of host data stored by a second cache line associated with the second metadata item fails to form an entire IU: storing, in the first cache line, the combination of the first portion of the host data and the second portion of host data; and invalidating the second cache line: (Palmer, Abstract; Fig. 2; and paragraphs 0021-0029, where the system of Palmer includes coalescing identification data structure 209 that stores indicators (i.e., metadata items) that associate unaligned portions of data, a logical page to which the unaligned data pertains, and an LBA range for the unaligned data. When multiple entries in the coalescing identification data structure 209 can be combined to fill an entire page or block, the multiple entries are combined and written to storage. Although Palmer does not appear to explicitly teach that the entries to be coalesced share a same IU identifier, it would have been obvious to a person having ordinary skill in the art before the instant application was effectively filed that Ius associated with entries in coalescing identification data structure 209 may be the same or different and would still be combinable because identified entries fill a block. Palmer therefore particularly teaches identifying, among a set of metadata items, a first metadata item and a second metadata item, wherein each of the first metadata item and the second metadata item stores a same IU identifier; responsive to determining that a combination of a first portion of host data stored by a first cache line associated with the first metadata item and a second portion of host data stored by a second cache line associated with the second metadata item fails to form an entire IU: storing, in the first cache line, the combination of the first portion of the host data and the second portion of host data; and invalidating the second cache line).
It would have been obvious to a person having ordinary skill in the art, having the teachings of Palmer and Li before them before the instant application was effectively filed, to modify the invention of Li to include the principles of Palmer of coalescing unaligned data based on metadata associated with the unaligned data.
The modification would have been obvious because a person having ordinary skill in the art would be motivated to increase system performance and reliability by implementing techniques for coalescing unaligned data in order to reduce wear and performance reductions associated with read-modify-write (RMW) operations (Palmer, paragraphs 0002 and 0006).
As per claim 13, the rejection of claim 8 is incorporated, and the Examiner notes that the language of dependent claim 13 is substantially similar to the language of dependent claim 6. Dependent claim 13 is therefore rejected using the same references and reasoning, mutatis mutandis, as used in the above rejection of dependent claim 6.
As per claim 14, the rejection of claim 8 is incorporated, and the Examiner notes that the language of dependent claim 14 is substantially similar to the language of dependent claim 7. Dependent claim 14 is therefore rejected using the same references and reasoning, mutatis mutandis, as used in the above rejection of dependent claim 7.
As per claim 19, the rejection of claim 15 is incorporated, and the Examiner notes that the language of dependent claim 19 is substantially similar to the language of dependent claim 6. Dependent claim 19 is therefore rejected using the same references and reasoning, mutatis mutandis, as used in the above rejection of dependent claim 6.
As per claim 20, the rejection of claim 15 is incorporated, and the Examiner notes that the language of dependent claim 20 is substantially similar to the language of dependent claim 7. Dependent claim 14 is therefore rejected using the same references and reasoning, mutatis mutandis, as used in the above rejection of dependent claim 7.
Conclusion
The following prior art is made of record and is not relied upon for any rejection but is considered pertinent to Applicant's disclosure:
USPGPUB 2008/0301359: teaches consolidation of memory stored to non-volatile memory in order to completely fille a full page or block of storage.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Daniel C. Chappell whose telephone number is (571)272-5003. The examiner can normally be reached 1000-1800, Eastern.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
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Daniel C. Chappell
Primary Examiner
Art Unit 2135
/Daniel C. Chappell/Primary Examiner, Art Unit 2135