DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6, 13-16, 19-20, and 22-24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Saeki et al. (US 2020/0410919).
Regarding claim 1, Saeki discloses a light emitting apparatus comprising: a plurality of light emitting devices (abstract, figs. 1-2, ¶ 2, ¶ 15-18, display elements 6);
a plurality of conversion circuits provided in correspondence with the plurality of light emitting devices, respectively (figs. 1-2, ¶ 19-22, decoders 26);
and a voltage generator configured to generate a plurality of reference voltages (figs. 1-2, ¶ 19-22, grayscale voltage generator 21),
wherein each of the plurality of conversion circuits converts, using the plurality of reference voltages generated by the voltage generator, a digital signal supplied from an outside into an analog signal for driving one corresponding light emitting device of the plurality of light emitting devices (figs. 1-2, ¶ 17-22, decoder outputs voltage based on digital-to-analog conversion of pixel data from host),
wherein at least one reference voltage of the plurality of reference voltages is supplied from the voltage generator to each of the plurality of conversion circuits via a buffer circuit (figs. 1-3, ¶ 19-26, gamma assist circuits 24; see also fig. 4, ¶ 27-39, source follower circuit 34 disclosed),
wherein the plurality of conversion circuits include a first group of conversion circuits to which the at least one reference voltage is supplied via a first buffer circuit, and a second group of conversion circuits to which the at least one reference voltage is supplied via a second buffer circuit (figs. 1-3, ¶ 19-26, groups of decoders 26 with gamma assist circuits 24; see also fig. 4, ¶ 27-39, source follower circuit 34 disclosed),
and wherein the first buffer circuit and the second buffer circuit are connected in series, and an output of the first buffer circuit is input to the second buffer circuit (figs. 1-3, ¶ 19-26, gamma assist circuits 24; see also fig. 4, ¶ 27-39, source follower circuit 34 disclosed).
Regarding claim 2, Saeki discloses wherein the plurality of conversion circuits include not less than two conversion circuits to which the at least one reference voltage is supplied via a common buffer circuit (figs. 1-3, ¶ 19-26, groups of decoders 26 with gamma assist circuits 24).
Regarding claim 3, Saeki discloses wherein the plurality of reference voltages generated by the voltage generator include a first reference voltage and a second reference voltage (figs. 1-2, ¶ 19-22, voltages V1-Vm; see also fig. 6, ¶ 45-46),
and wherein for the first reference voltage, a common buffer circuit is provided for every first number of conversion circuits, and for the second reference voltage, a common buffer circuit is provided for every second number of conversion circuits different from the first number (fig. 6, ¶ 45-46, e.g., relative to grayscale voltage generator, circuits 24A placed after one group of decoders 26, circuits 24B placed after two groups of decoders 26).
Regarding claim 4, Saeki discloses wherein the plurality of conversion circuits include not less than two conversion circuits to which the at least one reference voltage is supplied via different buffer circuits (figs. 1-3, ¶ 19-26, groups of decoders 26 with gamma assist circuits 24).
Regarding claim 6, Saeki discloses wherein an area of the first buffer circuit is larger than an area of the second buffer circuit (fig. 6, ¶ 45-46, e.g., for p≠2, circuit 24A may be larger than circuit 24B).
Regarding claim 13, Saeki discloses wherein the plurality of conversion circuits include the first group of conversion circuits and the second group of conversion circuits, and wherein the voltage generator is provided for each of the first group of conversion circuits and the second group of conversion circuits (figs. 1-3, ¶ 19-26, grayscale voltage generator 21 and groups of decoders 26).
Regarding claim 14, Saeki discloses wherein each of the plurality of conversion circuits includes a holding circuit configured to temporarily hold the at least one reference voltage supplied from the voltage generator (fig. 4, ¶ 27-39, holding node disclosed),
and after the holding circuit holds the at least one reference voltage, converts the digital signal into the analog signal using the at least one reference voltage held in the holding circuit (fig. 4, ¶ 27-39, holding node disclosed; see also figs. 1-2, ¶ 17-22).
Regarding claim 15, Saeki discloses wherein an operation of the buffer circuit is stopped during a period in which the at least one reference voltage is held in the holding circuit (figs. 4-5, ¶ 27-40, grayscale voltage written into holding node during period other than that gamma assist operation period).
Regarding claim 16, Saeki discloses wherein a plurality of buffer circuits provided for one reference voltage of the plurality of reference voltages use the same power supply, and buffer circuits provided for one reference voltage of the plurality of reference voltages and buffer circuits provided for other reference voltages use different power supplies (fig. 6, ¶ 45-46, circuits 24A and 24B; see fig. 4, ¶ 27-39, e.g., power supplies AVDD and AVSS).
Regarding claim 19, this claim is rejected under the same rationale as claims 1-3.
Regarding claim 20, this claim is rejected under the same rationale as claims 1 and 4.
Regarding claim 22, Saeki discloses a display apparatus including a light emitting apparatus defined in claim 1, and an active device connected to the light emitting apparatus (figs. 1-2, ¶ 2, ¶ 15-18, display panel with display driver disclosed).
Regarding claim 23, Saeki discloses wherein the at least one reference voltage is supplied from the voltage generator to the first group of conversion circuits through the first buffer circuit (figs. 1-3, ¶ 19-26, groups of decoders 26 with gamma assist circuits 24; see also fig. 4, ¶ 27-39, source follower circuit 34 disclosed; see also fig. 6, ¶ 45-46),
and wherein the at least one reference voltage is supplied from the voltage generator to the second group of conversion circuits through the first buffer circuit and the second buffer circuit in this order (figs. 1-3, ¶ 19-26, groups of decoders 26 with gamma assist circuits 24; see also fig. 4, ¶ 27-39, source follower circuit 34 disclosed; see also fig. 6, ¶ 45-46).
Regarding claim 24, Saeki discloses wherein an output node of the first buffer circuit is connected to reference-voltage input nodes of the conversion circuits of the first group and to an input node of the second buffer circuit (figs. 1-3, ¶ 19-26, groups of decoders 26 with gamma assist circuits 24; see also fig. 4, ¶ 27-39, source follower circuit 34 disclosed; see also fig. 6, ¶ 45-46),
and wherein an output node of the second buffer circuit is connected to reference-voltage input nodes of the conversion circuits of the second group (figs. 1-3, ¶ 19-26, groups of decoders 26 with gamma assist circuits 24; see also fig. 4, ¶ 27-39, source follower circuit 34 disclosed; see also fig. 6, ¶ 45-46).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 7, 10-12, 18, and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Saeki in view of Lo (US 2023/0316983).
Regarding claim 5, Saeki discloses wherein the first buffer circuit is constituted by a source follower formed by a MOS transistor and a current source (fig. 4, ¶ 27-39, source follower circuit 34 disclosed).
Saeki fails to explicitly disclose the second buffer circuit is constituted by a unity gain buffer formed by a differential amplification circuit.
Lo teaches the second buffer circuit is constituted by a unity gain buffer formed by a differential amplification circuit (figs. 2-4, ¶ 35-43, see also ¶ 47-54, basic and dynamic buffers disclosed; see also figs. 8-11, ¶ 71-78, unity gain op amps disclosed).
Saeki and Lo are both directed to buffer circuits for reference voltage generating circuits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Saeki with the device of Lo since such a modification provides a general or basic buffer (Lo, ¶ 73) for rapidly settling and stabilizing gamma voltages (Lo, ¶ 3, ¶ 8), and voltage difference between source driver circuits may be reduced (Lo, ¶ 43).
Regarding claim 7, Saeki fails to disclose wherein noise of the first buffer circuit is smaller than noise of the second buffer circuit.
Lo teaches wherein noise of the first buffer circuit is smaller than noise of the second buffer circuit (figs. 2-4, ¶ 35-43, see also ¶ 47-54, dynamic buffers may be turned off; see also figs. 8-11, ¶ 71-78).
Saeki and Lo are both directed to buffer circuits for reference voltage generating circuits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Saeki with the device of Lo since such a modification provides a general or basic buffer (Lo, ¶ 73) for rapidly settling and stabilizing gamma voltages (Lo, ¶ 3, ¶ 8), and voltage difference between source driver circuits may be reduced (Lo, ¶ 43).
Regarding claim 10, Saeki fails to disclose wherein the voltage generator generates the plurality of reference voltages by a resistor string connected between two terminals, and wherein a voltage is applied to each of the two terminals via a buffer circuit.
Lo teaches wherein the voltage generator generates the plurality of reference voltages by a resistor string connected between two terminals, and wherein a voltage is applied to each of the two terminals via a buffer circuit (figs. 3-4, ¶ 35-43, e.g., gamma resistor string disclosed, see also ¶ 47-54; see also figs. 14-15).
Saeki and Lo are both directed to buffer circuits for reference voltage generating circuits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Saeki with the device of Lo since such a modification provides a general or basic buffer (Lo, ¶ 73) for rapidly settling and stabilizing gamma voltages (Lo, ¶ 3, ¶ 8), and voltage difference between source driver circuits may be reduced (Lo, ¶ 43).
Regarding claim 11, Saeki discloses wherein the plurality of reference voltages generated by the voltage generator include a first reference voltage and a second reference voltage (figs. 1-2, ¶ 19-22, grayscale voltage generator 21).
Saeki fails to disclose wherein the light emitting apparatus further comprises a second resistor string connected between an output terminal of the first reference voltage and an output terminal of the second reference voltage in the voltage generator, wherein each of the first reference voltage and the second reference voltage is input to the second resistor string via a buffer circuit, and wherein a plurality of voltages generated by the second resistor string are supplied to each of the plurality of conversion circuits.
Lo teaches wherein the light emitting apparatus further comprises a second resistor string connected between an output terminal of the first reference voltage and an output terminal of the second reference voltage in the voltage generator (figs. 3-4, ¶ 35-43, e.g., gamma resistor string disclosed, see also ¶ 47-54; see also figs. 14-15),
wherein each of the first reference voltage and the second reference voltage is input to the second resistor string via a buffer circuit (figs. 3-4, ¶ 35-43, see also ¶ 47-54, basic and dynamic buffers disclosed; see also figs. 14-15),
and wherein a plurality of voltages generated by the second resistor string are supplied to each of the plurality of conversion circuits (figs. 2-4, ¶ 28-31).
Saeki and Lo are both directed to buffer circuits for reference voltage generating circuits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Saeki with the device of Lo since such a modification provides a general or basic buffer (Lo, ¶ 73) for rapidly settling and stabilizing gamma voltages (Lo, ¶ 3, ¶ 8), and voltage difference between source driver circuits may be reduced (Lo, ¶ 43).
Regarding claim 12, Saeki discloses wherein the plurality of conversion circuits include the first group of conversion circuits and the second group of conversion circuits (figs. 1-3, ¶ 19-26, groups of decoders 26 with gamma assist circuits 24).
Lo further teaches wherein the second resistor string is provided for each of the first group of conversion circuits and the second group of conversion circuits (figs. 3-4, ¶ 35-43, e.g., gamma resistor string disclosed, see also ¶ 47-54; see also figs. 14-15).
Regarding claim 18, Saeki discloses a plurality of buffer circuits provided for the plurality of reference voltages, respectively (figs. 1-3, ¶ 19-26, gamma assist circuits 24; see also fig. 4, ¶ 27-39).
Saeki fails to disclose a second detector configured to detect an output offset value between the plurality of buffer circuits, and a controller configured to control the plurality of buffer circuits, wherein each of the plurality of buffer circuits includes an output offset adjustment mechanism, and wherein the controller controls an output of each buffer circuit by the output offset adjustment mechanism, based on a detection result of the second detector, such that the output offset value between the plurality of buffer circuits is corrected.
Lo teaches a second detector configured to detect an output offset value between the plurality of buffer circuits, and a controller configured to control the plurality of buffer circuits, wherein each of the plurality of buffer circuits includes an output offset adjustment mechanism (figs. 1-4, ¶ 24, controller 23; see ¶ 35-43, see also ¶ 47-54, dynamic buffers may be turned off; see also figs. 8-11, 78-82, voltage detecting modules disclosed),
and wherein the controller controls an output of each buffer circuit by the output offset adjustment mechanism, based on a detection result of the second detector, such that the output offset value between the plurality of buffer circuits is corrected (figs. 1-4, ¶ 24, controller 23; see ¶ 35-43, see also ¶ 47-54, dynamic buffers may be turned off; see also figs. 8-11, 78-82, voltage detecting modules disclosed to settle and stabilize gamma voltages).
Saeki and Lo are both directed to buffer circuits for reference voltage generating circuits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Saeki with the device of Lo since such a modification provides a general or basic buffer (Lo, ¶ 73) for rapidly settling and stabilizing gamma voltages (Lo, ¶ 3, ¶ 8), and voltage difference between source driver circuits may be reduced (Lo, ¶ 43).
Regarding claim 25, Saeki discloses wherein the plurality of reference voltages include a first reference voltage and a second reference voltage (figs. 1-2, ¶ 19-22, grayscale voltage generator 21),
and wherein the buffer circuits connected to the second resistor string receive outputs of the buffer circuits connected to the first resistor string (figs. 1-3, ¶ 19-26, groups of decoders 26 with gamma assist circuits 24; see also fig. 4, ¶ 27-39, source follower circuit 34 disclosed; see also fig. 6, ¶ 45-46).
Saeki fails to disclose wherein for the first group of conversion circuits, a first resistor string is connected between an output of a buffer circuit for the first reference voltage and an output of a buffer circuit for the second reference voltage, and voltages generated by the first resistor string are supplied to the conversion circuits of the first group, wherein for the second group of conversion circuits, a second resistor string is connected between an output of a buffer circuit for the first reference voltage and an output of a buffer circuit for the second reference voltage, and voltages generated by the second resistor string are supplied to the conversion circuits of the second group.
Lo teaches wherein for the first group of conversion circuits, a first resistor string is connected between an output of a buffer circuit for the first reference voltage and an output of a buffer circuit for the second reference voltage, and voltages generated by the first resistor string are supplied to the conversion circuits of the first group (figs. 3-4, ¶ 35-43, e.g., gamma resistor string disclosed, see also ¶ 47-54; see also figs. 14-15),
wherein for the second group of conversion circuits, a second resistor string is connected between an output of a buffer circuit for the first reference voltage and an output of a buffer circuit for the second reference voltage, and voltages generated by the second resistor string are supplied to the conversion circuits of the second group (figs. 3-4, ¶ 35-43, e.g., gamma resistor string disclosed, see also ¶ 47-54; see also figs. 14-15).
Saeki and Lo are both directed to buffer circuits for reference voltage generating circuits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Saeki with the device of Lo since such a modification provides a general or basic buffer (Lo, ¶ 73) for rapidly settling and stabilizing gamma voltages (Lo, ¶ 3, ¶ 8), and voltage difference between source driver circuits may be reduced (Lo, ¶ 43).
Claims 8, 9, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Saeki in view of Kim et al. (US 2021/0193009).
Regarding claim 8, Saeki fails to disclose wherein the at least one reference voltage is supplied to the first group of conversion circuits further via a third buffer circuit, wherein the at least one reference voltage is supplied to the second group of conversion circuits further via a fourth buffer circuit, and wherein the third buffer circuit and the fourth buffer circuit are connected in parallel.
Kim teaches wherein the at least one reference voltage is supplied to the first group of conversion circuits further via a third buffer circuit, wherein the at least one reference voltage is supplied to the second group of conversion circuits further via a fourth buffer circuit, and wherein the third buffer circuit and the fourth buffer circuit are connected in parallel (fig. 3, ¶ 86-96, buffer circuits 124 and 224 connected in parallel; see also ¶ 104-105).
Saeki and Kim are both directed to buffer circuits for reference voltage generating circuits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Saeki with the device of Kim since such a modification eliminates a deviation in output between driving chips in a display (Kim, ¶ 7, ¶ 105).
Regarding claim 9, this claim is rejected under the same rationale as claim 8.
Regarding claim 21, Saeki fails to disclose a wearable device including a display apparatus configured to display an image, wherein the display apparatus includes a light emitting apparatus defined in claim 1.
Kim teaches a wearable device including a display apparatus configured to display an image, wherein the display apparatus includes a light emitting apparatus defined in claim 1 (¶ 4-7, small mobile communication terminal disclosed).
Saeki and Kim are both directed to buffer circuits for reference voltage generating circuits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Saeki with the device of Kim since such a modification eliminates a deviation in output between driving chips in a display (Kim, ¶ 7, ¶ 105).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Saeki in view of Lim et al. (US 2022/0328012).
Regarding claim 17, Saeki fails to disclose a first detector configured to detect an emission luminance in each of the plurality of light emitting devices, and a controller configured to control the buffer circuit, wherein the buffer circuit includes an output offset adjustment mechanism, and wherein the controller controls an output of the buffer circuit by the output offset adjustment mechanism, based on a detection result of the first detector, such that the emission luminance in each of the plurality of light emitting devices is corrected.
Lim teaches a first detector configured to detect an emission luminance in each of the plurality of light emitting devices (abstract, figs. 4-5, ¶ 50-54, e.g., maximum luminance detected; see also ¶ 85-86, ¶ 112, ¶ 125, ¶ 141-146),
and a controller configured to control the buffer circuit, wherein the buffer circuit includes an output offset adjustment mechanism, and wherein the controller controls an output of the buffer circuit by the output offset adjustment mechanism, based on a detection result of the first detector, such that the emission luminance in each of the plurality of light emitting devices is corrected (figs. 4-5, ¶ 50-54, e.g., maximum luminance detected; see also ¶ 85-86, ¶ 112, ¶ 125, ¶ 141-146, master/slave amplifiers enabled and/or disabled based on maximum luminance).
Saeki and Lim are both directed to buffer circuits for reference voltage generating circuits. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the device of Saeki with the device of Lim since such a modification reduces power consumption (Lim, ¶ 5, ¶ 145).
Response to Arguments
Applicant's arguments filed 8/4/26 have been fully considered but they are not persuasive. Regarding claim 1, Applicant argues “Saeki’s gamma assist circuitry does not provide … at least one reference voltage of the plurality of reference voltages is supplied from the voltage generator to each of the plurality of conversion circuits via a buffer circuit, with the first buffer circuit and the second buffer circuit being connected in series as claimed” (Remarks, pp. 2-3).
Examiner disagrees. As cited above, figs. 1-3 and ¶ 19-26 of Saeki show gamma assist circuits 24 serially connected with respect to each grayscale voltage (i.e., the output of a gamma assist circuit is connected to the input of a subsequent gamma assist circuit). Further, fig. 4 and ¶ 27-39 of Saeki discloses that each gamma assist unit circuit 28 comprises a source follower circuit 34 (i.e., a buffer circuit). Thus, Saeki discloses buffer circuits connected in series as is claimed.
The rejection of the claims is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEITH L CRAWLEY whose telephone number is (571)270-7616. The examiner can normally be reached Monday - Friday 10-6 ET.
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/KEITH L CRAWLEY/Primary Examiner, Art Unit 2626
