DETAILED ACTION
This office action is in response to the application filed on 02/06/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/06/2025 and 08/14/2025 has been considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in claims 23 and 33. Therefore, the “a unique second output voltage” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Examiner Note: A unique voltage would be one of a kind or unlike anything else, figures 17-18 and 20 show that the output voltages from the DC/DC converters output only two types of output levels and they are not unique because they repeated between the converters.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 35 and 39 are objected to because of the following informalities: Claims 35 and 39 recite “each of switched capacitor circuits” should be “each of the switched capacitor circuits”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 23-24, 26-29 and 31-40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muthukaruppan US 2014/0344589 (herein Muthu) in view of Low US 2020/0228002.
Regarding Claim 23, Muthu teaches (Figures 3-19) A power supply circuit (Fig. 3) comprising: a first node to which an input voltage is supplied (312); a second node from which a first output voltage is output (at 306); a plurality of DC-DC converters (at 318) that include switched capacitors (at 316), respectively, and are connected in parallel between the first node and the second node; and a first control circuit (at 304) configured to control the plurality of DC-DC converters individually (see fig. 16 and 19) , wherein the second node (306) is configured to output the first output voltage obtained by combining a plurality of the second output voltages (see fig. 3) output from the plurality of DC-DC converters (at 318), respectively. (For Example: Par. 53-54 and 86-100)
Muthu does not teach cause each of the plurality of DC-DC converters to output a unique second output voltage.
Low teaches (Figures 9-10) cause each of the plurality of DC-DC converters to output a unique second output voltage (see figs 10a-10dm 1/3 and 2/3 Iout, alternating). (For example: Par. 71-72)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Muthu to include cause each of the plurality of DC-DC converters to output a unique second output voltage as taught by Low to reduce internal energy losses due to redistribution of charges within the charge pump.
Regarding Claims 24 and 29, Muthu teaches (Figures 3-19) further comprising: a clock generation circuit (at 1642) configured to output a plurality of clock signals having different phases in association with the plurality of DC-DC converters (1644), wherein each of the plurality of DC-DC converters is configured to generate the second output voltage in synchronization with a corresponding clock signal (system clock) among the plurality of clock signals. (For Example: Par. 53-54 and 86-100)
Regarding Claims 26 and 31, Muthu teaches (Figures 3-19) wherein the plurality of DC-DC converters (318) includes a first DC-DC converter and a second DC- DC converter (at 316, fig. 3).
Muthu does not teach a value of a second output voltage output from the first DC-DC converter is different from a voltage of a second output voltage output from the second DC-DC converter.
Low teaches (Figures 9-10) a value of a second output voltage output from the first DC-DC converter (top converter) is different (1/3 and 2/3) from a voltage of a second output voltage output from the second DC-DC converter (bottom converter). (For example: Par. 71-72)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Muthu to include a value of a second output voltage output from the first DC-DC converter is different from a voltage of a second output voltage output from the second DC-DC converter, as taught by Low to reduce internal energy losses due to redistribution of charges within the charge pump.
Regarding Claims 27 and 32, Muthu teaches (Figures 3-19) wherein each of the plurality of DC-DC converters (418) includes a first switched capacitor circuit and a second switched capacitor circuit (316) having a similar configuration as the first switched capacitor circuit (fig. 4), and the first switched capacitor circuit and the second switched capacitor circuit are provided between the first node and the second node (412 and 406). (For Example: Par. 53-54 and 86-100)
Regarding Claim 28, Muthu teaches (Figures 3-19) a semiconductor integrated circuit (see fig. 17) comprising: the power supply circuit according to claim 23 (at 1701); and a circuity (load at 1700) configured to operate based on the first output voltage from the power supply circuit. (For Example: Par. 100-110)
Regarding Claim 33, Muthu teaches (Figures 3-19) a power supply circuit comprising: a first node (312) to which an input voltage is supplied; a second node (306) from which an output voltage is output; a plurality of DC-DC converters (318) connected in parallel between the first node and the second node; and a control circuit (Fig. 16) configured to control the plurality of DC-DC converters individually (see Fig. 19), wherein the plurality of DC-DC converters (318) include: a first DC-DC converter circuit including a first switched capacitor circuit (at 316); and a second DC-DC converter circuit (at 316) including a second switched capacitor circuit having a similar configuration as the first switched capacitor circuit (see fig. 4), and wherein the control circuit is configured to repeat a first switching state and a second switching state alternately (state 1-2, Figs. 4-7). (For Example: Par. 53-54 and 86-100)
Mutu does not teach cause each of the plurality of DC-DC converters to output a unique second output voltage; and the first switching state being a state in which a first capacitor in the first switched capacitor circuit is charged and a second capacitor in the second switched capacitor circuit is discharged, the second switching state being a state in which the second capacitor is charged and the first capacitor is discharged.
Low teaches (Figures 9-10) cause each of the plurality of DC-DC converters to output a unique second output voltage (see figs 10a-10dm 1/3 and 2/3 Iout, alternating); and the first switching state (1a) being a state in which a first capacitor in the first switched capacitor circuit is charged (C1a) and a second capacitor in the second switched capacitor circuit is discharged (C2a), the second switching state (2a) being a state in which the second capacitor is charged (C2a) and the first capacitor is discharged (C1a). (For example: Par. 71-72)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Muthu to include cause each of the plurality of DC-DC converters to output a unique second output voltage; and the first switching state being a state in which a first capacitor in the first switched capacitor circuit is charged and a second capacitor in the second switched capacitor circuit is discharged, the second switching state being a state in which the second capacitor is charged and the first capacitor is discharged, as taught by Low to reduce internal energy losses due to redistribution of charges within the charge pump.
Regarding Claims 34 and 38, Muthu teaches (Figures 3-19) wherein the control circuit (Fig. 16) is configured to perform switching control of the first switched capacitor circuit (416-1) and the second switched capacitor (416-2) circuit such that a capacitance on a side of the second node in the first switching state (Fig. 9) is equal to a capacitance on the second node side in the second switching state (Fig. 10). (For Example: Par. 53-54, 73-74 and 86-100)
Regarding Claims 35 and 39, Muthu teaches (Figures 3-19)further comprising: a clock generation circuit (1642) configured to output a plurality of clock signals (1644) having different phases in association with the plurality of DC-DC converters (318), wherein each of the plurality of DC-DC converters is configured to switch between the first switching state and the second switching state (state 1 and state 2, see figures 9-10) of each of switched capacitor circuits (418) included in each of the plurality of DC-DC converters in accordance with a logic (see fig. 19) of a corresponding clock signal (system clock) among the plurality of clock signals. (For Example: Par. 53-54 and 86-100)
Regarding Claims 36 and 40, Muthu teaches (Figures 3-19)wherein each of the plurality of DC-DC converters (318) includes a third switched capacitor circuit and a fourth switched capacitor circuit (see figs. 3-4) having a similar configuration (see fig. 3) as the third switched capacitor circuit, and the third switched capacitor circuit and the fourth switched capacitor circuit are provided between the first node and the second node (312 and 306). (For Example: Par. 53-54 and 86-100)
Regarding Claim 37, Muthu teaches (Figures 3-19) a semiconductor integrated circuit (see fig. 17) comprising: the power supply circuit according to claim 33 (at 1701); and a circuity (load at 1700) configured to operate based on the first output voltage from the power supply circuit. (For Example: Par. 100-110)
Claim(s) 25 and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muthukaruppan US 2014/0344589 (herein Muthu) in view of Low US 2020/0228002 and further in view of Ghayal et al. US 9658666.
Regarding Claims 25 and 30, Muthu teaches (Figures 3-19) a second control circuit configured to control whether to output each of the plurality of clock signals from the clock generation circuit based on a voltage level of the first output voltage (with 1650). (For Example: Par. 53-54 and 86-100)
Muthu does not teach wherein a first number of DC-DC converters to which the corresponding clock signals are supplied from the clock generation circuit among the plurality of DC-DC converters is configured to output the corresponding second output voltages, and the second node is configured to output the first output voltage obtained by combining the second output voltages from the first number of DC-DC converters to which the corresponding clock signals are supplied.
Ghayal teaches (Figures 3, 6-7) wherein a first number of DC-DC converters (activated circuit) to which the corresponding clock signals are supplied from the clock generation circuit (see fig. 3a-b) among the plurality of DC-DC converters is configured to output the corresponding second output voltages (Vout), and the second node is configured to output the first output voltage (at 102) obtained by combining the second output voltages from the first number of DC-DC converters (see fig. 7) to which the corresponding clock signals are supplied. (For example: Col. 7 and 11)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Muthu to include wherein a first number of DC-DC converters to which the corresponding clock signals are supplied from the clock generation circuit among the plurality of DC-DC converters is configured to output the corresponding second output voltages, and the second node is configured to output the first output voltage obtained by combining the second output voltages from the first number of DC-DC converters to which the corresponding clock signals are supplied as taught by Ghayal to improve efficiency across load current range.
Conclusion
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/GUSTAVO A ROSARIO-BENITEZ/ Primary Examiner, Art Unit 2838
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