DETAILED ACTION
Claims 1-20 are pending.
Priority: 10/15/2029(Continuation of 16/653,139
Assignee: Texas Instruments
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim(s) 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1-17 of U.S. Patent No. 11422938. Although the claims at issue are not identical, they are not patentably distinct from each other because each claim is an obvious variant of a corresponding claim.
Claim(s) 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1-20 of U.S. Patent No. 12223165. Although the claims at issue are not identical, they are not patentably distinct from each other because each claim is an obvious variant of a corresponding claim as shown below.
19/047,071(Instant)
12,223,165(parent)
1. A system comprising: a cache tag bank; a snoop filter bank coupled to the cache tag bank; a controller coupled to the cache tag bank and configurable to: receive a first read request that includes a first address tag; issue a first snoop request to a first peripheral when the first address tag is associated with a shared state in the snoop filter bank; if the first snoop request returns a first value, respond to the first read request with the first value; and retrieve a second value from an external memory and respond to the first read request with the second value if the first snoop request does not return a value.
1. A system comprising: a cache tag bank; a snoop filter bank coupled to the cache tag bank; a memory bank coupled to the cache tag bank; and a controller coupled to the cache tag bank, the controller configured to: receive a first read request that includes a first address tag; apply the first address tag to the snoop filter bank to determine that a unique state is associated with the first address tag; issue a first snoop request to a peripheral in response to determining that the unique state is associated with the first address tag; if the first snoop request returns a first value, respond to the first read request with the first value; and if the first snoop request does not return a value, retrieve a second value from the memory bank or from an external memory and respond to the first read request with the second value.
2. The system of claim 1, wherein the controller is configured to apply the first address tag to the snoop filter bank to determine that the first address tag is associated with the shared state.
(claim 1) apply the first address tag to the snoop filter bank to determine that a unique state is associated with the first address tag;
3. The system of claim 1, further comprising a memory bank coupled to the cache tag bank, wherein the controller is configured to: receive a second read request that includes a second address tag; determine that a third value associated with the second address tag is stored in the memory bank; and retrieve the third value from the memory bank when the second address tag is associated with an invalid state in the snoop filter bank.
2. The system of claim 1, wherein the controller is configured to: receive a second read request that includes a second address tag; determine that a third value associated with the second address tag is stored in the memory bank;
and determine a snoop state associated with the second address tag.
3. The system of claim 2, wherein the controller is configured to, in response to the snoop state indicating an invalid state: retrieve the third value from the memory bank; and respond to the second read request with the third value.
4. The system of claim 3, wherein the controller is configured to retrieve the third value from the memory bank without issuing a snoop request.
20. The system of claim 4, wherein the controller is configured to retrieve the third value from the memory bank without issuing a snoop request.
5. The system of claim 1, further comprising a memory bank coupled to the cache tag bank, wherein the controller is configured to: receive a second read request that includes a second address tag; determine that a third value associated with the second address tag is stored in the memory bank; and retrieve the third value from the memory bank when the second address tag is associated with the shared state in the snoop filter bank.
9. The system of claim 8, wherein: in response to the snoop state indicating the unique state or a shared state, the controller is configured to issue a second snoop request to a processor associated with the second address tag; in response to the second snoop request returning a third value, the controller is configured to respond to the second read request with the third value;
6. The system of claim 5, wherein the controller is configured to retrieve the third value from the memory bank without issuing a snoop request.
20. The system of claim 4, wherein the controller is configured to retrieve the third value from the memory bank without issuing a snoop request.
7. The system of claim 1, wherein the controller is configured to: receive a second read request that includes a second address tag; and retrieve a third value from the external memory when the second address tag is associated with an invalid state in the snoop filter bank.
2. The system of claim 1, wherein the controller is configured to: receive a second read request that includes a second address tag;
3. The system of claim 2, wherein the controller is configured to, in response to the snoop state indicating an invalid state: retrieve the third value from the memory bank; and respond to the second read request with the third value.
8. The system of claim 1, wherein the controller is configured to: receive a second read request that includes a second address tag; and issue a second snoop request to a second peripheral when the second address tag is associated with a unique state in the snoop filter bank; if the second snoop request returns a third value, respond to the second read request with the third value; and retrieve a fourth value from the external memory and respond to the second read request with the fourth value if the second snoop request does not return a value.
2. The system of claim 1, wherein the controller is configured to: receive a second read request that includes a second address tag;
(claim 9) 9. The system of claim 8, wherein: in response to the snoop state indicating the unique state or a shared state, the controller is configured to issue a second snoop request to a processor associated with the second address tag; in response to the second snoop request returning a third value, the controller is configured to respond to the second read request with the third value; and in response to the second snoop request not returning a value, the controller is configured to: retrieve a fourth value from the external memory;
9. The system of claim 1, further comprising a memory bank coupled to the cache tag bank, wherein the controller is configured to: receive a write request that includes a second address tag; and determine that a third value associated with the second address tag is stored in the memory bank; and write a fourth value associated with the second address tag to the memory bank when the second address tag is associated with an invalid state in the snoop filter bank.
5. The system of claim 1, wherein the controller is configured to: receive a write request that includes a second address tag; and determine that a third value associated with the second address tag is stored in the memory bank;
(claim 7) in response to the snoop state indicating an invalid state, the controller is configured to write a fourth value associated with the second address tag to the memory bank.
10. The system of claim 1, further comprising a memory bank coupled to the cache tag bank, wherein the controller is configured to: receive a write request that includes a second address tag; and determine that a third value associated with the second address tag is stored in the memory bank; and when the second address tag is associated with a unique state in the snoop filter bank: issue a second snoop request to a second peripheral associated with the second address tag to invalidate the third value stored by the second peripheral; and write a fourth value associated with the second address tag to the memory bank.
11. The system of claim 1, wherein the controller is configured to: receive a write request that includes a second address tag; and determine that a value associated with the second address tag is not stored in the memory bank; and determine a snoop state associated with the second address tag.
(claim 12) wherein the controller is configured to, in response to the snoop state indicating the unique state or a shared state: issue a second snoop request to a processor associated with the second address tag to invalidate a third first value stored by the processor; and write a fourth value associated with the second address tag to the external memory.
11. The system of claim 1, wherein the controller is configured to: receive a write request that includes a second address tag; and write a third value associated with the second address tag to the external memory when the second address tag is associated with an invalid state in the snoop filter bank.
3. The system of claim 2, wherein the controller is configured to, in response to the snoop state indicating an invalid state: retrieve the third value from the memory bank; and respond to the second read request with the third value.
6. The system of claim 5, wherein the controller is configured to, in response to the snoop state indicating the unique state or a shared state: issue a second snoop request to a processor associated with the second address tag to invalidate the third value stored by the processor; and write a fourth value associated with the second address tag to the memory bank.
12. The system of claim 1, wherein the controller is configured to: receive a write request that includes a second address tag; and when the second address tag is associated with the shared state in the snoop filter bank: issue a second snoop request to a second peripheral associated with the second address tag to invalidate a third value stored by the second peripheral; and write a fourth value associated with the second address tag to the external memory.
12. The system of claim 11, wherein the controller is configured to, in response to the snoop state indicating the unique state or a shared state: issue a second snoop request to a processor associated with the second address tag to invalidate a third first value stored by the processor; and write a fourth value associated with the second address tag to the external memory.
13. The system of claim 1, wherein the controller is configured to: determine that the snoop filter bank stores an identifier of the first peripheral, wherein the identifier is associated with the first address tag; and determine that the snoop filter bank indicates that data associated with the first address tag is stored in a cache of the first peripheral.
18. The system of claim 1, wherein the controller is configured to: determine that the snoop filter bank stores an identifier of the peripheral, wherein the identifier is associated with the first address tag; and determine that the snoop filter bank indicates that data associated with the first address tag is stored in a cache of the peripheral.
14. The system of claim 1, further comprising a memory bank coupled to the cache tag bank, wherein the cache tag bank is configured to be shared by the snoop filter bank and the memory bank.
(claim 14) a plurality of memory banks coupled to the plurality of cache tag banks
15. The method of claim 14, wherein: the plurality of cache tag banks includes a common cache tag bank; and the plurality of snoop filter banks and the plurality of memory banks share the common cache tag bank.
15. The system of claim 1, further comprising a memory bank coupled to the cache tag bank, wherein the cache tag bank is a common cache tag bank, and wherein the snoop filter bank and the memory bank share the common cache tag bank.
15. The method of claim 14, wherein: the plurality of cache tag banks includes a common cache tag bank; and the plurality of snoop filter banks and the plurality of memory banks share the common cache tag bank.
Allowable Subject Matter
Claim(s) 1-20 are allowed.
The following is an examiner’s statement of reasons for allowance. Claim(s) 1, 16 each contain the following limitations that distinguish the claims from the prior art:
“… A system comprising: a cache tag bank; a snoop filter bank coupled to the cache tag bank; a controller coupled to the cache tag bank and configurable to: receive a first read request that includes a first address tag; issue a first snoop request to a first peripheral when the first address tag is associated with a shared state in the snoop filter bank; if the first snoop request returns a first value, respond to the first read request with the first value; and retrieve a second value from an external memory and respond to the first read request with the second value if the first snoop request does not return a value.…”.
A related prior art is Pierson et al.(20140115272) where the interface has a first snoop address bus supplying a snoop address from the interface to a processing core. A command address bus supplies one of a read data address or a write data address to a multi-core shared memory controller. A data bus is adapted for receiving read data from the multi-core shared memory controller or supplying write data to the multi-core shared memory controller or supplying snoop response data to the multi-core shared memory controller. A second snoop address bus receives a snoop address from the multi-core shared memory controller. The interface allows adding a separate non-blocking pipeline for snoop returns in which the non-blocking pipeline is not blocked behind coherent requests so as to allow repartitioning the master initiated traffic to move cache evictions and non-coherent writes to the new non-blocking channel and remove a need for any coherent requests to complete before the snoop request can reach the memory controller, thus preventing deadlock issues when snoop and eviction occur concurrently.
A related prior art is Salisbury et al.(20160062890) where the interconnector has a snoop filter for allocating a new-snoop filter entry for target address. The snoop filter selects a victim snoop filter entry corresponding to victim address when snoop filter entries allocated for the target address are already allocated to another address and issues invalidate transaction for invalidating cached data for the victim address at set of devices. A coherency control circuitry performs coherency control operations for the invalidate transaction issued by the snoop filter to determine when the invalidate transaction is serviced. The interconnector avoids deadlock and reduces a circuit area and increases performance in the snoop filter. The interconnector allows transactions to progress beyond a point to include sufficient space in an eviction buffer if the buffer triggers the invalidate transaction, by preventing the transactions other than the invalidate transactions from progressing beyond a predetermined point when the eviction buffer is full. The snoop filter tracks snoops for lifetime of the transaction and updates snoop filter contents based on a snoop response.
The limitations distinguish from the prior art.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
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