The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination in this application (19/047,110) filed on February 6, 2025.
The Examiner cites particular sections in the references as applied to the claims below for the convenience of the applicant(s). Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant(s) fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
Claims 1-20 are pending for consideration.
Drawings
The drawings submitted on February 6, 2025 have been considered and accepted.
Information Disclosure Statement
Acknowledgment is made of the information disclosure statements filed on 6/13/2025. U.S. patents and Foreign Patents have been considered.
Claim Rejections - 35 U.S.C. 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 10 and 16 are rejected under 35 U.S.C. 112 (b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as claims recite “the processing device to perform”, where it is unclear if the storage device is performing the operations or its intended use is to perform the operations. Examiner suggest the language to recite “the processing device is configured to perform operations”. Claims also recite “good health status”, and “bad health status” as it is a relative term that was not defined.
All dependent claims are rejected as having the same deficiencies as the claims they depend from.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103(a) as being disclosed by Namala et al. (US PGPUB 2023/0033870 hereinafter referred to as Namala), and further in view of Srinivasan et al. (US PGPUB 2021/0232508 hereinafter referred to as Srinivasan) and further in view of Mukhopadhya et al. (US PGPUB 2017/0031656 hereinafter referred to as Mukhopadhya).
As per independent claim 1, Namala discloses a system comprising: a memory device; and a processing device operatively coupled to the memory device [(Paragraphs 0033-0040; FIG. 1-4 and related text) wherein Namala teaches Memory device 100 may include one or more memory controllers 105. Controller 105 may include processing circuitry 110 which may include one or more hardware processors 115. Processors 115 may be general purpose hardware processors that execute firmware or other software instructions for performing operations of the memory device, including implementing the host interface 123 and memory die interface 125to correspond to the claimed limitation].
Despite Namala teaches a defect may be identified with a first portion of a block of memory cells that may allow another portion to be utilized, the defect being of a type from a first identified list of defect types. The first identified list may comprise word line to word line shorts in data word lines, slow to program word lines, wordlines that do not pass the RBFR requirements, and resistive wordlines [(Paragraphs 0087)]; Namala does not appear to explicitly disclose setting a partial translation unit (TU) pointer to identify a first partial-TU of an ordered sequence of partial-TUs, the ordered sequence spanning over a plurality of dies of the memory device; responsive to determining that the first partial-TU has a good health status, appending the first partial-TU to a partial-TU stripe and incrementing the partial-TU pointer to identify a second partial-TU.
However, Srinivasan discloses setting a partial translation unit (TU) pointer to identify a first partial-TU of an ordered sequence of partial-TUs, the ordered sequence spanning over a plurality of dies of the memory device; responsive to determining that the first partial-TU has a good health status, appending the first partial-TU to a partial-TU stripe and incrementing the partial-TU pointer to identify a second partial-TU [(Paragraphs 0061-0064; FIG. 1-4 and related text) wherein Srinivasan teaches where the LWP search using the page map information shown in FIGS. 5A and 5B can be initiated via a LWP search command initiated by a system controller (e.g., 215) responsive to a loss of LWP information of a system (e.g., system 104). The LWP search command can be executed by one or more memory devices (e.g., 210-1 to 210-N) without further intervention from the system controller 215 (e.g., without providing subsequent commands such as page read commands to the memory devices 210). The search may commence by performing an word line search (e.g., a binary search of the word lines WL0 through WL10) for a particular one of the sub-blocks (e.g., sub-block SB0). Since the of the physical pages of a block may be programmed sequentially (e.g., starting at page “0” and ending at page “66”), a binary word line search of one of the sub-blocks can be sufficient to obtain the word line corresponding to the LWP. However, if a memory device comprises multiple decks of sub-blocks, a separate binary search of the word lines may be performed on a sub-block from each of the decks (e.g., to determine which deck includes the LWP) to correspond to the claimed limitation].
Namala and Srinivasan are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Namala and Srinivasan before him or her, to modify the method of Namala to include the binary search of Srinivasan because it will enhance efficiency.
The motivation for doing so would be [“provide benefits, such as reducing a TTR of a memory system and/or input/output (I/O) traffic within the memory system, as compared to prior approaches. For instance, a number of embodiments can perform a last written page (LWP) search internal to memory devices coupled to a system controller, as opposed to by using the system controller itself” (Paragraph 0015 by Srinivasan)].
Namala does not appear to explicitly disclose responsive to determining that the second partial-TU has a bad health status, incrementing the partial-TU pointer without adding the second partial-TU to the partial- TU stripe; and performing one or more write operations on a plurality of TUs comprised by the partial-TU stripe.
However, Mukhopadhya discloses responsive to determining that the second partial-TU has a bad health status, incrementing the partial-TU pointer without adding the second partial-TU to the partial- TU stripe; and performing one or more write operations on a plurality of TUs comprised by the partial-TU stripe [(Paragraphs 0020, 0029 and 0040; FIG. 1 and related text) wherein Mukhopadhya teaches where the memory die defect identification module 130 can identify the random defect in the memory die 120 by simply reading the stored information. For example, the stored information can indicate one or more of the following: a bad block list, a bad bit location, a partial bad block list, a partial good block list, a grown bad block list (“grown” meaning that the defect developed over time), and a list of defective wordlines (e.g., offset locations in a block). Instead of reading stored information about previous-detected defects, the memory die defect identification module 130 can be configured with a self-test feature to determine defects after the manufacturing of the memory die 120 (e.g., in the field). For example, the memory die defect identification module 130 can program a set of memory cells in the memory with known data, then read back the stored data to see if it matches (e.g., within a margin of error) the known data. If it does not, the memory die defect identification module 130 can identify that set of memory cells as having a defect to correspond to the claimed limitation].
Namala, Srinivasan and Mukhopadhya are analogous art because they are from the same field of endeavor of data storage management.
Before the effective filing date of the claimed inventions, it would have been obvious to one of ordinary skill in the art, having the teachings of Namala, Srinivasan and Mukhopadhya before him or her, to modify the method of Namala to include the defect detection module of Mukhopadhya because it will enhance efficiency.
The motivation for doing so would be [“provide a very simple way for generating a seed value for the generation of random number and can be implemented in existing memory systems without additional hardware support. Generating a seed value on the inherent randomness of the defects in a memory die provides a highly non-repeatable value and, thus, can generate non-overlapping random sequences across numerous memory systems. This is especially beneficial for memory systems that use a seed value to generate a random number for secure communication with another device for data security and protection” (Paragraph 0050 by Mukhopadhya)].
Namala further discloses performing one or more write operations on a plurality of TUs comprised by the partial-TU stripe [(Paragraphs 0040-0041 and 0048-0049; FIG. 1-4 and related text) wherein Namala teaches where the Host device 135 may send one or more commands, such as read comments, write commands, erase commands, and the like to the memory device 100 through the host interface 123. Host interface 123 may be part of controller 105 or may be implemented by separate circuitry. The memory device 100 may send data, command responses, and the like to host device 135 over the host interface over the host bus 137 to correspond to the claimed limitation].
Therefore, it would have been obvious to combine Namala, Srinivasan and Mukhopadhya to obtain the invention as specified in the instant claim.
As per dependent claim 2, Namala discloses wherein the second partial-TU comprises a plurality of translation sub-units (TSUs), and wherein the health status of the second partial-TU is determined to be bad in response to determining that a health status of at least one TSU of the plurality of TSUs of the second partial-TU is bad [(Paragraphs 0059-0061; FIG. 1-4 and 7 and related text) wherein Namala teaches that between applications of one or more programming pulses (e.g., Vpgm), a verify operation can be performed to determine if a selected memory cell has reached its intended programmed state. If the selected memory cell has reached its intended programmed state, it can be inhibited from further programming. If the selected memory cell has not reached its intended programmed state, additional programming pulses can be applied. If the selected memory cell has not reached its intended programmed state after a particular number of programming pulses (e.g., a maximum number), the selected memory cell, or a string, block, or page associated with such selected memory cell, can be marked as defective to correspond to the claimed limitation].
As per dependent claim 3, Namala discloses wherein the first partial-TU comprises a plurality of TSUs, and wherein the health status of the first partial-TU is determined to be good in response to determining a health status of each TSU of the plurality of TSUs of the first partial-TU is determined to be good [(Paragraphs 0084-0085; FIG. 1-4 and 7 and related text) wherein Namala teaches wherein the memory device may utilize the bottom deck 715 by application of bias voltages to the top deck 710 during operations to the bottom deck. The bottom deck 715 may thus be a salvageable deck that may be used to store user data, system data, system overprovisioning, or the like. As previously noted, a salvageable deck in some examples is a deck whose memory cells do not have a defect from a first group of defect types, but is part of a block in which at least one other deck has a defect from a second group of defect types. In some examples, the second group of defect types may include a word line-to-word line short, a resistive word line, a slow to program cell, and defects where a raw bit error rate (RBER) metric exceeds a threshold. In some examples, the first group of defect types include the second group of defect types and additional defect types such as word line to pillar shorts, SGS and SGD shorts, dummy word line shorts, and other defects that would typically cause the block to be marked as bad to correspond to the claimed limitation].
As per dependent claim 4, Namala discloses wherein the operations further comprise updating physical to logical (P2L) address mappings of a P2L table of the memory device in response to incrementing the partial-TU pointer without adding a partial-TU to the partial-TU stripe [(Paragraphs 0168; FIG. 1-4 and related text) wherein Namala teaches wherein forming the virtual block comprises creating a table entry in a L2P table indicating that the first and second portions form a virtual block to correspond to the claimed limitation].
As per dependent claim 5, Namala discloses wherein the determining the health status of the first partial-TU and the health status of the second partial-TU is based on a data structure comprising a plurality of elements, wherein an element of the data structure indicates a health status of a corresponding partial-TU [(Paragraphs 0089 and 0110-0112; FIG. 1-4 and related text) wherein Namala teaches Responsive to identifying that there is a defect with a first portion at operation 910 and that a second portion does not have a defect at operation 915, the first portion may be marked defective by the memory device, and the second portion may be marked as salvageable. For example, the portions may be marked in a Logical-to-Physical (L2P) table in a controller, in the memory portion itself, in a table in a memory die that flags defective blocks and/or portions, a one-time programmable area, and the like. In some examples, both portions may initially be marked as “bad” and after turning on a particular feature to use the salvageable portions, the memory device may update the designation of each portion of each block that is marked as bad if there is a salvageable portion. In some examples, prior to marking the portion as salvageable, the system may test the second portion, e.g., as shown in FIG. 10 to correspond to the claimed limitation].
As per dependent claim 6, Namala discloses wherein the operations further comprise generating a data structure comprising a plurality of elements, wherein an element of the data structure indicates a health status of a corresponding partial-TU [(Paragraphs 0110-0112; FIG. 1-4 and related text) wherein Namala teaches using salvageable portions of memory blocks marked as defective happen automatically, but in other examples, this may be a feature that may be enabled—either during device setup and/or initialization or during runtime. For example, blocks that are salvageable may be marked as salvageable after manufacturing during initial testing, but not enabled. The salvageable blocks may be enabled once a number of initially good blocks are marked as bad (e.g., they have degraded from use and the data thereon fails decoding of error correction coding (ECC) a threshold number of times). This allows the memory device to continue to store the advertised capacity for longer and thus increases the service life of the memory device. For example, the newly available salvageable blocks may be used to store user data, used for overprovisioning, used for temporary storage (such as during garbage collection), used for system data, or the like. The use of salvageable portions may be enabled by logic on the memory die itself, enabled by a controller of the memory device, a host, or the like. Once activated, the memory die or the controller may add the previously identified salvageable portions to a logical-to-physical mapping table as an available block or block portion. In some examples, as previously described the controller may form virtual blocks with one or more multiple block portions as described with respect to FIGS. 11-14 to correspond to the claimed limitation].
As per dependent claim 7, Namala discloses wherein the generating the data structure is done in at least one of a pre-runtime state or a runtime state of the memory device [(Paragraphs 0110-0112; FIG. 1-4 and related text) wherein Namala teaches using salvageable portions of memory blocks marked as defective happen automatically, but in other examples, this may be a feature that may be enabled—either during device setup and/or initialization or during runtime. For example, blocks that are salvageable may be marked as salvageable after manufacturing during initial testing, but not enabled. The salvageable blocks may be enabled once a number of initially good blocks are marked as bad (e.g., they have degraded from use and the data thereon fails decoding of error correction coding (ECC) a threshold number of times). This allows the memory device to continue to store the advertised capacity for longer and thus increases the service life of the memory device. For example, the newly available salvageable blocks may be used to store user data, used for overprovisioning, used for temporary storage (such as during garbage collection), used for system data, or the like. The use of salvageable portions may be enabled by logic on the memory die itself, enabled by a controller of the memory device, a host, or the like. Once activated, the memory die or the controller may add the previously identified salvageable portions to a logical-to-physical mapping table as an available block or block portion. In some examples, as previously described the controller may form virtual blocks with one or more multiple block portions as described with respect to FIGS. 11-14 to correspond to the claimed limitation].
As per dependent claim 8, Namala discloses wherein the operations further comprise performing one or more read operations on the plurality of TUs comprised by the partial-TU stripe [(Paragraphs 0110-0112; FIG. 1-4 and related text) wherein Namala teaches flowchart of a method 1300 of forming multiplane virtual blocks from multiple single plane virtual blocks is shown according to some examples of the present disclosure. Method 1300 may be performed by either, or both of a controller (such as controller 105) or by a memory control unit (such as memory control unit 430) on one or more memory dies (such as memory die 400, 130A-130N+1). At operation 1310 a first single plane virtual block on a first plane is identified. For example, using the process of FIG. 12. At operation 1315 a second virtual block on a second plane is identified. For example, using the process of FIG. 12. At operation 1320, a multiplane virtual block may be created from both the first and second virtual blocks identified in operations 1310 and 1315. For example, the memory controller may store information on the makeup of the multiplane virtual blocks in a data structure. For example, the logical to physical translation table that translates logical addresses to valid physical addresses may be used to correspond to the claimed limitation].
As per dependent claim 9, Namala discloses wherein the partial-TU stripe is a half-block stripe [(Paragraph 0140; FIG. 1-4 and related text) wherein Namala teaches wherein the first portion is a first deck of the block and the second portion is a second deck of the block to correspond to the claimed limitation].
As for independent claims 10 and 16, the applicant is directed to the rejections to claim 1 set forth above, as they are rejected based on the same rationale.
As for dependent claim 11, the applicant is directed to the rejections to claim 2 set forth above, as they are rejected based on the same rationale.
As for dependent claim 12, the applicant is directed to the rejections to claim 3 set forth above, as they are rejected based on the same rationale.
As for dependent claims 13 and 17, the applicant is directed to the rejections to claim 5 set forth above, as they are rejected based on the same rationale.
As for dependent claims 14 and 18, the applicant is directed to the rejections to claim 6 set forth above, as they are rejected based on the same rationale.
As for dependent claims 15 and 19, the applicant is directed to the rejections to claim 7 set forth above, as they are rejected based on the same rationale.
As for dependent claim 20, the applicant is directed to the rejections to claim 9 set forth above, as they are rejected based on the same rationale.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jared Ian Rutz whose telephone number is (571)272-5535. The examiner can normally be reached on Monday-Friday, 8:00 AM to 4:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared Rutz can be reached on 571-272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-270-2857.
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/MOHAMED M GEBRIL/Primary Examiner, Art Unit 2135