CTNF 19/047,192 CTNF 100758 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Khandare (US 2019/0347047 A1) in view of Eliash (US 2021/0407613 A1) . In regards to claim 1, Khandare teaches: and data path emulation circuitry configured to: toggle between a first data set and a second data set to be provided to the error checking component from an emulated data path to monitor a property of the data path; (0056, the flash interface manager 204 may implement a parametric ONFI2/3/4 or Toggle2/3 or Async device interface. The interface may be “parametric” in the sense that its behavior in terms of signal timing may be controllable via parameters. The metadata and control manager 214 may further configure the status information provided to the SSD controller 104 by the flash interface manager 204. Example status information that may be maintained by the flash interface manager 204 as part of the parametric interface may include an ONFIx/ToggleX status register, a read latency parameter, a device ready parameter, a device fail parameter, and a detection threshold. Of course, these examples are not limiting and the status information provided may vary based on the type of flash storage device being emulated (e.g., based on the standard or specifications of the emulated flash storage device).) and determine whether to provide data to the error checking component from the data path or from the emulated data path based on an operational mode of the device. (0063, In the example illustrated in FIG. 3, the flash error emulation module 310 is positioned on the data path between the data buffer 206 and the DDR controller 212. In this manner, the flash error emulation module 310 can control data 315 being read from, and/or programmed to, the DDR 110.) Khandare fails to teach: An apparatus, comprising: a device having a data path associated therewith; an error checking component coupled to the device and configured to receive data from the device via the data path; However, Eliash teaches: An apparatus, comprising: a device having a data path associated therewith; an error checking component coupled to the device and configured to receive data from the device via the data path; (0050, Each NOC (202/204) is connected to SRAM (230/260), a buffer (232/262), processor (220/250), and a data path controller (222/252) via an XOR engine (224/254), an ECC engine (226/256). The ECC engines 226/256 are used to perform error correction, as known in the art. Herein, the ECC engines 226/256 may be referred to as controller ECC engines.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the virtual solid state storage system is provided with solid state storage error emulation of Khandare with the teaching of Eliash, which teaches control die is configured to program user data to and read user data from the memory die based on one or more operational parameters in order improve calibration efficiency. (Eliash: 0004, One reason that calibration takes so much time is the need to transfer data between the die being tested and an external testing/calibration computer via a narrow interface using a slow protocol.) In regards to claim 2, Khandare in view of Eliash teaches the apparatus of claim 1. Khandare teaches: wherein the emulated data path includes one or more flip-flop circuits, one or more multiplexors, one or more delay circuits, and one or more gates to mimic a timing of the data path of the device. (0063, The flash error emulation module 310 can flips bits, for example, in data 315 being sent to the DDR 110 and/or in data 315 read from the DDR 110. In addition, the exemplary flash error emulation module 310 is also connected to the status buffer 210, which holds the flash status responses 330 to be sent back to the SSD controller 104.) In regards to claim 3, Khandare in view of Eliash teaches the apparatus of claim 1. Khandare teaches: wherein the data path is a read data path when the device is a memory device and the property is one of a timing of the read data path or a data integrity of the emulated data path. (0046 & 0056, the virtual flash device 108 may operate such that all the processing for the write path and read path, along with the behavior modeling and book-keeping of meta-data is contained within the virtual flash device 108. In addition, the virtual flash device 108 may perform address translation between an emulated address space of the emulated flash storage device and an address space of the memory 110. signal timing may be controllable via parameters;) In regards to claim 4, Khandare in view of Eliash teaches the apparatus of claim 1. Khandare teaches: wherein the operational mode is one of a read mode and a non- read mode. (0046, the virtual flash device 108 may operate such that all the processing for the write path and read path.) In regards to claim 5, Khandare in view of Eliash teaches the apparatus of claim 4. Khandare teaches: wherein the data path emulation circuitry is configured to provide data from the data path to the error checking component when the device is in the read mode and provide data from the emulated data path when the device is in the non-read mode. (0046, the virtual flash device 108 may operate such that all the processing for the write path and read path, along with the behavior modeling and book-keeping of meta-data is contained within the virtual flash device 108. In addition, the virtual flash device 108 may perform address translation between an emulated address space of the emulated flash storage device and an address space of the memory 110.) In regards to claim 6, Khandare in view of Eliash teaches the apparatus of claim 1. Khandare teaches: wherein the data path emulation is configured to generate a signal when a timing of the data provided to the error checking component from the emulated data path is outside a timing threshold. (0055 & 0056, the virtual flash device 108 provide different or additional monitor information, a determination that the metadata indicates a threshold has been reached; signal timing may be controllable via parameters) In regards to claim 7, Khandare in view of Eliash teaches the apparatus of claim 1. Khandare teaches: wherein the data path emulation circuitry is configured to switch a multiplexor to either provide data to the error checking component from the data path or provide toggled data from the emulated data path based on an operational mode of the device. (0063 & 0056, The flash error emulation module 310 can flips bits, for example, in data 315 being sent to the DDR 110 and/or in data 315 read from the DDR 110. In addition, the exemplary flash error emulation module 310 is also connected to the status buffer 210, which holds the flash status responses 330 to be sent back to the SSD controller 104. parametric interface may include an ONFIx/ToggleX status register) In regards to claim 8, Khandare teaches: providing the clock signal to data path emulation circuitry configured to monitor a timing of the data path by: providing the clock signal to an emulated data path; toggling between at least a first data set and a second data set; and providing the toggled data to the error checking component based on the clock signal; (0056, the flash interface manager 204 may implement a parametric ONFI2/3/4 or Toggle2/3 or Async device interface. The interface may be “parametric” in the sense that its behavior in terms of signal timing may be controllable via parameters. The metadata and control manager 214 may further configure the status information provided to the SSD controller 104 by the flash interface manager 204. Example status information that may be maintained by the flash interface manager 204 as part of the parametric interface may include an ONFIx/ToggleX status register, a read latency parameter, a device ready parameter, a device fail parameter, and a detection threshold. Of course, these examples are not limiting and the status information provided may vary based on the type of flash storage device being emulated (e.g., based on the standard or specifications of the emulated flash storage device).) and determining whether to provide data to the error checking component from the data path or from the emulated data path based on an operational mode of the device. (0063, In the example illustrated in FIG. 3, the flash error emulation module 310 is positioned on the data path between the data buffer 206 and the DDR controller 212. In this manner, the flash error emulation module 310 can control data 315 being read from, and/or programmed to, the DDR 110.) Khandare fails to teach: A method, comprising: providing a clock signal to a device having a data path associated therewith, the data path being associated with providing data from the device to an error checking component; However, Eliash teaches: A method, comprising: providing a clock signal to a device having a data path associated therewith, the data path being associated with providing data from the device to an error checking component; (0050, Each NOC (202/204) is connected to SRAM (230/260), a buffer (232/262), processor (220/250), and a data path controller (222/252) via an XOR engine (224/254), an ECC engine (226/256). The ECC engines 226/256 are used to perform error correction, as known in the art. Herein, the ECC engines 226/256 may be referred to as controller ECC engines.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the virtual solid state storage system is provided with solid state storage error emulation of Khandare with the teaching of Eliash, which teaches control die is configured to program user data to and read user data from the memory die based on one or more operational parameters in order improve calibration efficiency. (Eliash: 0004, One reason that calibration takes so much time is the need to transfer data between the die being tested and an external testing/calibration computer via a narrow interface using a slow protocol.) In regards to claim 9, Khandare in view of Eliash teaches the method of claim 8. Khandare teaches: further comprising preventing the clock signal from being provided to the emulated data path when the operation mode of the device is a read operational mode. (0056, the flash interface manager 204 may implement a parametric ONFI2/3/4 or Toggle2/3 or Async device interface.) In regards to claim 10, Khandare in view of Eliash teaches the method of claim 8. Khandare teaches: wherein the emulated data path is configured to provide the toggled data to the error checking component within a threshold timing associated with the data path of the device. (0071, When a given count reaches a specific threshold, the metadata and control manager 214 programs the flash error emulation module 310 to send one or more errors for the page or block which has crossed the threshold.) In regards to claim 11, Khandare in view of Eliash teaches the method of claim 8. Khandare teaches: further comprising determining whether to provide data to the error checking component from the data path or from the emulated data path based on an operational mode of a data bus associated with the device. (0046, the virtual flash device 108 may operate such that all the processing for the write path and read path, along with the behavior modeling and book-keeping of meta-data is contained within the virtual flash device 108. In addition, the virtual flash device 108 may perform address translation between an emulated address space of the emulated flash storage device and an address space of the memory 110.) In regards to claim 12, Khandare in view of Eliash teaches the method of claim 11. Khandare teaches: wherein the operational mode of the data bus includes a data transfer operational mode and a non-operational mode. (0023, the present disclosure relates to devices and systems that may emulate a flash storage device to a flash storage controller to allow for testing error functionality of the operation of the flash storage controller.) In regards to claim 13, Khandare in view of Eliash teaches the method of claim 8. Khandare teaches: further comprising determining when a detected error is associated with data from the data path or toggled data from the emulated data path. (0046 & 0063, the virtual flash device 108 provide different or additional monitor information, a determination that the metadata indicates a threshold has been reached; signal timing may be controllable via parameters) In regards to claim 14, Khandare in view of Eliash teaches the method of claim 8. Khandare teaches: further comprising determining an error is associated with the data path in response to determining a timing of the emulated data path is outside a timing threshold. (0055 & 0056, the virtual flash device 108 provide different or additional monitor information, a determination that the metadata indicates a threshold has been reached; signal timing may be controllable via parameters) In regards to claim 15, Khandare teaches: and data path emulation circuitry configured to: determine an operational mode of the device; provide a clock signal to an emulated data path in response to the operational mode of the device being a non-read operational mode; toggle between a first data set and a second data set in response to the clock signal being provided to the emulated data path; provide the toggled data to the error checking component from the emulated data path to monitor a timing of the data path; (0056, the flash interface manager 204 may implement a parametric ONFI2/3/4 or Toggle2/3 or Async device interface. The interface may be “parametric” in the sense that its behavior in terms of signal timing may be controllable via parameters. The metadata and control manager 214 may further configure the status information provided to the SSD controller 104 by the flash interface manager 204. Example status information that may be maintained by the flash interface manager 204 as part of the parametric interface may include an ONFIx/ToggleX status register, a read latency parameter, a device ready parameter, a device fail parameter, and a detection threshold. Of course, these examples are not limiting and the status information provided may vary based on the type of flash storage device being emulated (e.g., based on the standard or specifications of the emulated flash storage device).) and determine whether data provided to the error checking component is from the data path or from the emulated data path based on the operational mode of the device. (0063, In the example illustrated in FIG. 3, the flash error emulation module 310 is positioned on the data path between the data buffer 206 and the DDR controller 212. In this manner, the flash error emulation module 310 can control data 315 being read from, and/or programmed to, the DDR 110.) Khandare fails to teach: A system, comprising: a device having a data path associated therewith; an error checking component coupled to the device and configured to receive data from the device via the data path; However, Eliash teaches: A system, comprising: a device having a data path associated therewith; an error checking component coupled to the device and configured to receive data from the device via the data path; (0050, Each NOC (202/204) is connected to SRAM (230/260), a buffer (232/262), processor (220/250), and a data path controller (222/252) via an XOR engine (224/254), an ECC engine (226/256). The ECC engines 226/256 are used to perform error correction, as known in the art. Herein, the ECC engines 226/256 may be referred to as controller ECC engines.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the virtual solid state storage system is provided with solid state storage error emulation of Khandare with the teaching of Eliash, which teaches control die is configured to program user data to and read user data from the memory die based on one or more operational parameters in order improve calibration efficiency. (Eliash: 0004, One reason that calibration takes so much time is the need to transfer data between the die being tested and an external testing/calibration computer via a narrow interface using a slow protocol.) In regards to claim 16, Khandare in view of Eliash teaches the system of claim 15. Khandare teaches: wherein the non-read operational mode is an operational mode where the device is not performing a read operation utilizing the data path. (0032, In operation, the configuration device 106 may send configuration information 114 to the virtual flash device 108 and receive monitor information 116 from the virtual flash device 108.) In regards to claim 17, Khandare in view of Eliash teaches the system of claim 15. Khandare teaches: wherein emulated data path includes delay circuitry to mimic a timing of the data path based on a propagation time and a margin time of the data path. (0063, The flash error emulation module 310 can flips bits, for example, in data 315 being sent to the DDR 110 and/or in data 315 read from the DDR 110. In addition, the exemplary flash error emulation module 310 is also connected to the status buffer 210, which holds the flash status responses 330 to be sent back to the SSD controller 104.) In regards to claim 18, Khandare in view of Eliash teaches the system of claim 15. Khandare teaches: wherein the first data set is a first static data set and the second data set is a second static data set that is different from the first static data set. (0043, the SSD controller 104 using the memory 110 as storage for data 112 that would otherwise be stored to the emulated flash storage device. The virtual flash device 108 may also provide monitor information 116 to the configuration device 106.) In regards to claim 19, Khandare in view of Eliash teaches the system of claim 15. Khandare teaches: wherein the error checking component is further configured to receive the toggled data from the emulated data path to determine a property of the emulated data path. (0056, the flash interface manager 204 may implement a parametric ONFI2/3/4 or Toggle2/3 or Async device interface. The interface may be “parametric” in the sense that its behavior in terms of signal timing may be controllable via parameters. The metadata and control manager 214 may further configure the status information provided to the SSD controller 104 by the flash interface manager 204. Example status information that may be maintained by the flash interface manager 204 as part of the parametric interface may include an ONFIx/ToggleX status register, a read latency parameter, a device ready parameter, a device fail parameter, and a detection threshold. Of course, these examples are not limiting and the status information provided may vary based on the type of flash storage device being emulated (e.g., based on the standard or specifications of the emulated flash storage device).) In regards to claim 20, Khandare in view of Eliash teaches the system of claim 19. Khandare teaches: wherein the error checking component is further configured to compare the timing of the emulated data path to an expected timing and generate a timing violation when the timing of the emulated data path is outside a threshold of the expected timing. (0055, a determination that the metadata indicates a threshold has been reached) Prior Art Made of Record The prior art mode of record and not relied upon is considered pertinent to Applicant’s disclosure: Sforzin (US 2022/0415426 A1): Methods, systems, and devices for shared error correction coding (ECC) circuitry are described. For example, a memory device configured with shared ECC circuitry may be configured to receive data at the shared circuitry from either a host device or a set of memory cells of the memory device. The shared circuitry may be configured to generate a set of multiple syndromes associated with a cyclic error correction code, based on the received data. As part of an encoding process, an encoder circuit may generate a set of parity bits based on the generated syndromes. As part of a decoding process, a decoder circuit may generate an error vector for decoding the received data, based on the generated syndromes. The decoder circuit may also correct one or more errors in the received data based on generating the error vector. Huang (US 2023/0207028 A1): A threshold criterion of a plurality of threshold criteria is identified based on a current program-erase cycle (PEC) count of a first block of a memory device, wherein the first block is configured as quad-level cell (QLC) memory. A raw bit error rate (RBER) associated with data of a second block of the memory device is determined, wherein the second block is configured as single-level cell (SLC) memory. It is determined that the RBER associated with the data of the second block satisfies the threshold criterion. In response to determining that the RBER satisfies the threshold criterion, the data of the second block is written to the first block. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR PERRY whose telephone number is (571)272-6319. The examiner can normally be reached Monday - Friday 8:00 - 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached on (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /V.P./Examiner, Art Unit 2111 /GUERRIER MERANT/Primary Examiner, Art Unit 2111 5/1/2026 Application/Control Number: 19/047,192 Page 2 Art Unit: 2111 Application/Control Number: 19/047,192 Page 3 Art Unit: 2111 Application/Control Number: 19/047,192 Page 4 Art Unit: 2111 Application/Control Number: 19/047,192 Page 5 Art Unit: 2111 Application/Control Number: 19/047,192 Page 6 Art Unit: 2111 Application/Control Number: 19/047,192 Page 7 Art Unit: 2111 Application/Control Number: 19/047,192 Page 8 Art Unit: 2111 Application/Control Number: 19/047,192 Page 9 Art Unit: 2111 Application/Control Number: 19/047,192 Page 10 Art Unit: 2111 Application/Control Number: 19/047,192 Page 11 Art Unit: 2111 Application/Control Number: 19/047,192 Page 12 Art Unit: 2111 Application/Control Number: 19/047,192 Page 13 Art Unit: 2111 Application/Control Number: 19/047,192 Page 14 Art Unit: 2111
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