CTNF 19/047,257 CTNF 100758 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1 – 5, 7, & 12 - 20 are rejected under 35 U.S.C. 103 as being unpatentable over Northcott (US 9183085 B1) in view of Ditty (US 2023/0036130 A1) . In regards to claim 1, Northcott teaches: A storage device comprising: a nonvolatile memory device; and a memory controller configured to control the nonvolatile memory device, wherein the memory controller includes :an internal buffer configured to store first data read from the nonvolatile memory device; (71, data can be accumulated in a data buffer in the controller prior to any write commands being issued;) and an error correction code block configured to read the first data from the internal buffer, correct an error of the first data, perform an error correction operation that performs an error correction loop for the first data, (149, In the stage 813, the process de-interleaves the secondary codewords and returns the corrected data to the format or order used for decode of the primary ECC. The process returns to the stage 808 to continue iteration of the loop.) perform an estimation operation that estimates an error level of second data, the second data being obtained as an execution result of the error correction loop for the first data, based on the error level estimated in the estimation operation being uncorrectable in a next error correction operation, perform the next error correction operation and the estimation operation, (130, the primary LDPC decoder adjusts error likelihood estimations (LLRs) to reflect the outcome of the grid decoding, setting higher confidence on bits which were part of successfully corrected by the grid decoder, and lower confidence on those which were part of uncorrectable grid codewords.) Northcott fails to teach: and based on the error level being correctable in the next error correction operation, perform the next error correction operation and perform a check operation that checks integrity of third data used in the next error correction operation. However, Ditty teaches: and based on the error level being correctable in the next error correction operation, perform the next error correction operation and perform a check operation that checks integrity of third data used in the next error correction operation. (0219, 0143, & 0148, the system may set a threshold value for the confidence and consider only the detections exceeding the threshold value as true positive detections; The SI 110 passes the read data through the error detection block 272, which determines a check code for the read data and compares the error detection code with the check code. In block 916, the error detection block 272 determines a check code for each of the error detection code(s) obtained in block 914;) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus and methods that provide low uncorrectable bit error rates of Northcott with the teaching of Ditty, which teaches a system operating based on risk level in order improve reliability and efficiency. (Ditty: 0028, To avoid at least some of the latency and expense;) In regards to claim 2, Northcott in view of Ditty teaches the storage device of claim 1. Northcott fails to teach: wherein the error correction code block is configured to omit the check operation based on the error level being uncorrectable in the next error correction operation. However, Ditty teaches: wherein the error correction code block is configured to omit the check operation based on the error level being uncorrectable in the next error correction operation. (0171, Other arrangements and elements (e.g., machines, interfaces, functions, orders, groupings of functions, etc.) may be used in addition to or instead of those shown, and some elements may be omitted altogether.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus and methods that provide low uncorrectable bit error rates of Northcott with the teaching of Ditty, which teaches a system operating based on risk level in order improve reliability and efficiency. (Ditty: 0028, To avoid at least some of the latency and expense;) In regards to claim 3, Northcott in view of Ditty teaches the storage device of claim 1. Northcott teaches: wherein the error correction code block is configured to, based on the error level being correctable in the next error correction operation, perform a store operation that stores the third data in the internal buffer. (19 & 201, If the primary decode process alone is sufficient to correct the data with high confidence, the operation is complete. the journaling engine temporarily stores the allocation block in the current page stripe buffer 1413;) In regards to claim 4, Northcott in view of Ditty teaches the storage device of claim 3. Northcott teaches: wherein the check operation and the store operation are performed in parallel. (66, various stages can be implemented in a pipelined fashion and/or performed in parallel.) In regards to claim 5, Northcott in view of Ditty teaches the storage device of claim 1. Northcott teaches: wherein the error correction code block is configured to, based on an error being detected in the check operation, perform the error correction operation and the estimation operation on the third data. (130, the primary LDPC decoder adjusts error likelihood estimations (LLRs) to reflect the outcome of the grid decoding, setting higher confidence on bits which were part of successfully corrected by the grid decoder, and lower confidence on those which were part of uncorrectable grid codewords.) In regards to claim 7, Northcott in view of Ditty teaches the storage device of claim 1. Northcott fails to teach: wherein the error correction code block is configured to trigger an early termination signal based on the error level being correctable in the next error correction operation. However, Ditty teaches: wherein the error correction code block is configured to trigger an early termination signal based on the error level being correctable in the next error correction operation. (0081, The processor 150 may notify the processor 140 that the fault has been cleared from the particular SoC fault aggregator. Then, the method 540 terminates.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus and methods that provide low uncorrectable bit error rates of Northcott with the teaching of Ditty, which teaches a system operating based on risk level in order improve reliability and efficiency. (Ditty: 0028, To avoid at least some of the latency and expense;) In regards to claim 12, Northcott in view of Ditty teaches the storage device of claim 11. Northcott teaches: wherein the first error correction operation is a last performed error correction operation, and wherein the second error correction operation is an error correction operation performed immediately before the first error correction operation or an error correction operation performed for the first time. (162, After error correction, in a stage 908, the process de-interleaves the data to the format used for primary decode in a manner similar to that of the stage 813 (FIG. 8). The process flow returns from the stage 908 to the stage 903.) In regards to claim 13, Northcott in view of Ditty teaches the storage device of claim 1. Northcott teaches: wherein the estimation operation is performed based on the number of bits converged in the third data. (68, each lane is an 8-bit wide open NAND flash interface (ONFI) bus or a TOGGLE bus. The distribution of data can be done a variety of ways) In regards to claim 14, Northcott in view of Ditty teaches the storage device of claim 1. Northcott teaches: wherein the error correction code block is configured to, based on the number of bits converged in the error correction operation being greater than a third threshold value, estimate that the error level is correctable in the next error correction operation. (68, each lane is an 8-bit wide open NAND flash interface (ONFI) bus or a TOGGLE bus. The distribution of data can be done a variety of ways) In regards to claim 15, Northcott in view of Ditty teaches the storage device of claim 1. Northcott teaches: wherein the error correction code block is configured to perform low density parity check (LDPC) decoding, and wherein the error correction operation corresponds to one loop of the LDPC decoding. (30 The tertiary error correction is preferably an erasure code such as RS or LDPC, capable of rebuilding data lost when a page of the page grid becomes unreadable.) In regards to claim 16, Northcott in view of Ditty teaches the storage device of claim 15. Northcott fails to teach: wherein the error correction code block is configured to perform min-sum decoding, and wherein the estimation operation is performed based on at least one of minimum values or sum values of the min-sum decoding. However, Ditty teaches: wherein the error correction code block is configured to perform min-sum decoding, and wherein the estimation operation is performed based on at least one of minimum values or sum values of the min-sum decoding. (0013, FIG. 6A illustrates an example signal timing diagram for signals received and sent by the processor of the safety island after a low severity uncorrected error (e.g., the minimum value) has been asserted.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus and methods that provide low uncorrectable bit error rates of Northcott with the teaching of Ditty, which teaches a system operating based on risk level in order improve reliability and efficiency. (Ditty: 0028, To avoid at least some of the latency and expense;) In regards to claim 17, Northcott in view of Ditty teaches the storage device of claim 1. Northcott teaches: wherein the error correction code block is configured to, based on the first data being single level cell (SLC) data, perform the check operation after the error correction operation is performed up to a fourth threshold value. (5 & 22, A memory cell in flash memory can be a single-level cell (SLC), which encodes one bit of information per cell;) In regards to claim 18, Northcott in view of Ditty teaches the storage device of claim 17. Northcott teaches: wherein the error correction code block is configured to, based on the first data being single level cell (SLC) data, perform the check operation without the estimation operation after the error correction operation is performed up to the fourth threshold value. (5 & 22, A memory cell in flash memory can be a single-level cell (SLC), which encodes one bit of information per cell;) In regards to claim 19, Northcott teaches: An operating method of a storage device that includes a nonvolatile memory device and a memory controller, the method comprising: reading, at the memory controller, first data from the nonvolatile memory device; (210, When performing a read, the flash stripe controller 1312 retrieves the corresponding data and reassembles a page of data.) performing, at the memory controller, an error estimation operation on the second data; based on an error level estimated in the error correction operation being uncorrectable in a next error correction operation, (19 & 130 an SSD memory controller or a flash drive controller with one or more of the following features: (1) translation of logical or virtual addresses and real addresses via a journaling file system or flash translation layer to reduce the number of program/erase cycles to the memory cells (see FIG. 12); (2) selection of a strength of error correction coding based on a raw bit error rate (see FIG. 11); (3) provision of one or more additional error correction codes so that lower latency reads for small numbers of errors are possible as well additional error correction for larger numbers of errors (see FIGS. 8 and 9); and/or (4) rebuilding of an entire failed page from redundant data (see FIG. 10). Each of these features will be described in more detail in the following. The primary LDPC decoder adjusts error likelihood estimations (LLRs) to reflect the outcome of the grid decoding, setting higher confidence on bits which were part of successfully corrected by the grid decoder, and lower confidence on those which were part of uncorrectable grid codewords.) Northcott fails to teach: performing, at the memory controller, an error correction operation on the first data to generate second data; performing, at the memory controller, the next error correction operation and the error estimation operation; and based on the error level being correctable in the next error correction operation, performing, at the memory controller, the next error correction operation and an integrity estimation operation on the second data. However, Ditty teaches: performing, at the memory controller, an error correction operation on the first data to generate second data; (0119, the error detection block 272 may include other types of code generation circuitry that generates different types of error detection codes, such as error correction code (“ECC”)) performing, at the memory controller, the next error correction operation and the error estimation operation; and based on the error level being correctable in the next error correction operation, performing, at the memory controller, the next error correction operation and an integrity estimation operation on the second data. (0219, 0143, & 0148, the system may set a threshold value for the confidence and consider only the detections exceeding the threshold value as true positive detections; The SI 110 passes the read data through the error detection block 272, which determines a check code for the read data and compares the error detection code with the check code. In block 916, the error detection block 272 determines a check code for each of the error detection code(s) obtained in block 914;) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus and methods that provide low uncorrectable bit error rates of Northcott with the teaching of Ditty, which teaches a system operating based on risk level in order improve reliability and efficiency. (Ditty: 0028, To avoid at least some of the latency and expense;) In regards to claim 20, Northcott teaches: A memory system comprising: a nonvolatile memory device; and a memory controller configured to control the nonvolatile memory device, wherein the memory controller includes: an internal buffer configured to store first data read from the nonvolatile memory device; (210 & 71, When performing a read, the flash stripe controller 1312 retrieves the corresponding data and reassembles a page of data. data can be accumulated in a data buffer in the controller prior to any write commands being issued) and an error correction code block configured to read the first data from the internal buffer, correct an error of the first data, perform an error correction operation that performs an error correction loop for the first data, (149, In the stage 813, the process de-interleaves the secondary codewords and returns the corrected data to the format or order used for decode of the primary ECC. The process returns to the stage 808 to continue iteration of the loop.) perform an estimation operation that estimates an error level of second data, the second data being obtained as an execution result of the error correction loop for the first data, (130, the primary LDPC decoder adjusts error likelihood estimations (LLRs) to reflect the outcome of the grid decoding, setting higher confidence on bits which were part of successfully corrected by the grid decoder, and lower confidence on those which were part of uncorrectable grid codewords.) Northcott fails to teach: based on the error level estimated in the estimation operation being uncorrectable in a next error correction operation, perform the next error correction operation and the estimation operation, based on the error level being correctable in the next error correction operation, perform the next error correction operation, and perform a check operation that checks integrity of third data used in the next error correction operation, based on the error level being uncorrectable in the next error correction operation, omit the check operation, and based on an error being detected in the check operation, perform the error correction operation and the estimation operation on the third data. However, Ditty teaches: based on the error level estimated in the estimation operation being uncorrectable in a next error correction operation, perform the next error correction operation and the estimation operation, based on the error level being correctable in the next error correction operation, perform the next error correction operation, and perform a check operation that checks integrity of third data used in the next error correction operation, (0219, 0143, & 0148, the system may set a threshold value for the confidence and consider only the detections exceeding the threshold value as true positive detections; The SI 110 passes the read data through the error detection block 272, which determines a check code for the read data and compares the error detection code with the check code. In block 916, the error detection block 272 determines a check code for each of the error detection code(s) obtained in block 914;) based on the error level being uncorrectable in the next error correction operation, omit the check operation, and based on an error being detected in the check operation, perform the error correction operation and the estimation operation on the third data (0171, Other arrangements and elements (e.g., machines, interfaces, functions, orders, groupings of functions, etc.) may be used in addition to or instead of those shown, and some elements may be omitted altogether.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus and methods that provide low uncorrectable bit error rates of Northcott with the teaching of Ditty, which teaches a system operating based on risk level in order improve reliability and efficiency. (Ditty: 0028, To avoid at least some of the latency and expense;) Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 6 & 8 - 11 are rejected under 35 U.S.C. 103 as being unpatentable over Northcott (US 9183085 B1) in view of Ditty (US 2023/0036130 A1) in view of Lee (KR 102387463 B1) . In regards to claim 6, Northcott in view of Ditty teaches the storage device of claim 1. Northcott in view of Ditty fails to teach: wherein the error correction code block is configured to delete the third data based on an error being not detected in the check operation. However, Ditty teaches: wherein the error correction code block is configured to delete the third data based on an error being not detected in the check operation. (Fig 13. and corresponding specification, the nonvolatile memory 1460 may perform an operation indicated by a command on a memory cell selected by an address. In an embodiment, the command may be a program command, a read command, or an erase command as an input/output command, and an operation indicated by the command (or an operation corresponding to the command) ;) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus and methods that provide low uncorrectable bit error rates of Northcott with the teaching of Lee, which teaches a memory device performing commands from host in order improve reliability and efficiency. (Lee: Background-Art, checking and correcting a response to an error of a semiconductor memory device at low cost.) In regards to claim 8, Northcott in view of Ditty teaches the storage device of claim 1. Northcott in view of Ditty fails to teach: wherein the estimation operation is performed based on a syndrome weight. However, Ditty teaches: wherein the estimation operation is performed based on a syndrome weight. (Fig 1. and corresponding specification, The ECC decoder 122 may generate syndrome data using the output data transferred from the volatile memory 110 . In addition, the ECC decoder 122 may calculate a position of a bad cell among memory cells included in the volatile memory 110 , that is, an error bit position by using the syndrome data.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus and methods that provide low uncorrectable bit error rates of Northcott with the teaching of Lee, which teaches a memory device performing commands from host in order improve reliability and efficiency. (Lee: Background-Art, checking and correcting a response to an error of a semiconductor memory device at low cost.) In regards to claim 9, Northcott in view of Ditty teaches the storage device of claim 8. Northcott in view of Ditty fails to teach: wherein the error correction code block is configured to, based on the syndrome weight being equal to or smaller than a first threshold value, estimate that the error level is correctable in the next error correction operation. However, Ditty teaches: wherein the error correction code block is configured to, based on the syndrome weight being equal to or smaller than a first threshold value, estimate that the error level is correctable in the next error correction operation. (Fig 1. and corresponding specification, The syndrome generator 620 may receive 128-bit data [0:127] and parity bits PARITY BIT [0:7] and generate syndrome data using an XOR array operation. The coefficient calculator 630 may calculate the coefficient of the error location equation by using the syndrome data.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus and methods that provide low uncorrectable bit error rates of Northcott with the teaching of Lee, which teaches a memory device performing commands from host in order improve reliability and efficiency. (Lee: Background-Art, checking and correcting a response to an error of a semiconductor memory device at low cost.) In regards to claim 10, Northcott in view of Ditty teaches the storage device of claim 8. Northcott in view of Ditty fails to teach: wherein the estimation operation is performed based on the number of bits inverted in the third data. However, Ditty teaches: wherein the estimation operation is performed based on the number of bits inverted in the third data. (Figs. 9C & 11C and corresponding specification, The hint data applicator 610 may perform an XOR operation on the codeword (Codeword [0:135]) and the hint data (HD [0:135]). In this case, the bit values of the codewords Codeword [0:135] for the 6th bit line BL 6 and the 71st bit line BL 71 are inverted.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus and methods that provide low uncorrectable bit error rates of Northcott with the teaching of Lee, which teaches a memory device performing commands from host in order improve reliability and efficiency. (Lee: Background-Art, checking and correcting a response to an error of a semiconductor memory device at low cost.) In regards to claim 11, Northcott in view of Ditty teaches the storage device of claim 10. Northcott in view of Ditty fails to teach: wherein the error correction code block is configured to, based on a count corresponding to a difference between the number of bits inverted in a first error correction operation and the number of bits inverted in a second error correction operation being greater than a second threshold value, estimate that the error level is correctable in the next error correction operation. However, Ditty teaches: wherein the error correction code block is configured to, based on a count corresponding to a difference between the number of bits inverted in a first error correction operation and the number of bits inverted in a second error correction operation being greater than a second threshold value, estimate that the error level is correctable in the next error correction operation. (Figs. 9C & 11C and corresponding specification, The hint data applicator 610 may perform an XOR operation on the codeword (Codeword [0:135]) and the hint data (HD [0:135]). In this case, the bit values of the codewords Codeword [0:135] for the 6th bit line BL 6 and the 71st bit line BL 71 are inverted.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus and methods that provide low uncorrectable bit error rates of Northcott with the teaching of Lee, which teaches a memory device performing commands from host in order improve reliability and efficiency. (Lee: Background-Art, checking and correcting a response to an error of a semiconductor memory device at low cost.) Prior Art Made of Record The prior art mode of record and not relied upon is considered pertinent to Applicant’s disclosure: Jang (US 2022/0365847 A1): The controller (1000) has an error estimation circuit (100) configured to receive a set of data, to estimate an error level of the set of data, and to generate error information. A decision circuit (120) receives the set of data, performs first operation i.e. logical operation, on the set of data, and generates decision data. An error correction circuit (140) receives the decision data, corrects an error on the decision data, and generates error correction data. A selection circuit (160) selects data among the decision data and the error correction data, where the error information comprise a first value when the error estimation circuit estimates the error level of the set of data to be equal to or greater than a first level, and the error information comprises a second value when the error estimation circuit estimates the error level of the set of data to be less than the first level. Northcott (US 9053012 B1): Apparatus and methods provide relatively low uncorrectable bit error rates, low write amplification, long life, fast and efficient retrieval, and efficient storage density such that a solid-state drive (SSD) can be reliably implemented using various types of memory cells, including relatively inexpensive multi-level cell flash. One embodiment intelligently coordinates remapping of bad blocks with error correction code control, which eliminates the tables used to avoid bad blocks. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR PERRY whose telephone number is (571)272-6319. The examiner can normally be reached Monday - Friday 8:00 - 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached on (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /V.P./Examiner, Art Unit 2111 /GUERRIER MERANT/ Primary Examiner, Art Unit 2111 6/11/2026 Application/Control Number: 19/047,257 Page 2 Art Unit: 2111 Application/Control Number: 19/047,257 Page 3 Art Unit: 2111 Application/Control Number: 19/047,257 Page 4 Art Unit: 2111 Application/Control Number: 19/047,257 Page 5 Art Unit: 2111 Application/Control Number: 19/047,257 Page 6 Art Unit: 2111 Application/Control Number: 19/047,257 Page 7 Art Unit: 2111 Application/Control Number: 19/047,257 Page 8 Art Unit: 2111 Application/Control Number: 19/047,257 Page 9 Art Unit: 2111 Application/Control Number: 19/047,257 Page 10 Art Unit: 2111 Application/Control Number: 19/047,257 Page 11 Art Unit: 2111 Application/Control Number: 19/047,257 Page 12 Art Unit: 2111 Application/Control Number: 19/047,257 Page 13 Art Unit: 2111 Application/Control Number: 19/047,257 Page 14 Art Unit: 2111 Application/Control Number: 19/047,257 Page 15 Art Unit: 2111 Application/Control Number: 19/047,257 Page 16 Art Unit: 2111 Application/Control Number: 19/047,257 Page 17 Art Unit: 2111
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