Prosecution Insights
Last updated: August 06, 2026
Application No. 19/047,761

ZERO CURRENT DETECTOR

Non-Final OA §102§103
Filed
Feb 07, 2025
Priority
Feb 07, 2024 — FR 24/01211
Examiner
MCANDREW, CHRISTOPHER P
Art Unit
Tech Center
Assignee
Dolphin Semiconductor
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
9m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
843 granted / 981 resolved
+25.9% vs TC avg
Moderate +14% lift
Without
With
+13.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
28 currently pending
Career history
1000
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
50.4%
+10.4% vs TC avg
§102
28.4%
-11.6% vs TC avg
§112
15.9%
-24.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 981 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2 & 5-8 are rejected under 35 U.S.C. 102(a)(1) & (a)(2) as being anticipated by Xu (U.S. PGPub # 2016/0322900). Regarding Independent claim 1, Xu teaches: A zero current detection circuit (Title, Abstract, & paragraphs 0002, 0006-0008.) comprising: a first comparator (Fig 1 Element 103. Paragraph 0024.) configured to compare a first voltage (Fig 1 Elements 103 & IL. Paragraph 0024.), representative of a first current (Fig 1 Elements 103 & IL. Paragraph 0024.), with a first threshold voltage (Fig 1 Elements 103 & Voffset. Paragraphs 0024.); and a calibration circuit (Fig. 1 Elements 101 & 102. See paragraphs 0022-0025.) configured to modify the value of the first threshold voltage in view of process (Fig. 1 Elements 101 & 102. See paragraphs 0022-0025.), voltage (Fig. 1 Elements 101 & 102. See paragraphs 0022-0025.), and/or temperature variations. PNG media_image1.png 292 458 media_image1.png Greyscale Regarding claim 2, Xu teaches all elements of claim 1, upon which this claim depends. Xu teaches said first threshold voltage is an offset voltage of said first comparator (See Fig. 4 See paragraphs 0023-0025, 0027-0029, & 0031-0032.). PNG media_image2.png 308 472 media_image2.png Greyscale Regarding claim 5, Xu teaches all elements of claim 1, upon which this claim depends. Xu teaches a logic circuit configured to be the main control circuit of the zero current detection circuit (Fig. 1 Element 204, the logic circuit. Fig. 4 Element 204, the logic circuit. Paragraphs 0022, 0024-0025, 0027, 0029, & 0032-0033 wherein the logic circuits are disclosed.). Regarding claim 6, Xu teaches all elements of claim 1, upon which this claim depends. Xu teaches a DC-DC converter comprising a zero current detection circuit according to claim 1 (Paragraphs 0003, 0022, & 0050 wherein the disclosed Buck convertor is a DC-DC converter.). Regarding claim 7, Xu teaches all elements of claim 6, upon which this claim depends. Xu teaches two switches coupled in series, and a coil having one of its terminals coupled to the middle node between said two switches (Fig. 5 Elements M1, M2, SW, & L1.). PNG media_image3.png 442 724 media_image3.png Greyscale Regarding claim 8, Xu teaches all elements of claim 7, upon which this claim depends. Xu teaches said zero current detection circuit is configured to detect when the current in said coil is equal to zero (Title, Abstract, & Paragraphs 0003, 0006, 0008, 0024, & elsewhere.). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Xu (U.S. PGPub # 2016/0322900) in view of Chen et al (U.S. PGPub # 2014/0111168). Regarding claim 3, Xu teaches all elements of claim 1, upon which this claim depends. Xu does not explicitly teach said calibration circuit comprises a second comparator circuit. Chen teaches said calibration circuit comprises a second comparator circuit (Fig. 7 Element 213, the CMP, and comparator 215. See paragraphs 0022-0026.). PNG media_image4.png 492 666 media_image4.png Greyscale It would have been obvious to one of ordinary skill in the art before the effective time of filing to apply the teachings of Chen to the teachings of Xu such that said calibration circuit comprises a second comparator circuit because this would allow one to better control the functioning of the down bridge transistor. Regarding claim 4, Xu teaches all elements of claim 1, upon which this claim depends. Xu does not explicitly teach said second comparator circuit is more precise than the first comparator. Chen teaches said second comparator circuit is more precise than the first comparator (Fig. 7 Element 213 in relation to 215. See paragraphs 0022-0026.). It would have been obvious to one of ordinary skill in the art before the effective time of filing to apply the teachings of Chen to the teachings of Xu such that said second comparator circuit is more precise than the first comparator because this would allow one to better control the functioning of the down bridge transistor. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art listed but not cited represents the previous state of the art and analogous art that teaches some of the limitations claimed by applicant. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER P MCANDREW whose telephone number is (469)295-9025. The examiner can normally be reached Monday-Thursday 6-4:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached on 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER P MCANDREW/Primary Examiner, Art Unit 2858
Read full office action

Prosecution Timeline

Feb 07, 2025
Application Filed
Jul 16, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
99%
With Interview (+13.9%)
2y 3m (~9m remaining)
Median Time to Grant
Low
PTA Risk
Based on 981 resolved cases by this examiner. Grant probability derived from career allowance rate.

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