Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3, 8, 10, 11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lohr et al. (United States Patent Application Publication US 2007/0115600), hereinafter Lohr.
Regarding claim 1, Lohr teaches a circuit for controlling voltage overshoot in a computing system, comprising: a network of shunt devices arranged into a plurality of branches ([0031] “Clap circuit 608A provides protection for signal pad 606A and application circuitry…Clamp circuits 608B and 608C each protect application circuitry coupled to signal pads 606B and 606C, respectively, to guard against damage from EOS conditions.”), wherein each branch of the plurality of branches includes one or more shunt devices connected to an enable pin associated with the branch ([0032] “clamp actuator comparators 610A, 610B, and 610C are coupled to associated clamp circuits 608A, 608B, and 608C, respectively, to guard against damage from EOS conditions while application circuit 600 is powered on.” [0037] “Clamp circuit 106 may be an exemplary grounded gate NMOS device as may currently be applied to protect application circuitry from damage due to electrostatic discharge (ESD) currents.”),
wherein each shunt device of the one or more shunt devices is configured to, when the shunt device is activated, induce current through a transistor connected between a power node and a ground node of the computing system ([0035] “Clamp circuit 106 is actuated while the application circuit 110 is powered off to shunt any damaging current from an EOS condition to the current sink of ground signal path 152.”); and
a controller connected to a plurality of enable pins corresponding to the plurality of branches of the network of shunt devices, the controller being configured to: receive a computing processor voltage of a computing processor of the computing system; generate a difference value that indicates a difference between the computing processor voltage and a reference voltage ([0032] “In general, each clamp actuator comparator circuit 610A-610C is operable to actuate its associated clamp circuit 608A-608C, respectively, in response to sensing or detecting that the external voltage level applied to the corresponding signal pads 606A-606C exceeds the corresponding reference voltage level supplied by a reference voltage source 612.” A voltage level applied to signal pads are sensed. Then, the sensed voltage is compared to a reference voltage. By comparing the sensed voltage and the reference voltage, the difference is determined.); and
send one or more enable signals to one or more enable pins of one or more branches of the plurality of branches of the network of shunt devices to activate the shunt devices in the one or more branches based at least on the difference value indicating that the computing processor voltage is greater than the reference voltage ([0040] “the reference voltage level so generated and applied to path 156 may be received as an input to a comparator clamp actuator circuit configured to actuate an associated clamp circuit in response to sensing an EOS condition as exceeding the threshold voltage level of the reference voltage applied to path 156.” When the sensed voltage exceeds the reference voltage, which also determines the difference between the sensed voltage and the reference voltage, clamping circuit is enabled. A pin is a metal contact point to transfer electrical signals between components. Thus, the signals or commands between components to control the clamping circuits are sent to pins of the clamping circuits.).
Regarding claim 2, Lohr teach wherein a number of enable signals that are sent by the controller to activate a corresponding number of branches of shunt devices of the network of shunt devices is based at least on a magnitude of the difference value ([0032] “In general, each clamp actuator comparator circuit 610A-610C is operable to actuate its associated clamp circuit 608A-608C, respectively, in response to sensing or detecting that the external voltage level applied to the corresponding signal pads 606A-606C exceeds the corresponding reference voltage level supplied by a reference voltage source 612.” [0033] “reference voltage source 612 may provide distinct reference voltage level signals appropriate for each clamp actuator comparator circuit 610A-610C. Further, reference voltage source 612 may provide multiple distinct reference voltage level signals by utilizing multiple charge pump circuits coupled to a common bandgap reference source as discussed in further detail herein below.”).
Regarding claim 3, Lohr teaches wherein a number of branches of the network of shunt devices and a number of shunt devices per branch are based at least on a voltage tolerance range of components of the computing processor ([0005] “A particular problem known as "latch up" arises in EOS conditions in CMOS electronic circuits due to the nature of CMOS circuit designs. In general, dynamic latch up of a CMOS device may occur when a device is subjected to a "spike" (an EOS condition) on its Vdd power supply signal while the device is operating. Such a latch up condition of a CMOS device often renders the device unusable.” [0032] “In general, each clamp actuator comparator circuit 610A-610C is operable to actuate its associated clamp circuit 608A-608C, respectively, in response to sensing or detecting that the external voltage level applied to the corresponding signal pads 606A-606C exceeds the corresponding reference voltage level supplied by a reference voltage source 612.” [0033] “reference voltage source 612 may provide distinct reference voltage level signals appropriate for each clamp actuator comparator circuit 610A-610C. Further, reference voltage source 612 may provide multiple distinct reference voltage level signals by utilizing multiple charge pump circuits coupled to a common bandgap reference source as discussed in further detail herein below.”).
Regarding claim 8, Lohr teaches wherein the controller is configured to: receive an updated computing processor voltage; generate an updated voltage difference value that indicates a difference between the updated computing processor voltage and the reference voltage; based at least on the updated computing processor voltage being greater than the reference voltage and the updated difference value being less than the difference value, send one or more disable signals to one or more enable pins of one or more branches of the plurality of branches of the network of shunt devices to deactivate the shunt devices one by one in the corresponding branch ([0032] “In general, each clamp actuator comparator circuit 610A-610C is operable to actuate its associated clamp circuit 608A-608C, respectively, in response to sensing or detecting that the external voltage level applied to the corresponding signal pads 606A-606C exceeds the corresponding reference voltage level supplied by a reference voltage source 612.” [0036] “Comparator circuit 104 receives the present signal voltage level on path 150 and compares that signal voltage level to a reference voltage level signal on path 156 generated by reference voltage source 102.” Since the comparator circuit actuates clamp circuit by generating a signal only when the voltage level exceeds the reference voltage, when the voltage does not exceed the reference voltage, the comparator does not generate the signal to actuate the clamping circuit. Furthermore, since each of the clamping circuit is individually controlled, each of the clamping circuit is deactivated when corresponding comparator circuit does not generate the signal to actuate the clamping circuit.); and
based at least on the updated computing processor voltage being greater than the reference voltage and the updated difference value being greater than the difference value, send one or more enable signals to one or more additional enable pins of one or more additional branches of the plurality of branches of the network of shunt devices to activate additional shunt devices in the corresponding one or more additional branches ([0032] “In general, each clamp actuator comparator circuit 610A-610C is operable to actuate its associated clamp circuit 608A-608C, respectively, in response to sensing or detecting that the external voltage level applied to the corresponding signal pads 606A-606C exceeds the corresponding reference voltage level supplied by a reference voltage source 612.” [0038] “features and aspects hereof provide actuation of the clamp circuit 106 in response to sensing an EOS condition while the application circuit utilizing the clamp circuit is powered on.” Since each comparator circuit control the associated clamp circuit when the “detecting that the external voltage level applied to the corresponding signal pads 606A-606C exceeds the corresponding reference voltage level supplied by a reference voltage source 612,” each of the clamping circuits is individually controlled to be actuated for additional EOS conditions.).
Regarding claim 10, Lohr further teaches wherein shunt devices of the network of shunt devices are connected at regular distances throughout the computing processor to induce currents across different regions of the computing processor when activated (FIG. 6 “CLAMP 608A-C” “CLAMP ACUTATOR COMPARATOR 610A-C” “REFERENCE VOLTAGE SOURCE 612”).
Regarding claim 11, Lohr further teaches wherein the network of shunt devices is integrated into a same integrated circuit as the computing processor (ABSTRACT “apparatus is provided that integrates with the application circuit that utilizes an existing clamp circuit to guard against EOS conditions” FIG. 6 “FIG. 6 APPLICATION CIRCUIT 600” “CLAMP 608A-C” “CLAMP ACUTATOR COMPARATOR 610A-C” “REFERENCE VOLTAGE SOURCE 612”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12-14, 16-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lohr in view of Ahmed et al. (United States Patent Application Publication US 2021/0271277), hereinafter Ahmed.
Regarding claim 12, Lohr teaches all the limitations, as discussed above.
Lohr further teaches wherein the network of shunt devices is connected to a plurality of connection points on the first integrated circuit (FIG. 6 “FIG. 6 APPLICATION CIRCUIT 600” “CLAMP 608A-C” “CLAMP ACUTATOR COMPARATOR 610A-C” “REFERENCE VOLTAGE SOURCE 612”).
However, Lohr does not teach wherein the computing processor is positioned on a first integrated circuit, and wherein the network of shunt devices is positioned on a second integrated circuit that is separate from the first integrated circuit.
Ahmed teaches wherein the computing processor is positioned on a first integrated circuit (FIG. 3A, FIG. 3C “Processor or load 306”), and wherein the network of shunt devices is positioned on a second integrated circuit that is separate from the first integrated circuit (FIG. 3A, “301, 302”, FIG. 3C “Power gate 305” As shown in FIG. 3A and 3B, the processor are separated from the power gates and CDLDO.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Lohr by incorporating the teaching of Ahmed of wherein the computing processor is positioned on a first integrated circuit, and wherein the network of shunt devices is positioned on a second integrated circuit that is separate from the first integrated circuit. They are all directed toward protecting circuits from over voltage. As well known in the art before the effective filing date of the claimed invention, having electrical components positioned in two separate ICs is well known method. Furthermore, by positioning devices in separated ICs, when a failure or damage to one IC occurs, the other IC can be protected. Therefore, it would be advantageous to incorporate the teaching of Ahmed of wherein the computing processor is positioned on a first integrated circuit, and wherein the network of shunt devices is positioned on a second integrated circuit that is separate from the first integrated circuit in order to improve the overall protection of the system.
Regarding claim 14, Lohr teaches a network of shunt devices arranged into a plurality of branches, wherein each branch of the plurality of branches includes a plurality of shunt devices connected to an enable pin associated with the branch ([0031] “Clap circuit 608A provides protection for signal pad 606A and application circuitry…Clamp circuits 608B and 608C each protect application circuitry coupled to signal pads 606B and 606C, respectively, to guard against damage from EOS conditions.”),
wherein the plurality of shunt device in the branch of the plurality of branches is configured to deactivate one by one in a cascade along the branch based at least on a disable signal being sent to the enable pin for the branch ([0032] “clamp actuator comparators 610A, 610B, and 610C are coupled to associated clamp circuits 608A, 608B, and 608C, respectively, to guard against damage from EOS conditions while application circuit 600 is powered on.” [0037] “Clamp circuit 106 may be an exemplary grounded gate NMOS device as may currently be applied to protect application circuitry from damage due to electrostatic discharge (ESD) currents.”),
wherein each shunt device of the plurality of shunt devices is configured to, when the shunt device is activated, induce current through a transistor connected between a power node and a ground node of the computing system ([0035] “Clamp circuit 106 is actuated while the application circuit 110 is powered off to shunt any damaging current from an EOS condition to the current sink of ground signal path 152.”); and
a controller connected to a plurality of enable pins corresponding to the plurality of branches of the network of shunt devices, the controller being configured to: receive a computing processor voltage of a computing processor of the computing system; generate a difference value that indicates a difference between the computing processor voltage and a reference voltage ([0032] “In general, each clamp actuator comparator circuit 610A-610C is operable to actuate its associated clamp circuit 608A-608C, respectively, in response to sensing or detecting that the external voltage level applied to the corresponding signal pads 606A-606C exceeds the corresponding reference voltage level supplied by a reference voltage source 612.” A voltage level applied to signal pads are sensed. Then, the sensed voltage is compared to a reference voltage. By comparing the sensed voltage and the reference voltage, the difference is determined.); and send one or more enable signals to one or more enable pins of one or more branches of the plurality of branches of the network of shunt devices to activate the shunt devices in the one or more branches based at least on the difference value indicating that the computing processor voltage is greater than the reference voltage ([0040] “the reference voltage level so generated and applied to path 156 may be received as an input to a comparator clamp actuator circuit configured to actuate an associated clamp circuit in response to sensing an EOS condition as exceeding the threshold voltage level of the reference voltage applied to path 156.” When the sensed voltage exceeds the reference voltage, which also determines the difference between the sensed voltage and the reference voltage, clamping circuit is enabled. A pin is a metal contact point to transfer electrical signals between components. Thus, the signals or commands between components to control the clamping circuits are sent to pins of the clamping circuits.).
However, Lohr does not teach wherein the plurality of shunt device in a branch of the plurality of branches is configured to activate in unison based at least on an enable signal being sent to the enable pin for the branch.
Ahmed teaches wherein the plurality of shunt device in a branch of the plurality of branches is configured to activate in unison based at least on an enable signal being sent to the enable pin for the branch ([0087] “During a voltage overshoot event, or when the reference voltage suddenly steps down, FSM 333g transitions to the "All OFF" state in which all power gates are turned off.” By turning off all power gates, the over voltage event is prevented. Thus, the turning off all power gates eventually activates the shunting devices to protect the over voltage.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teaching of Lohr of wherein the plurality of shunt device in a branch of the plurality of branches is configured to activate in unison based at least on an enable signal being sent to the enable pin for the branch by incorporating the teaching of Ahmed of wherein the plurality of shunt device in a branch of the plurality of branches is configured to activate in unison based at least on an enable signal being sent to the enable pin for the branch. By activating the shunt devices in unison, the response to a large voltage droop/overshoot can be faster. Therefore, it would be advantageous to incorporate the teaching of Ahmed of wherein the plurality of shunt device in a branch of the plurality of branches is configured to activate in unison based at least on an enable signal being sent to the enable pin for the branch in order to improve performance.
Regarding claim 16, Lohr in view of Ahmed teaches all the limitations of the circuit of claim 14, as discussed above.
Ahmed further teaches wherein the shunt device further includes a supplemental resistor connected in series with the transistor ([0063] “The voltage on Vout is sampled via a resistive divider R1 and R2 (e.g., 0.75x gain) of voltage divider 332 and fed into ADC 307.”).
Regarding claim 17, Lohr in view of Ahmed teaches all the limitations of the circuit of claim 14, as discussed above.
Ahmed further teaches wherein, for a first shunt device in each branch of the plurality of branches of the network of shunt devices, the second input pin of the shunt device is connected to the enable pin, wherein the output pin of the first shunt device is connected to a second input pin of a next shunt device in the branch, and wherein each output pin of each shunt device in the branch other than the first shunt device is connected to a second input pin of a next shunt device in the branch ([0052] “PG 305 comprises a plurality of power gates (e.g., 0 though n, where 'n' is an integer) coupled in parallel. The power gates comprises p-type transistors MP0 to MPn.”).
Regarding claim 18, Lohr in view of Ahmed teaches all the limitations of the circuit of claim 14, as discussed above.
Lohr, as modified above, further teaches wherein the controller is configured to: receive an updated computing processor voltage; generate an updated voltage difference value that indicates a difference between the updated computing processor voltage and the reference voltage; based at least on the updated computing processor voltage being greater than the reference voltage and the updated difference value being less than the difference value, send one or more disable signals to one or more enable pins of one or more branches of the plurality of branches of the network of shunt devices to deactivate the shunt devices one by one in the corresponding branch ([0032] “In general, each clamp actuator comparator circuit 610A-610C is operable to actuate its associated clamp circuit 608A-608C, respectively, in response to sensing or detecting that the external voltage level applied to the corresponding signal pads 606A-606C exceeds the corresponding reference voltage level supplied by a reference voltage source 612.” [0036] “Comparator circuit 104 receives the present signal voltage level on path 150 and compares that signal voltage level to a reference voltage level signal on path 156 generated by reference voltage source 102.” Since the comparator circuit actuates clamp circuit by generating a signal only when the voltage level exceeds the reference voltage, when the voltage does not exceed the reference voltage, the comparator does not generate the signal to actuate the clamping circuit. Furthermore, since each of the clamping circuit is individually controlled, each of the clamping circuit is deactivated when corresponding comparator circuit does not generate the signal to actuate the clamping circuit.); and
based at least on the updated computing processor voltage being greater than the reference voltage and the updated difference value being greater than the difference value, send one or more enable signals to one or more additional enable pins of one or more additional branches of the plurality of branches of the network of shunt devices to activate additional shunt devices in the corresponding one or more additional branches ([0032] “In general, each clamp actuator comparator circuit 610A-610C is operable to actuate its associated clamp circuit 608A-608C, respectively, in response to sensing or detecting that the external voltage level applied to the corresponding signal pads 606A-606C exceeds the corresponding reference voltage level supplied by a reference voltage source 612.” [0038] “features and aspects hereof provide actuation of the clamp circuit 106 in response to sensing an EOS condition while the application circuit utilizing the clamp circuit is powered on.” Since each comparator circuit control the associated clamp circuit when the “detecting that the external voltage level applied to the corresponding signal pads 606A-606C exceeds the corresponding reference voltage level supplied by a reference voltage source 612,” each of the clamping circuits is individually controlled to be actuated for additional EOS conditions.).
Regarding claim 20, Lohr teaches A circuit for controlling voltage overshoot in a computing system, comprising: a network of shunt devices arranged into a plurality of branches ([0031] “Clap circuit 608A provides protection for signal pad 606A and application circuitry…Clamp circuits 608B and 608C each protect application circuitry coupled to signal pads 606B and 606C, respectively, to guard against damage from EOS conditions.”), wherein each branch of the plurality of branches includes one or more shunt devices connected to an enable pin associated with the branch ([0032] “clamp actuator comparators 610A, 610B, and 610C are coupled to associated clamp circuits 608A, 608B, and 608C, respectively, to guard against damage from EOS conditions while application circuit 600 is powered on.” [0037] “Clamp circuit 106 may be an exemplary grounded gate NMOS device as may currently be applied to protect application circuitry from damage due to electrostatic discharge (ESD) currents.”),
wherein each shunt device of the one or more shunt devices is configured to, when the shunt device is activated, induce current through a transistor connected between a power node and a ground node of the computing system ([0035] “Clamp circuit 106 is actuated while the application circuit 110 is powered off to shunt any damaging current from an EOS condition to the current sink of ground signal path 152.”); and
a controller connected to a plurality of enable pins corresponding to the plurality of branches of the network of shunt devices, the controller being configured to: receive a computing processor voltage of a computing processor of the computing system; generate a difference value that indicates a difference between the computing processor voltage and a reference voltage ([0032] “In general, each clamp actuator comparator circuit 610A-610C is operable to actuate its associated clamp circuit 608A-608C, respectively, in response to sensing or detecting that the external voltage level applied to the corresponding signal pads 606A-606C exceeds the corresponding reference voltage level supplied by a reference voltage source 612.” A voltage level applied to signal pads are sensed. Then, the sensed voltage is compared to a reference voltage. By comparing the sensed voltage and the reference voltage, the difference is determined.).
However, Lohr does not teach wherein the computing processor is configured to have a voltage tolerance range including a maximum tolerance voltage and a minimum tolerance voltage, wherein the computing processor is configured to, during a full load state operate at a lower voltage setpoint that is closer to minimum tolerance voltage than the maximum tolerance voltage, and during a light load state operate at an upper voltage setpoint that is closer to maximum tolerance voltage than the minimum tolerance voltage, and wherein the reference voltage is greater than or equal to the upper setpoint voltage.
Ahmed teaches wherein the computing processor is configured to have a voltage tolerance range including a maximum tolerance voltage and a minimum tolerance voltage (Fig. 1 “V_DRP” “V_OS”), wherein the computing processor is configured to, during a full load state operate at a lower voltage setpoint that is closer to minimum tolerance voltage than the maximum tolerance voltage (FIG. 4A, 4B, 4C, “Droop_Threshold” “Response to large load step --CC”, Fig. 10A. [0056] “digital comparator and the event detector 302g also monitors the output voltage for specific events droop, overshoot, reference transient and startup. Droop event occurs when voltage on Vout drops below a threshold.” The droop event occurs when the voltage on Vout drops below a threshold, which occurs due to a change of the load from a light load to a high or full load state. As shown in FIG. 1, 4A-4C, the voltage drops to low voltage closer to a low droop threshold, which causes malfunctions and errors.), and
during a light load state operate at an upper voltage setpoint that is closer to maximum tolerance voltage than the minimum tolerance voltage, and wherein the reference voltage is greater than or equal to the upper setpoint voltage (Fig. 1 “V_OS” FIG. 7, 8, 10B [0056] “Overshoot event occurs when voltage on Vout suddenly rises above a normal (or target) voltage level.” When the load decreases from a full load to a light load as shown in FIG. 1, the voltage overshoot event occurs, which increases the voltage above a threshold.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teaching of Lohr by incorporating the teaching of Ahmed of wherein the computing processor is configured to have a voltage tolerance range including a maximum tolerance voltage and a minimum tolerance voltage, wherein the computing processor is configured to, during a full load state operate at a lower voltage setpoint that is closer to minimum tolerance voltage than the maximum tolerance voltage, and during a light load state operate at an upper voltage setpoint that is closer to maximum tolerance voltage than the minimum tolerance voltage, and wherein the reference voltage is greater than or equal to the upper setpoint voltage. They are all directed toward protecting circuits from over voltage. As recognized by Ahmed, power management for different “di/dt” event is difficult ([0003]). By having adjusting operating voltage for different “di/dt” events or overshoot/voltage droop, one regulator can protect the device from the overshoot/voltage droop. Therefore, it would be advantageous to incorporate the teaching of Ahmed of wherein the computing processor is configured to have a voltage tolerance range including a maximum tolerance voltage and a minimum tolerance voltage, wherein the computing processor is configured to, during a full load state operate at a lower voltage setpoint that is closer to minimum tolerance voltage than the maximum tolerance voltage, and during a light load state operate at an upper voltage setpoint that is closer to maximum tolerance voltage than the minimum tolerance voltage, and wherein the reference voltage is greater than or equal to the upper setpoint voltage in order to improve the scalability and performance.
Regarding claim 13, Lohr teaches all the limitations of the circuit of claim 1, as discussed above.
Ahmed further teaches wherein the computing processor is configured to have a voltage tolerance range including a maximum tolerance voltage and a minimum tolerance voltage (Fig. 1 “V_DRP” “V_OS”), wherein the computing processor is configured to, during a full load state operate at a lower voltage setpoint that is closer to minimum tolerance voltage than the maximum tolerance voltage (FIG. 4A, 4B, 4C, “Droop_Threshold” “Response to large load step --CC”, Fig. 10A. [0056] “digital comparator and the event detector 302g also monitors the output voltage for specific events droop, overshoot, reference transient and startup. Droop event occurs when voltage on Vout drops below a threshold.” The droop event occurs when the voltage on Vout drops below a threshold, which occurs due to a change of the load from a light load to a high or full load state. As shown in FIG. 1, 4A-4C, the voltage drops to low voltage closer to a low droop threshold, which causes malfunctions and errors.), and
during a light load state operate at an upper voltage setpoint that is closer to maximum tolerance voltage than the minimum tolerance voltage, and wherein the reference voltage is greater than or equal to the upper setpoint voltage (Fig. 1 “V_OS” FIG. 7, 8, 10B [0056] “Overshoot event occurs when voltage on Vout suddenly rises above a normal (or target) voltage level.” When the load decreases from a full load to a light load as shown in FIG. 1, the voltage overshoot event occurs, which increases the voltage above a threshold.).
Allowable Subject Matter
Claims 4-7, 9, 15, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Lohr teaches clamping circuits to guard an application circuit against electrical over-stress condition while the application circuit is powered off and on. However, Lohr does not teach “wherein each shunt device of the network of shunt devices includes a first input pin, a second input pin, and an output pin, wherein the first input pin is connected to an enable pin of a corresponding branch in which the shunt device is arranged, wherein the first input pin is further connected to a first input of a NOR gate, wherein the second input pin is connected to an input of a delay buffer, wherein an output of the delay buffer is connected to a second input of the NOR gate, wherein an output of the NOR gate is connected to a gate of the transistor, and wherein the output pin of the shunt device is electrically connected between the output of the delay buffer and the second input of the NOR gate” “wherein the controller is configured to: execute a timer to wait a designated delay time in between sending each disable signal of the one or more disable signals to deactivate shunt devices in the one or more branches one at a time” “wherein the controller is configured to: execute a timer to wait a designated delay time in between sending each disable signal of the one or more disable signals to deactivate shunt devices in the one or more branches one at a time.”
Ahmed teaches a computational digital low dropout (CDLDO) regulator to adjust power gates when detecting voltage droop events and overshoot events. However, Ahmed does not teach “wherein each shunt device of the network of shunt devices includes a first input pin, a second input pin, and an output pin, wherein the first input pin is connected to an enable pin of a corresponding branch in which the shunt device is arranged, wherein the first input pin is further connected to a first input of a NOR gate, wherein the second input pin is connected to an input of a delay buffer, wherein an output of the delay buffer is connected to a second input of the NOR gate, wherein an output of the NOR gate is connected to a gate of the transistor, and wherein the output pin of the shunt device is electrically connected between the output of the delay buffer and the second input of the NOR gate” “wherein the controller is configured to: execute a timer to wait a designated delay time in between sending each disable signal of the one or more disable signals to deactivate shunt devices in the one or more branches one at a time” “wherein the controller is configured to: execute a timer to wait a designated delay time in between sending each disable signal of the one or more disable signals to deactivate shunt devices in the one or more branches one at a time.”
Uan-Zo-li et al. (United States Patent Application Publication US 2019/0377405) teaches to provide a throttle signal to a processor if the input voltage of the processor droops below a threshold voltage. However, Uan-Zo-li does not teach “wherein each shunt device of the network of shunt devices includes a first input pin, a second input pin, and an output pin, wherein the first input pin is connected to an enable pin of a corresponding branch in which the shunt device is arranged, wherein the first input pin is further connected to a first input of a NOR gate, wherein the second input pin is connected to an input of a delay buffer, wherein an output of the delay buffer is connected to a second input of the NOR gate, wherein an output of the NOR gate is connected to a gate of the transistor, and wherein the output pin of the shunt device is electrically connected between the output of the delay buffer and the second input of the NOR gate” “wherein the controller is configured to: execute a timer to wait a designated delay time in between sending each disable signal of the one or more disable signals to deactivate shunt devices in the one or more branches one at a time” “wherein the controller is configured to: execute a timer to wait a designated delay time in between sending each disable signal of the one or more disable signals to deactivate shunt devices in the one or more branches one at a time.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sekerli et al. (United States Patent Application Publication US 2022/0253082) teaches an electronic circuit comprising an error amplifier and an overshoot and undershoot detection circuit. The overshoot and undershoot detection circuit compares differential input nodes of the output amplifier to a baseline voltage signal and activates the switch circuit when detecting an overshoot condition or an undershoot condition using the baseline voltage signal.
Shibib et al. (United States Patent Application Publication US 2019/0393693) teaches a protection circuit including a first clamping sub-circuit, a first switching sub-circuit and a first resistive sub-circuit coupled in series between a first and second node and also including a second clamping subcircuit, a second switching sub-circuit and a second resistive sub-circuit coupled in series between the second and first nodes.
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