DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The prior art documents submitted by applicant in the Information Disclosure Statements filed on 02/07/2025 have all been considered and made of record with the exception of lined-through references for which a copy of the foreign patent documents with drawings were not filed, a translation of a foreign language references were not provided, or the citations were incorrect (note the attached copies of form PTO-1449).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP §§ 706.02(l)(1) - 706.02(l)(3) for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 21-25 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 1, 2, 6, 1 of U.S. Patent 12254526. This is a nonstatutory double patenting rejection.
Regarding claim 1:
19048323
US 12254526
21. An apparatus comprising:
processor circuitry coupled to a memory associated with cache and processing resources of the processing circuitry,
the processing circuitry to facilitate the memory to communicate sets of data with the cache such that the processing resources to seamlessly perform processing of the sets of data during varying time periods.
1. A graphics multiprocessor, comprising:
a plurality of compute engines to perform first computations to generate a first set of data of a process; cache for storing data; and
a high density memory for temporal buffering that is integrated on a same semiconductor chip with the plurality of compute engines and the cache, the high density memory to receive the first set of data, to temporarily store the first set of data, and to provide the first set of data from the high density memory to the cache during a first time period that is prior to a second time period when the plurality of compute engines request the first set of data for second computations of the process, wherein the plurality of compute engines use the first set of data for second computations to generate a second set of data, wherein the first set of data comprises activation data for a forward pass of the process that will be transferred from the high density memory to the cache prior to when the activation data is needed during a backward pass of the process.
Although the conflicting claims are not identical, they are not patentably distinct from each other (see the comparison between claim 21 of the instant invention and claim 1 of the US 12254526).
Likewise instant dependent claims 22-25 are anticipated by dependent claims 1, 2, 6, 1 of the US 12254526, and is not patentably distinct from claims 1, 2, 6, 1 of the US 12254526.
Claim Objections
Claim 30 is objected to because of the following informalities: “The apparatus of claim 21” should be “The method of claim 26”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21-22, 24-27, 29-32, and 34-35 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. PGPubs 2018/0293701 to Appu et al..
Regarding claim 21, Appu et al. teach an apparatus (abstract, Fig 8, par 0092-0094, “graphics processor 800 includes a graphics pipeline 820, a media pipeline 830, a display engine 840, thread execution logic 850, and a render output pipeline 870”, Fig 28C, par 0242-0245, “The illustrated graphics multiprocessor 2834 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of differing architectures may be included within the processing cluster 2814.”), comprising:
processor circuitry coupled to a memory associated with cache and processing resources of the processing circuitry (par 0075, “thread execution logic 600 includes one or more connections to memory, such as system memory or cache memory, through one or more of instruction cache 606, data port 614, sampler 610, and execution units 608A-608N”, par 0094, “execution units 852A-852B have an attached L1 cache 851 that is specific for each array or shared between the arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions”, par 0246-0248, “the graphics multiprocessor 2834 can forego an internal cache and use a cache memory (e.g., L1 cache 308) within the processing cluster 2814. Each graphics multiprocessor 2834 also has access to L2 caches within the partition units (e.g., partition units 2820A-2820N of FIG. 28) that are shared among all processing clusters 2814 and may be used to transfer data between threads”, par 0126-0129, “FIG. 12 is a block diagram illustrating an exemplary system on a chip integrated circuit 1200 that may be fabricated using one or more IP cores, according to an embodiment … Memory interface may be provided via a memory controller 1265 for access to SDRAM or SRAM memory devices” … a system-on-a-chip (SoC) integrated circuit which include a memory that is integrated on a same semiconductor chip with the plurality of compute engines and the cache (see Figs 12-14, par 0126-0129), par 0232, “The parallel processing unit 2802 can transfer data from system memory via the I/O unit 2804 for processing. During processing the transferred data can be stored to on-chip memory (e.g., parallel processor memory 2822) during processing, then written back to system memory”, par 0246-0248, “The graphics multiprocessor 2834 may also access off-chip global memory, which can include one or more of local parallel processor memory and/or system memory”),
the processing circuitry to facilitate the memory to communicate sets of data with the cache such that the processing resources to seamlessly perform processing of the sets of data during varying time periods (par 0098, “ execution units 852A-852B and associated cache(s) 851, texture and media sampler 854, and texture/sampler cache 858 interconnect via a data port 856 to perform memory access and communicate with render output pipeline components of the processor”, par 0246-0248, “Embodiments in which the processing cluster 2814 includes multiple instances of the graphics multiprocessor 2834 can share common instructions and data, which may be stored in the L1 cache 2908 … a processing cluster 2814 may be configured such that each graphics multiprocessor 2834 is coupled to a texture unit 2836 for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering the texture data. Texture data is read from an internal texture L1 cache (not shown) or in some embodiments from the L1 cache within graphics multiprocessor 2834 and is fetched from an L2 cache, local parallel processor memory, or system memory, as needed. Each graphics multiprocessor 2834 outputs processed tasks to the data crossbar 2840 to provide the processed task to another processing cluster 2814 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via the memory crossbar 2816”, par 0255, “The memory and cache interconnect 2868 is an interconnect network that connects each of the functional units of the graphics multiprocessor 2924 to the register file 2858 and to the shared memory 2870 …The shared memory 2870 can be used to enable communication between threads that execute on the functional units within the graphics multiprocessor 2834. The cache memory 2872 can be used as a data cache for example, to cache texture data communicated between the functional units and the texture unit 2836” …inherent/obvious the data would be move from L2 cache, local parallel processor memory, or system memory to L1 cache before multiprocessor receive data from L1 cache to process to improve running performance).
Regarding claim 22, Appu et al. as modified Chadha et al. teach all the limitation of claim 21, and Appu et al. further teach wherein the processing circuitry is further to facilitate the memory to temporarily store a first set of data during a first time period, while a processing resource performs computations on a second set of data during a second time period (par 0246-0248, “Embodiments in which the processing cluster 2814 includes multiple instances of the graphics multiprocessor 2834 can share common instructions and data, which may be stored in the L1 cache 2908 … a processing cluster 2814 may be configured such that each graphics multiprocessor 2834 is coupled to a texture unit 2836 for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering the texture data. Texture data is read from an internal texture L1 cache (not shown) or in some embodiments from the L1 cache within graphics multiprocessor 2834 and is fetched from an L2 cache, local parallel processor memory, or system memory, as needed. Each graphics multiprocessor 2834 outputs processed tasks to the data crossbar 2840 to provide the processed task to another processing cluster 2814 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via the memory crossbar 2816” …inherent/obvious the data would be move from L2 cache, local parallel processor memory, or system memory to L1 cache before multiprocessor receive data from L1 cache to process to improve running performance).
Regarding claim 24, Appu et al. teach all the limitation of claim 21, and Appu et al. further teach wherein the cache comprises an embedded Dynamic Random Access Memory (DRAM) (par 0047, par 0055, “interconnect which facilitates communication between various processor components and a high-performance embedded memory module 218, such as an eDRAM module. In some embodiments, each of the processor cores 202A-202N and graphics processor 208 use embedded memory modules 218 as a shared Last Level Cache”, par 0236, par 0264, “each multi-core processor 3005-3006 is communicatively coupled to a processor memory 3001-3002, via memory interconnects 3030-3031, respectively, and each GPU 3010-3013 is communicatively coupled to GPU memory 3020-3023 over GPU memory interconnects 3050-3053, respectively. The memory interconnects 3030-3031 and 3050-3053 may utilize the same or different memory access technologies. By way of example, and not limitation, the processor memories 3001-3002 and GPU memories 3020-3023 may be volatile memories such as dynamic random access memories (DRAMs) (including stacked DRAMs), Graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or High Bandwidth Memory (HBM) and/or may be non-volatile memories such as 3D XPoint or Nano-Ram. In one embodiment, some portion of the memories may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy)”).
Regarding claim 25, Appu et al. teach all the limitation of claim 21, and Appu et al. further teach wherein the processing circuitry comprises one or more of graphics processing circuitry or application processing circuitry (par 0114, par 0126, par 0133, par 0260).
Regarding claims 26-27 and 29-30, the method claims 26-27 and 29-30 are similar in scope to claims 21-22 and 24-25 and are rejected under the same rational.
Regarding claim 31, Appu et al. teach at least one computer-readable medium having stored thereon instructions which, when executed, cause a computing device to perform operations (par 0122, par 0315). The remaining limitations of the claim are similar in scope to claim 21 and rejected under the same rationale.
Regarding claim 32 and 34-35, Appu et al. teach all the limitation of claim 31, the method claims 32 and 34-45 are similar in scope to claims 32 and 34-35 and are rejected under the same rational.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 23, 28, and 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. PGPubs 2018/0293701 to Appu et al. in view of U.S. PGPubs 2018/0284186 to Chadha et al.. further in view of U.S. PGPubs 2008/0225603 to Hein.
Regarding claim 23, Appu et al. teach all the limitation of claim 21, but keep silent for teaching wherein the memory comprises a high-density memory or a stack-based memory, wherein the high-density memory includes a first serial port and a second serial port to receive and provide, respectively, the sets of data, wherein the stack-based memory includes a Last-In- First-Out (LIFO) stack such that the set of data are added or removed based on the LIFO technique.
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In related endeavor, Chadha et al. teach wherein the memory comprises a high-density memory or a stack-based memory (par 0003, “In 2D IC packages, multiple chips are mounted on a printed circuit board, where high-performance logic, lower-performance logic, memory, and analog/RF functions, and other functional elements are presented as discrete devices in separate chip packages. By contrast, in 2.5D ICs and 3D IC packages, multiple IC chips are mounted on a silicon interposer instead of a conventional package substrate. The silicon interposer, which is typically a silicon wafer, allows very small and high-density conductive traces to be formed between the multiple IC chips because the fabrication processes used to form the conductive traces are the same processes used to form the metal interconnects in the metalization layers of a silicon chip“, par 0049-0055, “IC chip 410 is a logic chip, such as a CPU or GPU, and IC chips 421-423 are memory chips associated with IC chip 410. In such embodiments, 3D IC chip stack 420 may include identical dynamic random-access memory (DRAM) or other random access memory chips that are each electrically coupled to IC chip 410 via a plurality of conductive traces 435 (described below) formed in interposer 430 … the wide-interface architecture of a high-bandwidth DRAM system may have one thousand or more conductive traces 435 for each IC chip in 3D IC chip stack 420. Thus, when 3D IC chip stack 420 includes four such DRAM chips, four thousand or more conductive traces 435 are formed between IC chip 410 and 3D IC chip stack 420, and are necessarily closely spaced, e.g., having a line pitch on the order of 10-100 microns”), wherein the stack-based memory includes a Last-In- First-Out (LIFO) stack such that the set of data are added or removed based on the LIFO technique (Fig 4A, par 0049-0052, “IC chip 410 is a logic chip, such as a CPU or GPU, and IC chips 421-423 are memory chips associated with IC chip 410. In such embodiments, 3D IC chip stack 420 may include identical dynamic random-access memory (DRAM) or other random access memory chips that are each electrically coupled to IC chip 410 via a plurality of conductive traces 435 (described below) formed in interposer 430”).
It would have been obvious to a person of ordinary skill in the art at the time before the effective filing data of the claimed invention to modified Appu et al. to include wherein the memory comprises a high-density memory or a stack-based memory, wherein the stack-based memory includes a Last-In- First-Out (LIFO) stack such that the set of data are added or removed based on the LIFO technique as taught by Chadha et al. to build a 3D IC stack packages to implement a memory bus residing in between a processor and a high-bandwidth memory chip with high-bandwidth in a high density.
In related endeavor, Hein teaches wherein the high-density memory includes a first serial port and a second serial port to receive and provide, respectively, the sets of data (Fig 6A, par 0091, “Output 130 of output buffer 110 works with the core speed of 500 MHz at a bus width of 72 bits and is coupled to an eight-fold parallel/serial converter 580 (x8 Par2Ser) which, in turn, performs a conversion of the incoming 72 data signals of the core domain into a 9 bits wide data stream in the WCK domain, a transmission speed of 4 Gps being achieved again per pin. Converter 580 is then coupled to data interface 140 via transmit driver circuit 410”) and a second serial port to provide the first set of data (Fig 6A, par 0086-0087, “Conversion circuit 510 then reduces the transmission frequency of 2 GHz to the core speed of, for example, 500 MHz, and at the same time represents a transition in an SDR architecture, so that a total of eight data signals are generated on eight data lines from each incoming data line. This data which is present at the output of conversion circuit 510 is also referred to as write data”).
It would have been obvious to a person of ordinary skill in the art at the time before the effective filing data of the claimed invention to modified Appu et al. as modified Chadha et al. to include wherein the high-density memory includes a first serial port and a second serial port to receive and provide, respectively, the sets of data as taught by Hein to transmit data from a memory core coupled to the input of the output buffer through a serial port to cause data stored within the output buffer to be output to the data interface upon reception of a first signal and cause data stored within the memory core to be output to the input of the output buffer upon reception of a second signal to synchronize the data interface to a clock on the basis of the transmit data pattern and the receive data pattern between memories and processors.
Regarding claim 28, Appu et al. teach all the limitation of claim 26, the method claim 28 is similar in scope to claim 23 and is rejected under the same rational.
Regarding claim 33, Appu et al. teach all the limitation of claim 31, the method claim 33 is similar in scope to claim 23 and is rejected under the same rational.
Conclusion
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JIN . GE
Examiner
Art Unit 2619
/JIN GE/Primary Examiner, Art Unit 2619
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