CTNF 19/048,338 CTNF 83226 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 35 U.S.C. 103 07-20-fti The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action: (a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made. 07-21 AIA Claim s 1-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Vashi et al. (US Pub. No. 2021/0125675) in view of (Tomita - US Pub. No. 2002/0044484) . With respect to claims 1, 8 and 15, the Vashi et al. reference teaches a memory device; and a processing device operatively coupled to the memory device, the processing device to perform operations comprising: determining that a scan triggering condition has been satisfied for a block of the memory device ([0024] - Once the stacking of reliability conditions of concern has been identified, storing required information for each block and trigger ing refresh, based on threshold conditions defined, can provide better coverage to stacking of reliability issues observed in the system); setting a scan flag associated with the block to a first value indicative of satisfaction of the scan triggering condition ([0084] - the erasure count (EC) of this block is at some number, x, which can be monitored with counter as EC=x. At T 0 , the block is flagged for a scan, which, in this example scenario, results in a condition 771 in which the block pass es a correctable error correction code (CECC) error count criteria, and a check of a corresponding cross temperature delta for the corresponding scan results in the cross temperature delta being less than a threshold cross temperature delta for the memory device); responsive to performing the erase operation on the block, performing the scan operation on the block ([0084] - the erasure count (EC) of this block is at some number, x, which can be monitored with counter as EC=x. At T 0 , the block is flagged for a scan, which, in this example scenario, results in a condition 771 in which the block pass es a correctable error correction code (CECC) error count criteria, and a check of a corresponding cross temperature delta for the corresponding scan results in the cross temperature delta being less than a threshold cross temperature delta for the memory device)). The Vashi et al. reference does not teach delaying a scan operation of the block until an erase operation is performed on the block. The Tomita reference teaches delaying a scan operation of the block until an erase operation is performed on the block ([0149] - The flash programmer scans a programming instruction code into the function command register 34 to initiate the erasing and programming of the selected sector in the memory cell array 12, then repeatedly scans in No Operation instruction codes and checks the value of the busy status signal, which is scanned out at the TDO terminal, to determine when programming has been completed). Thus, it would have been obvious to one of ordinary skill in the art at the time of the invention was made to have combined the references Vashi et al. and Tomita to incorporate delaying a scan operation of the block until an erase operation is performed on the block into the claimed invention. The motivation for delaying a scan operation of the block until an erase operation is performed on the block is for improved speed ([0188] - Tomita). With respect to claims 2, 9 and 16, the Vashi et al. reference teaches wherein the operations further comprise retiring the block from use in the memory device in response to determining that the block fails the scan operation ([0099] - determining fail ure of a scan of the block and, with the reliability specification different from a data retention specification being a cross temperature delta specification, logging the information associated with the fail ure of the scan of the block with a refresh not triggered due to a determined cross temperature delta exceeding a threshold cross temperature delta). With respect to claims 3, 10 and 17, the Vashi et al. reference teaches wherein the operations further comprise retaining the block for use in the memory device in response to determining that the block passes the scan operation ([0084] - the erasure count (EC) of this block is at some number, x, which can be monitored with counter as EC=x. At T 0 , the block is flagged for a scan, which, in this example scenario, results in a condition 771 in which the block pass es a correctable error correction code (CECC) error count criteria, and a check of a corresponding cross temperature delta for the corresponding scan results in the cross temperature delta being less than a threshold cross temperature delta for the memory device). With respect to claim 4, 11 and 18, the Vashi et al. reference teaches wherein the scan triggering condition is a threshold number of memory access operations performed on the block ([0077] - to execute a memory scan and implement a trigger of a refresh of a block of the scanned memory based on exceeding a thres hold condition for a combination of reliability specifications). With respect to claim 5, 12 and 19, the Vashi et al. reference teaches wherein the scan operation is performed as a background operation ([0028] - number of sca ns, N, is a variable that can be monitored, for example, using a counter arrangement that can be reset after a refresh. A threshold parameter for the number of sca ns is a parameter that can be fixed for an analysis but can be updated in the firmware that controls the sca n and evaluation process. The number of sca ns threshold condition can be used when the system does not have power-on time logging capability). With respect to claims 6, 13 and 20, the Vashi et al.. reference teaches wherein a blockstripe comprises a plurality of blocks of the memory device, the plurality of blocks comprising the block, and wherein the erase operation is performed on each of the plurality of blocks of the blockstripe ([0075] - A program erase cycles specification provides the number of times a NAND cell can erase and write data, without impacting the data information/errors, which determines the endurance of the NAND cell). With respect to claims 7 and 14, the Vashi et al.. reference teaches wherein the operations further comprise using a look-up table to track scan flags associated with the plurality of blocks of the blockstripe ([0138] - trac king the operations of the memory device it initiates) . Conclusion 07-101 Any inquiry concerning this communication or earlier communications from the examiner should be directed to Enam Ahmed whose telephone number is 571-270-1729 . The examiner can normally be reached on Mon-Fri from 8:30 A.M . to 5:30 P.M . If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Albert Decady , can be reached on 571-272-3819 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). EA 6/10/26 /ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112 Application/Control Number: 19/048,338 Page 2 Art Unit: 2112 Application/Control Number: 19/048,338 Page 3 Art Unit: 2112 Application/Control Number: 19/048,338 Page 4 Art Unit: 2112 Application/Control Number: 19/048,338 Page 5 Art Unit: 2112 Application/Control Number: 19/048,338 Page 6 Art Unit: 2112
Prosecution Insights