DETAILED ACTION
This Office Action is filed responsive to the initial filing of application 19/048,403 filed 7 February 2025.. Claims 1-20, as presented in a preliminary amendment on 7 February 2025, are currently pending and have been fully considered below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 3, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG (US PGPub 2005/0027961) in further view of HSU et al (US PGPub 2014/0181460).
With respect to Claim 1, ZHANG discloses a system-on-chip comprising:
a translation lookaside buffer (TLB) that stores a portion of address translation information for translating between virtual addresses and physical addresses (Fig 2, 2nd Level TLB 208; ¶[0003] – “TLBs facilitate quick mapping of virtual addresses to physical addresses”);
at least one core configured to execute an instruction and to access the TLB (Fig 1, Processor(s) 102; ¶[0022] – “The computer system 100 may comprise one, two, three, or more processors, any of which may execute a set of instructions in accordance with embodiments of the present invention”; ¶[0006] – “The processor includes a translation lookaside buffer”);
a page table walker configured to perform a page table walk operation of searching a page table that stores the address translation information (¶[0028] – “if a match is not found in either of the TLBs, the virtual address resolution system 200 fetches the corresponding page frame number 212 from the page table 210”); and
a static page management (SPM) circuit (Fig 2, 1st Level TLB 206).
ZHANG may not explicitly disclose a static page management (SPM) circuit configured to, when a physical address is obtained from a virtual address included in static address translation information corresponding to a static page among the address translation information, stop access to the TLB by the at least one core or stop the page table walk operation.
However, HSU discloses a static page management (SPM) circuit configured to, when a physical address is obtained from a virtual address included in static address translation information corresponding to a static page among the address translation information, stop access to the TLB by the at least one core or stop the page table walk operation (¶[0031] – “The processing device 100 may include more than two groups of processing units that share a memory and respective TLB hierarchies. In such case, a translation request of any processing unit that fails to be fulfilled with reference to TLB hierarchy with which that processing unit is associated can result in a probe of all or a subset of the other TLB hierarchies for the requested address translation. In one embodiment, if a hit is encountered in any probed TLB hierarchy, a page table walk is avoided. Alternatively, the probes may be issued in parallel with initiating the page table walk. In such case, if a translation hit is returned by any queried device, the page table walk is aborted or its response is ignored.”).
ZHANG and HSU are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG and HSU before him or her, to modify the virtual address resolution system of ZHANG to include aborting searching a page table responsive to a TLB hit as taught by HSU. A motivation for doing so would have been to free computing resources used to conduct the page table search so that they may be allocated for other purposes. Therefore, it would have been obvious to combine ZHANG and HSU to obtain the invention as specified in the instant claims.
With respect to Claim 3, the combination of ZHANG and HSU disclose the system-on-chip of claim 1.
HSU further discloses wherein, when the physical address is obtained from the static address translation information, the SPM circuit is configured to stop the page table walk operation provided from the TLB (¶[0031] – “The processing device 100 may include more than two groups of processing units that share a memory and respective TLB hierarchies. In such case, a translation request of any processing unit that fails to be fulfilled with reference to TLB hierarchy with which that processing unit is associated can result in a probe of all or a subset of the other TLB hierarchies for the requested address translation. In one embodiment, if a hit is encountered in any probed TLB hierarchy, a page table walk is avoided. Alternatively, the probes may be issued in parallel with initiating the page table walk. In such case, if a translation hit is returned by any queried device, the page table walk is aborted or its response is ignored.”).
With respect to Claim 8, the combination of ZHANG and HSU disclose the system-on-chip of claim 1.
ZHANG further discloses wherein the SPM circuit is further configured to store, as the static address translation information, address translation information corresponding to a virtual address of data for performing a certain function (Fig 4A illustrates a TLB entry including address translation information; ¶[0031] – “ the page frame number 212 is combined with an offset to address a location in physical memory {analogous to ‘a certain function’}”).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG in further view of RAVAL et al (US PGPub 2020/0097413).
With respect to Claim 11, ZHANG discloses an operating method of a system-on-chip, the operating method comprising:
starting a first search operation of searching a translation lookaside buffer (TLB) that stores address translation information corresponding to a static page and a dynamic page, the address translation information being for translating between virtual addresses and physical addresses (Fig 2, 2nd Level TLB 208; ¶[0027] – “The virtual page number 202 is transmitted to the first level TLB 206, which attempts to match the virtual page number 202 with a virtual page number (not shown) stored in the first level TLB 206 … The virtual page number 202 is also transmitted to a second level TLB 208, which attempts to match the virtual page number 202 with a virtual page number (not shown) stored in the second level TLB 208”);
starting a second search operation of searching a static page management buffer that stores static address translation information corresponding to the static page (Fig 2, 1st Level TLB 206; ¶[0027] – “The virtual page number 202 is transmitted to the first level TLB 206, which attempts to match the virtual page number 202 with a virtual page number (not shown) stored in the first level TLB 206 … The virtual page number 202 is also transmitted to a second level TLB 208, which attempts to match the virtual page number 202 with a virtual page number (not shown) stored in the second level TLB 208”); and
obtaining a physical address corresponding to a virtual address, based on a result of the first search operation or a result of the second search operation (¶[0027] – “If the first level TLB 206 finds an entry containing a virtual page number matching the virtual page number 202, the first level TLB 206 provides a page frame number 212 corresponding to the virtual page number 202 … If the second level TLB 208 finds an entry containing a virtual page number matching the virtual page number 202, the second level TLB 208 provides the page frame 212 number corresponding to the virtual page 202”).
ZHANG may not explicitly disclose wherein, in response to the result of the second search operation being received while the first search operation is still being performed, stopping the first search operation.
However, RAVAL discloses wherein, in response to the result of the second search operation being received while the first search operation is still being performed, stopping the first search operation (¶[0030] – “if MMU 320 receives a translation request indicating a virtual memory address, it checks TLB 330 to see if a translation has been cached therein (i.e., a TLB hit). If not (i.e., a TLB miss), the MMU 320 checks EMTLB 360 to see if a translation has been cached therein, and/or performs a page table walk using PTW 340”; ¶[0032] – “In some cases, the EMTLB lookup is aborted after the TLB lookup completes”).
ZHANG and RAVAL are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG and RAVAL before him or her, to modify the operation of fetching physical address information from the 2nd Level TLB of ZHANG to include aborting the 2nd Level TLB operation in response to completion of the TLB lookup by the 1st Level TLB as taught by RAVAL. A motivation for doing so would have been to free computing resources used to conduct the page table search so that they may be allocated for other purposes. Therefore, it would have been obvious to combine ZHANG and RAVAL to obtain the invention as specified in the instant claims.
Claim(s) 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG in further view of RO et al (US PGPub 2021/096745).
With respect to Claim 18, ZHANG discloses an operating method of a system-on-chip, the operating method comprising:
performing a first search operation of searching a translation lookaside buffer (TLB) that stores address translation information for a dynamic page and a static page, the address translation information being for translating between virtual addresses and physical addresses (Fig 2, 2nd Level TLB 208; ¶[0027] – “The virtual page number 202 is transmitted to the first level TLB 206, which attempts to match the virtual page number 202 with a virtual page number (not shown) stored in the first level TLB 206 … The virtual page number 202 is also transmitted to a second level TLB 208, which attempts to match the virtual page number 202 with a virtual page number (not shown) stored in the second level TLB 208”);
performing a second search operation of searching a page table that is stored in a memory device, based on a result of the first search operation (Fig 2, 1st Level TLB 206; ¶[0027] – “The virtual page number 202 is transmitted to the first level TLB 206, which attempts to match the virtual page number 202 with a virtual page number (not shown) stored in the first level TLB 206 … The virtual page number 202 is also transmitted to a second level TLB 208, which attempts to match the virtual page number 202 with a virtual page number (not shown) stored in the second level TLB 208”).
ZHANG may not explicitly disclose replacing address translation information for the dynamic page in preference to replacing address translation information for the static page, in at least one of the TLB and the page table, based on the result of the first search operation and a result of the second search operation.
However, RO discloses replacing address translation information for the dynamic page in preference to replacing address translation information for the static page, in at least one of the TLB and the page table, based on the result of the first search operation and a result of the second search operation (¶[0065] – “the first L1 TLB 2121, the second L1 TLB 2122 and the L2 TLB 230 may evict a stored PTE. For example, the first L1 TLB 2121, the second L1 TLB 2122 and the L2 TLB 230 may sequentially evict PTEs in ascending order of hit frequency according to the least recently used (LRU) scheme so that other PTEs may be stored.”; the specification at ¶[0042] states “the static page may refer to a page that is frequently accessed by the OS”; thus, a ‘static’ page may be interpreted as a page having a higher hit frequency than a ‘dynamic’ page).
ZHANG and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG and RO before him or her, to modify the eviction order of a page table entry in a TLB of ZHANG to include victim selection based on hit frequency as taught by RO. A motivation for doing so would have been to optimize use of the TLBs so that the most frequently used entries are kept in the TLB in hopes of maximizing the TLB hit rate (Abstract). Therefore, it would have been obvious to combine ZHANG and RO to obtain the invention as specified in the instant claims..
With respect to Claim 19, the combination of ZHANG and RO disclose the operating method of claim 18.
RO further discloses wherein the address translation information for the dynamic page comprises address translation information about a virtual address accessed less than a threshold number of times by a core, and the address translation information for the static page comprises address translation information about a virtual address accessed the threshold number of times or more by the core (¶[0068] – “Each of PTEs configuring the page tables of the first and second L1 TLBs 2121 and 2122 may be configured to include a valid hit V, a count bit C, a tag and a physical page number PPN …The count bit C is a bit added to determine whether a corresponding page is a hot page”; ‘static’ vs ‘dynamic’ pages may be identified or distinguished by count bit C).
With respect to Claim 20, the combination of ZHANG and RO disclose the operating method of claim 18.
RO further discloses wherein the address translation information for the static page comprises address translation information corresponding to a virtual address of data of a certain type (¶[0068] – “Each of PTEs configuring the page tables of the first and second L1 TLBs 2121 and 2122 may be configured to include a valid hit V, a count bit C, a tag and a physical page number PPN …The count bit C is a bit added to determine whether a corresponding page is a hot page”; ‘static’ vs ‘dynamic’ pages {or ‘data of a certain type’} may be identified or distinguished by count bit C).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG in further view of HSU and RAVAL et al (US PGPub 2020/0097413).
With respect to Claim 2, the combination of ZHANG and HSU discloses the system-on-chip of claim 1.
ZHANG and HSU may not explicitly disclose wherein, when the physical address is obtained from the static address translation information, the SPM circuit is configured to stop the at least one core from accessing the TLB in response to an address translation request.
However, RAVAL discloses wherein, when the physical address is obtained from the static address translation information, the SPM circuit is configured to stop the at least one core from accessing the TLB in response to an address translation request (¶[0030] – “if MMU 320 receives a translation request indicating a virtual memory address, it checks TLB 330 to see if a translation has been cached therein (i.e., a TLB hit). If not (i.e., a TLB miss), the MMU 320 checks EMTLB 360 to see if a translation has been cached therein, and/or performs a page table walk using PTW 340”; ¶[0032] – “In some cases, the EMTLB lookup is aborted after the TLB lookup completes”).
ZHANG, HSU, and RAVAL are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, HSU, and RAVAL before him or her, to modify the operation of fetching physical address information from the 2nd Level TLB of the combination of ZHANG and HSU to include aborting the 2nd Level TLB operation in response to completion of the TLB lookup by the 1st Level TLB as taught by RAVAL. A motivation for doing so would have been to free computing resources used to conduct the page table search so that they may be allocated for other purposes. Therefore, it would have been obvious to combine ZHANG, HSU, and RAVAL to obtain the invention as specified in the instant claims.
Claim(s) 4-7, 9, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG in further view of HSU and RO.
With respect to Claim 4, the combination of ZHANG and HSU disclose the system-on-chip of claim 1.
ZHANG and HSU may not explicitly disclose wherein, when the physical address is obtained from the static address translation information, the SPM circuit is configured to provide address translation information corresponding to the virtual address to the TLB.
However, RO discloses wherein, when the physical address is obtained from the static address translation information, the SPM circuit is configured to provide address translation information corresponding to the virtual address to the TLB (¶[0062] – “When the PTE count bit C reaches a set second threshold, the first L1 TLB 2121 transmits the PTE to the second L1 TLB 2122. That is, the first L1 TLB 2121 treats, as a hot page, a PTE having a count bit C higher than the second threshold, and stores the PTE in the second L1 TLB 2122”).
ZHANG, HSU, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, HSU, and RO before him or her, to modify the 1st and 2nd Level TLBs of the combination of ZHANG and HSU to include moving entries between the TLBs as taught by RO. A motivation for doing so would have been to optimize use of the TLBs according to the type of memory implementing the TLBs such that hot pages may be allocated to the fastest TLB improving overall system performance (¶[0028]). Therefore, it would have been obvious to combine ZHANG, HSU, and RO to obtain the invention as specified in the instant claims.
With respect to Claim 5, the combination of ZHANG and HSU disclose the system-on-chip of claim 1.
ZHANG and HSU may not explicitly disclose wherein, in a page replacement operation of replacing address translation information that is stored in the TLB, a replacement priority of address translation information corresponding to a dynamic page among the address translation information that is stored in the TLB is higher than a replacement priority of address translation information corresponding to the static page.
However, RO discloses wherein, in a page replacement operation of replacing address translation information that is stored in the TLB, a replacement priority of address translation information corresponding to a dynamic page among the address translation information that is stored in the TLB is higher than a replacement priority of address translation information corresponding to the static page (¶[0065] – “the first L1 TLB 2121, the second L1 TLB 2122 and the L2 TLB 230 may evict a stored PTE. For example, the first L1 TLB 2121, the second L1 TLB 2122 and the L2 TLB 230 may sequentially evict PTEs in ascending order of hit frequency according to the least recently used (LRU) scheme so that other PTEs may be stored.”; the specification at ¶[0042] states “the static page may refer to a page that is frequently accessed by the OS”; thus, a ‘static’ page may be interpreted as a page having a higher hit frequency than a ‘dynamic’ page).
ZHANG, HSU, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, HSU, and RO before him or her, to modify the eviction order of a page table entry in a TLB of the combination of ZHANG and HSU to include victim selection based on hit frequency as taught by RO. A motivation for doing so would have been to optimize use of the TLBs so that the most frequently used entries are kept in the TLB in hopes of maximizing the TLB hit rate (Abstract). Therefore, it would have been obvious to combine ZHANG, HSU, and RO to obtain the invention as specified in the instant claims.
With respect to Claim 6, the combination of ZHANG and HSU disclose the system-on-chip of claim 1.
ZHANG and HSU may not explicitly disclose wherein, in a page replacement operation of replacing address translation information stored in the TLB, at least a portion of address translation information other than address translation information corresponding to the static page among the address translation information that is stored in the TLB is replaced.
However, RO discloses wherein, in a page replacement operation of replacing address translation information stored in the TLB, at least a portion of address translation information other than address translation information corresponding to the static page among the address translation information that is stored in the TLB is replaced ((¶[0065] – “the first L1 TLB 2121, the second L1 TLB 2122 and the L2 TLB 230 may evict a stored PTE. For example, the first L1 TLB 2121, the second L1 TLB 2122 and the L2 TLB 230 may sequentially evict PTEs in ascending order of hit frequency according to the least recently used (LRU) scheme so that other PTEs may be stored.”).
ZHANG, HSU, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, HSU, and RO before him or her, to modify the eviction order of a page table entry in a TLB of the combination of ZHANG and HSU to include victim selection based on hit frequency as taught by RO. A motivation for doing so would have been to optimize use of the TLBs so that the most frequently used entries are kept in the TLB in hopes of maximizing the TLB hit rate (Abstract). Therefore, it would have been obvious to combine ZHANG, HSU, and RO to obtain the invention as specified in the instant claims.
With respect to Claim 7, the combination of ZHANG and HSU disclose the system-on-chip of claim 1.
ZHANG and HSU may not explicitly disclose wherein the SPM circuit is further configured to store, as the static address translation information, address translation information about a virtual address accessed a threshold number of times or more, among the address translation information.
However, RO discloses wherein the SPM circuit is further configured to store, as the static address translation information, address translation information about a virtual address accessed a threshold number of times or more, among the address translation information (¶[0068] – “Each of PTEs configuring the page tables of the first and second L1 TLBs 2121 and 2122 may be configured to include a valid hit V, a count bit C, a tag and a physical page number PPN …The count bit C is a bit added to determine whether a corresponding page is a hot page”).
ZHANG, HSU, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, HSU, and RO before him or her, to modify the 1st and 2nd Level TLBs of the combination of ZHANG and HSU to include maintaining count bits for page table entries as taught by RO. A motivation for doing so would have been to determine access counts for page table entries that may be used to optimize use of the TLBs according to the type of memory implementing the TLBs such that hot pages may be allocated to the fastest TLB improving overall system performance (¶[0028]). Therefore, it would have been obvious to combine ZHANG, HSU, and RO to obtain the invention as specified in the instant claims.
With respect to Claim 9, the combination of ZHANG and HSU disclose the system-on-chip of claim 1.
ZHANG and HSU may not explicitly disclose wherein the TLB further stores information distinguishing between the static address translation information and dynamic address translation information, wherein the static address translation information corresponds to the static page, and the dynamic address translation information corresponds to a dynamic page.
However, RO discloses wherein the TLB further stores information distinguishing between the static address translation information and dynamic address translation information, wherein the static address translation information corresponds to the static page, and the dynamic address translation information corresponds to a dynamic page (¶[0068] – “Each of PTEs configuring the page tables of the first and second L1 TLBs 2121 and 2122 may be configured to include a valid hit V, a count bit C, a tag and a physical page number PPN …The count bit C is a bit added to determine whether a corresponding page is a hot page”; ‘static’ vs ‘dynamic’ pages may be identified or distinguished by count bit C).
ZHANG, HSU, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, HSU, and RO before him or her, to modify the 1st and 2nd Level TLBs of the combination of ZHANG and HSU to include maintaining count bits for page table entries as taught by RO. A motivation for doing so would have been to determine access counts for page table entries that may be used to optimize use of the TLBs according to the type of memory implementing the TLBs such that hot pages may be allocated to the fastest TLB improving overall system performance (¶[0028]). Therefore, it would have been obvious to combine ZHANG, HSU, and RO to obtain the invention as specified in the instant claims.
With respect to Claim 10, the combination of ZHANG and HSU disclose the system-on-chip of claim 1.
ZHANG and HSU may not explicitly disclose wherein the TLB further stores, for each virtual address in the address translation information stored in the TLB, information about a number of times the at least one core accesses the virtual address.
However, RO discloses wherein the TLB further stores, for each virtual address in the address translation information stored in the TLB, information about a number of times the at least one core accesses the virtual address (¶[0068] – “Each of PTEs configuring the page tables of the first and second L1 TLBs 2121 and 2122 may be configured to include a valid hit V, a count bit C, a tag and a physical page number PPN …The count bit C is a bit added to determine whether a corresponding page is a hot page”).
ZHANG, HSU, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, HSU, and RO before him or her, to modify the 1st and 2nd Level TLBs of the combination of ZHANG and HSU to include maintaining count bits for page table entries as taught by RO. A motivation for doing so would have been to determine access counts for page table entries that may be used to optimize use of the TLBs according to the type of memory implementing the TLBs such that hot pages may be allocated to the fastest TLB improving overall system performance (¶[0028]). Therefore, it would have been obvious to combine ZHANG, HSU, and RO to obtain the invention as specified in the instant claims.
Claim(s) 12 and 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG in further view of RAVAL and RO.
With respect to Claim 12, the combination of ZHANG and RAVAL disclose the operating method of claim 11.
ZHANG and RAVAL may not explicitly disclose when the static address translation information includes an entry corresponding to the virtual address, copying the entry from the static page management buffer into the TLB.
However, RO discloses when the static address translation information includes an entry corresponding to the virtual address, copying the entry from the static page management buffer into the TLB (¶[0062] – “When the PTE count bit C reaches a set second threshold, the first L1 TLB 2121 transmits the PTE to the second L1 TLB 2122. That is, the first L1 TLB 2121 treats, as a hot page, a PTE having a count bit C higher than the second threshold, and stores the PTE in the second L1 TLB 2122”). \
ZHANG, RAVAL, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, RAVAL, and RO before him or her, to modify the 1st and 2nd Level TLBs of the combination of ZHANG and RAVAL to include moving entries between the TLBs as taught by RO. A motivation for doing so would have been to optimize use of the TLBs according to the type of memory implementing the TLBs such that hot pages may be allocated to the fastest TLB improving overall system performance (¶[0028]). Therefore, it would have been obvious to combine ZHANG, RAVAL, and RO to obtain the invention as specified in the instant claims.
With respect to Claim 14, the combination of ZHANG and RAVAL disclose the operating method of claim 11.
ZHANG and RAVAL may not explicitly disclose in a page replacement operation of replacing the address translation information stored in the TLB, replacing address translation information corresponding to the dynamic page in preference to address translation information corresponding to the static page.
However, RO discloses in a page replacement operation of replacing the address translation information stored in the TLB, replacing address translation information corresponding to the dynamic page in preference to address translation information corresponding to the static page (¶[0065] – “the first L1 TLB 2121, the second L1 TLB 2122 and the L2 TLB 230 may evict a stored PTE. For example, the first L1 TLB 2121, the second L1 TLB 2122 and the L2 TLB 230 may sequentially evict PTEs in ascending order of hit frequency according to the least recently used (LRU) scheme so that other PTEs may be stored.”; the specification at ¶[0042] states “the static page may refer to a page that is frequently accessed by the OS”; thus, a ‘static’ page may be interpreted as a page having a higher hit frequency than a ‘dynamic’ page).
ZHANG, RAVAL, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, RAVAL, and RO before him or her, to modify the eviction order of a page table entry in a TLB of the combination of ZHANG and RAVAL to include victim selection based on hit frequency as taught by RO. A motivation for doing so would have been to optimize use of the TLBs so that the most frequently used entries are kept in the TLB in hopes of maximizing the TLB hit rate (Abstract). Therefore, it would have been obvious to combine ZHANG, RAVAL, and RO to obtain the invention as specified in the instant claims.
With respect to Claim 15, the combination of ZHANG and RAVAL disclose the operating method of claim 11.
ZHANG and RAVAL may not explicitly disclose wherein the address translation information corresponding to the static page comprises address translation information corresponding to a virtual address accessed a threshold number of times or more.
However, RO discloses wherein the address translation information corresponding to the static page comprises address translation information corresponding to a virtual address accessed a threshold number of times or more (¶[0068] – “Each of PTEs configuring the page tables of the first and second L1 TLBs 2121 and 2122 may be configured to include a valid hit V, a count bit C, a tag and a physical page number PPN …The count bit C is a bit added to determine whether a corresponding page is a hot page”).
ZHANG, RAVAL, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, RAVAL, and RO before him or her, to modify the 1st and 2nd Level TLBs of the combination of ZHANG and RAVAL to include maintaining count bits for page table entries as taught by RO. A motivation for doing so would have been to determine access counts for page table entries that may be used to optimize use of the TLBs according to the type of memory implementing the TLBs such that hot pages may be allocated to the fastest TLB improving overall system performance (¶[0028]). Therefore, it would have been obvious to combine ZHANG, RAVAL, and RO to obtain the invention as specified in the instant claims.
With respect to Claim 16, the combination of ZHANG and RAVAL disclose the operating method of claim 11.
ZHANG and RAVAL may not explicitly disclose storing, in the TLB, information distinguishing between address translation information corresponding to the static page and address translation information corresponding to the dynamic page.
However, RO discloses storing, in the TLB, information distinguishing between address translation information corresponding to the static page and address translation information corresponding to the dynamic page (¶[0068] – “Each of PTEs configuring the page tables of the first and second L1 TLBs 2121 and 2122 may be configured to include a valid hit V, a count bit C, a tag and a physical page number PPN …The count bit C is a bit added to determine whether a corresponding page is a hot page”; ‘static’ vs ‘dynamic’ pages may be identified or distinguished by count bit C).
ZHANG, RAVAL, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, RAVAL, and RO before him or her, to modify the 1st and 2nd Level TLBs of the combination of ZHANG and RAVAL to include maintaining count bits for page table entries as taught by RO. A motivation for doing so would have been to determine access counts for page table entries that may be used to optimize use of the TLBs according to the type of memory implementing the TLBs such that hot pages may be allocated to the fastest TLB improving overall system performance (¶[0028]). Therefore, it would have been obvious to combine ZHANG, RAVAL, and RO to obtain the invention as specified in the instant claims.
With respect to Claim 17, the combination of ZHANG and RAVAL disclose the operating method of claim 11.
ZHANG and RAVAL may not explicitly disclose storing, in the TLB, information about a number of times a core of the at least one core accesses the address translation information.
However, RO discloses storing, in the TLB, information about a number of times a core of the at least one core accesses the address translation information (¶[0068] – “Each of PTEs configuring the page tables of the first and second L1 TLBs 2121 and 2122 may be configured to include a valid hit V, a count bit C, a tag and a physical page number PPN …The count bit C is a bit added to determine whether a corresponding page is a hot page”).
ZHANG, RAVAL, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, RAVAL, and RO before him or her, to modify the 1st and 2nd Level TLBs of the combination of ZHANG and RAVAL to include maintaining count bits for page table entries as taught by RO. A motivation for doing so would have been to determine access counts for page table entries that may be used to optimize use of the TLBs according to the type of memory implementing the TLBs such that hot pages may be allocated to the fastest TLB improving overall system performance (¶[0028]). Therefore, it would have been obvious to combine ZHANG, RAVAL, and RO to obtain the invention as specified in the instant claims.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG in further view of RAVAL and HSU.
With respect to Claim 13, the combination of ZHANG and RAVAL disclose the operating method of claim 11.
ZHANG and RAVAL may not explicitly disclose starting a page table walk operation of searching a page table that stores address translation information, and based on the result of the first search operation being obtained, stopping the page table walk operation.
However, HSU discloses starting a page table walk operation of searching a page table that stores address translation information, and based on the result of the first search operation being obtained, stopping the page table walk operation (¶[0031] – “The processing device 100 may include more than two groups of processing units that share a memory and respective TLB hierarchies. In such case, a translation request of any processing unit that fails to be fulfilled with reference to TLB hierarchy with which that processing unit is associated can result in a probe of all or a subset of the other TLB hierarchies for the requested address translation. In one embodiment, if a hit is encountered in any probed TLB hierarchy, a page table walk is avoided. Alternatively, the probes may be issued in parallel with initiating the page table walk. In such case, if a translation hit is returned by any queried device, the page table walk is aborted or its response is ignored.”).
ZHANG, RAVAL, and HSU are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, RAVAL, and HSU before him or her, to modify the virtual address resolution system of the combination of ZHANG and RAVAL to include aborting searching a page table responsive to a TLB hit as taught by HSU. A motivation for doing so would have been to free computing resources used to conduct the page table search so that they may be allocated for other purposes. Therefore, it would have been obvious to combine ZHANG, RAVAL, and HSU to obtain the invention as specified in the instant claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure teach similar processes for managing virtual-to-physical address mappings.
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/ERIC T LOONAN/Examiner, Art Unit 2137