DETAILED ACTION
This Office Action, based on application 19/048,403 filed 7 February 2025, is filed in response to applicant’s amendment and remarks filed 24 June 2026. Claims 1-19 are currently pending and have been fully considered below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s remarks, filed 24 June 2026 in response to the Office Action filed 25 March 2026, have been fully considered below.
Specification Objection
The Office withdraws the previously issued objection in view of applicant’s amendment and remarks.
Claim Rejections under 35 U.S.C. § 103
The applicant traverses the prior art rejection to the claims alleging cited prior art fails to teach or reasonably suggest the features of Claims 1, 11, and 18 (and respective dependent claims) as amended.
With respect to Claim 1, the applicant first alleges ZHANG fails to disclose only “static address translation information corresponding to the static page” since ZHANG allegedly teaches general purpose TLBs that store all types of address translations. In response, the Office acknowledges ZHANG’s first level TLB may not explicitly disclose addresses of a certain type, the Office presents new grounds of rejection in view of WATKINS disclosing that memory regions may dedicated to specific address types. The applicant further (secondly) alleges HSU’s teaching of aborting a page table walk upon a general TLB hit of one of multiple TLBs does not teach applicant’s claimed stopping feature since HSU is directed to a general TLB hit scenario and not applicant’s dedicated SPMB. The Office asserts the functioning of the address translation is the same regardless of whether the addresses stored in the TLB are static or dynamic. Whether or not an address in a TLB may change in the future does not change any functioning of a TLB to determine whether or not the TLB hits or misses an address triggering a page table walk. The Office is not persuaded by applicant’s argument and maintains the grounds of rejection.
With respect to Claim 11, the applicant applies a similar argument (e.g. ‘only’ static address translation information) as presented in applicant’s first argument to Claim 1. The Office maintains a similar response and presents new grounds of rejection in view of WATKINS.
With respect to Claim 18, the applicant alleges RO’s eviction scheme fails to disclose evicting based on address information of a static page corresponding to data corresponding to a certain software or data for performing a certain function of the certain software as allegedly required by the amended claim. In response, the Office asserts the claim is not limited as alleged by the applicant as the claims simply are not limited to the address information of a static page as the basis for evicting or ‘replacing’. The claim clearly recites “replacing address translation information … based on the result of the first search operation and a result of the second search operation”. While the applicant has amended the claim to recite a correspondence of the static page, the recitation merely indicates an intended use of the static page and in no way alters the claimed method of performing search operations and address translation replacement (i.e. the search operations and subsequent ‘replacing’ operation are not dependent or in any way linked as claimed to whether or not the static page has the claimed correspondence). The Office maintains a prior art rejection to the claim for reasons now presented in the grounds of rejection issued below.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 3, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG (US PGPub 2005/0027961) in further view of HSU et al (US PGPub 2014/0181460) and WATKINS (US Patent 6,073,224).
With respect to Claim 1, ZHANG discloses a system-on-chip comprising:
a translation lookaside buffer (TLB) that stores a portion of address translation information for translating between virtual addresses and physical addresses (Fig 2, 2nd Level TLB 208; ¶[0003] – “TLBs facilitate quick mapping of virtual addresses to physical addresses”);
at least one core configured to execute an instruction and to access the TLB (Fig 1, Processor(s) 102; ¶[0022] – “The computer system 100 may comprise one, two, three, or more processors, any of which may execute a set of instructions in accordance with embodiments of the present invention”; ¶[0006] – “The processor includes a translation lookaside buffer”);
a page table walker configured to perform a page table walk operation of searching a page table that stores the address translation information (¶[0028] – “if a match is not found in either of the TLBs, the virtual address resolution system 200 fetches the corresponding page frame number 212 from the page table 210”); and
a static page management (SPM) circuit (Fig 2, 1st Level TLB 206).
ZHANG may not explicitly disclose the static page management (SPM) circuit including a static page management buffer (SPMB) that stores only static address translation information corresponding to a static page among the address translation information, the SPM being configured to, when a physical address is obtained from a virtual address included in the static address translation information that is stored in the SPMB, stop access to the TLB by the at least one core or stop the page table walk operation.
However, HSU discloses the SPM being configured to, when a physical address is obtained from a virtual address included in the static address translation information that is stored in the SPMB, stop access to the TLB by the at least one core or stop the page table walk operation (¶[0031] – “The processing device 100 may include more than two groups of processing units that share a memory and respective TLB hierarchies. In such case, a translation request of any processing unit that fails to be fulfilled with reference to TLB hierarchy with which that processing unit is associated can result in a probe of all or a subset of the other TLB hierarchies for the requested address translation. In one embodiment, if a hit is encountered in any probed TLB hierarchy, a page table walk is avoided. Alternatively, the probes may be issued in parallel with initiating the page table walk. In such case, if a translation hit is returned by any queried device, the page table walk is aborted or its response is ignored.”).
ZHANG and HSU are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG and HSU before him or her, to modify the virtual address resolution system of ZHANG to include aborting searching a page table responsive to a TLB hit as taught by HSU. A motivation for doing so would have been to free computing resources used to conduct the page table search so that they may be allocated for other purposes. Therefore, it would have been obvious to combine ZHANG and HSU to obtain the invention as specified in the instant claims.
ZHANG and HSU may not explicitly disclose the static page management (SPM) circuit including a static page management buffer (SPMB) that stores only static address translation information corresponding to a static page among the address translation information.
However, WATKINS discloses the static page management (SPM) circuit including a static page management buffer (SPMB) that stores only static address translation information corresponding to a static page among the address translation information (Abstract, Col 8, Lines 28-38 – “generally static address translations may be allocated to a ‘locked’ region of memory and generally dynamic address translations in an ‘unlocked’ region of memory”).
ZHANG, HSU, and WATKINS are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, HSU, and WATKINS before him or her, to modify the TLBs of the combination of ZHANG and HSU to include translation information dedicated to a specific type of address translation such as static addresses as taught by WATKINS. A motivation for doing so would have been to improve performance by reducing the number of fetches to main memory for I/O MMU translation misses (Col 8, Lines 37-39). Therefore, it would have been obvious to combine ZHANG, HSU, and WATKINS to obtain the invention as specified in the instant claims.
With respect to Claim 3, the combination ZHANG, HSU, and WATKINS disclose the system-on-chip of claim 1.
HSU further discloses wherein, when the physical address is obtained from the static address translation information, the SPM circuit is configured to stop the page table walk operation provided from the TLB (¶[0031] – “The processing device 100 may include more than two groups of processing units that share a memory and respective TLB hierarchies. In such case, a translation request of any processing unit that fails to be fulfilled with reference to TLB hierarchy with which that processing unit is associated can result in a probe of all or a subset of the other TLB hierarchies for the requested address translation. In one embodiment, if a hit is encountered in any probed TLB hierarchy, a page table walk is avoided. Alternatively, the probes may be issued in parallel with initiating the page table walk. In such case, if a translation hit is returned by any queried device, the page table walk is aborted or its response is ignored.”).
With respect to Claim 8, the combination of ZHANG, HSU, and WATKINS disclose the system-on-chip of claim 1.
ZHANG further discloses wherein the SPM circuit is further configured to store, as the static address translation information, address translation information corresponding to a virtual address of data for performing a certain function (Fig 4A illustrates a TLB entry including address translation information; ¶[0031] – “ the page frame number 212 is combined with an offset to address a location in physical memory {analogous to ‘a certain function’}”).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG in further view of RAVAL et al (US PGPub 2020/0097413) and WATKINS.
With respect to Claim 11, ZHANG discloses an operating method of a system-on-chip, the operating method comprising:
starting a first search operation of searching a translation lookaside buffer (TLB) that stores address translation information corresponding to a static page and a dynamic page, the address translation information being for translating between virtual addresses and physical addresses (Fig 2, 2nd Level TLB 208; ¶[0027] – “The virtual page number 202 is transmitted to the first level TLB 206, which attempts to match the virtual page number 202 with a virtual page number (not shown) stored in the first level TLB 206 … The virtual page number 202 is also transmitted to a second level TLB 208, which attempts to match the virtual page number 202 with a virtual page number (not shown) stored in the second level TLB 208”);
starting a second search operation of searching a static page management buffer that stores static address translation information corresponding to the static page (Fig 2, 1st Level TLB 206; ¶[0027] – “The virtual page number 202 is transmitted to the first level TLB 206, which attempts to match the virtual page number 202 with a virtual page number (not shown) stored in the first level TLB 206 … The virtual page number 202 is also transmitted to a second level TLB 208, which attempts to match the virtual page number 202 with a virtual page number (not shown) stored in the second level TLB 208”); and
obtaining a physical address corresponding to a virtual address, based on a result of the first search operation or a result of the second search operation (¶[0027] – “If the first level TLB 206 finds an entry containing a virtual page number matching the virtual page number 202, the first level TLB 206 provides a page frame number 212 corresponding to the virtual page number 202 … If the second level TLB 208 finds an entry containing a virtual page number matching the virtual page number 202, the second level TLB 208 provides the page frame 212 number corresponding to the virtual page 202”).
ZHANG may not explicitly disclose wherein the static page management buffer stores only static address translation information; and wherein, in response to the result of the second search operation being received while the first search operation is still being performed, stopping the first search operation.
However, RAVAL discloses wherein, in response to the result of the second search operation being received while the first search operation is still being performed, stopping the first search operation (¶[0030] – “if MMU 320 receives a translation request indicating a virtual memory address, it checks TLB 330 to see if a translation has been cached therein (i.e., a TLB hit). If not (i.e., a TLB miss), the MMU 320 checks EMTLB 360 to see if a translation has been cached therein, and/or performs a page table walk using PTW 340”; ¶[0032] – “In some cases, the EMTLB lookup is aborted after the TLB lookup completes”).
ZHANG and RAVAL are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG and RAVAL before him or her, to modify the operation of fetching physical address information from the 2nd Level TLB of ZHANG to include aborting the 2nd Level TLB operation in response to completion of the TLB lookup by the 1st Level TLB as taught by RAVAL. A motivation for doing so would have been to free computing resources used to conduct the page table search so that they may be allocated for other purposes. Therefore, it would have been obvious to combine ZHANG and RAVAL to obtain the invention as specified in the instant claims.
ZHANG and RAVAL may not explicitly disclose wherein the static page management buffer stores only static address translation information.
However, WATKINS discloses wherein the static page management buffer stores only static address translation information (Abstract, Col 8, Lines 28-38 – “generally static address translations may be allocated to a ‘locked’ region of memory and generally dynamic address translations in an ‘unlocked’ region of memory”).
ZHANG, RAVAL, and WATKINS are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, RAVAL, and WATKINS before him or her, to modify the TLBs of the combination of ZHANG and RAVAL to include translation information dedicated to a specific type of address translation such as static addresses as taught by WATKINS. A motivation for doing so would have been to improve performance by reducing the number of fetches to main memory for I/O MMU translation misses (Col 8, Lines 37-39). Therefore, it would have been obvious to combine ZHANG, RAVAL, and WATKINS to obtain the invention as specified in the instant claims.
Claim(s) 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG in further view of RO et al (US PGPub 2021/096745) and WATKINS.
With respect to Claim 18, ZHANG discloses an operating method of a system-on-chip, the operating method comprising:
performing a first search operation of searching a translation lookaside buffer (TLB) that stores address translation information for a dynamic page and a static page, the address translation information being for translating between virtual addresses and physical addresses (Fig 2, 2nd Level TLB 208; ¶[0027] – “The virtual page number 202 is transmitted to the first level TLB 206, which attempts to match the virtual page number 202 with a virtual page number (not shown) stored in the first level TLB 206 … The virtual page number 202 is also transmitted to a second level TLB 208, which attempts to match the virtual page number 202 with a virtual page number (not shown) stored in the second level TLB 208”);
performing a second search operation of searching a page table that is stored in a memory device, based on a result of the first search operation (Fig 2, 1st Level TLB 206; ¶[0027] – “The virtual page number 202 is transmitted to the first level TLB 206, which attempts to match the virtual page number 202 with a virtual page number (not shown) stored in the first level TLB 206 … The virtual page number 202 is also transmitted to a second level TLB 208, which attempts to match the virtual page number 202 with a virtual page number (not shown) stored in the second level TLB 208”).
ZHANG may not explicitly disclose replacing address translation information for the dynamic page in preference to replacing address translation information for the static page, in at least one of the TLB and the page table, based on the result of the first search operation and a result of the second search operation; and wherein the static page corresponds to data corresponding to a certain software or data for performing a certain function of the certain software.
However, RO discloses replacing address translation information for the dynamic page in preference to replacing address translation information for the static page, in at least one of the TLB and the page table, based on the result of the first search operation and a result of the second search operation (¶[0065] – “the first L1 TLB 2121, the second L1 TLB 2122 and the L2 TLB 230 may evict a stored PTE. For example, the first L1 TLB 2121, the second L1 TLB 2122 and the L2 TLB 230 may sequentially evict PTEs in ascending order of hit frequency according to the least recently used (LRU) scheme so that other PTEs may be stored.”; the specification at ¶[0042] states “the static page may refer to a page that is frequently accessed by the OS”; thus, a ‘static’ page may be interpreted as a page having a higher hit frequency than a ‘dynamic’ page).
ZHANG and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG and RO before him or her, to modify the eviction order of a page table entry in a TLB of ZHANG to include victim selection based on hit frequency as taught by RO. A motivation for doing so would have been to optimize use of the TLBs so that the most frequently used entries are kept in the TLB in hopes of maximizing the TLB hit rate (Abstract). Therefore, it would have been obvious to combine ZHANG and RO to obtain the invention as specified in the instant claims.
ZHANG and RO may not explicitly disclose wherein the static page corresponds to data corresponding to a certain software or data for performing a certain function of the certain software.
However, WATKINS discloses wherein the static page corresponds to data corresponding to a certain software or data for performing a certain function of the certain software (Col 8, Lines 33-34 – “generally static translations {e.g. translation for a ring descriptor}”; Col 10, Lines 21-31 – “prior to enabling the ATU, address translations of descriptor rings {similar to ‘data corresponding to a certain software or data performing a certain function of the certain software”} or other generally static data structures are manually written by system software into the ATU”).
ZHANG, RO, and WATKINS are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, RO, and WATKINS before him or her, to modify the TLBs of the combination of ZHANG and RO to include translation information dedicated to a specific type of address translation such as static addresses for a ring descriptor as taught by WATKINS. A motivation for doing so would have been to allow address translations considered to be more static in nature from being replaced for address translations considered to be less static in nature resulting in a performance enhancement of the system (Col 2, Lines 55-63). Therefore, it would have been obvious to combine ZHANG, RO, and WATKINS to obtain the invention as specified in the instant claims.
With respect to Claim 19, the combination of ZHANG, RO, and WATKINS disclose the operating method of claim 18.
RO further discloses wherein the address translation information for the dynamic page comprises address translation information about a virtual address accessed less than a threshold number of times by a core, and the address translation information for the static page comprises address translation information about a virtual address accessed the threshold number of times or more by the core (¶[0068] – “Each of PTEs configuring the page tables of the first and second L1 TLBs 2121 and 2122 may be configured to include a valid hit V, a count bit C, a tag and a physical page number PPN …The count bit C is a bit added to determine whether a corresponding page is a hot page”; ‘static’ vs ‘dynamic’ pages may be identified or distinguished by count bit C).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG in further view of HSU, WATKINS, and RAVAL et al (US PGPub 2020/0097413).
With respect to Claim 2, the combination of ZHANG, HSU, and WATKINS discloses the system-on-chip of claim 1.
ZHANG, HSU, and WATKINS may not explicitly disclose wherein, when the physical address is obtained from the static address translation information, the SPM circuit is configured to stop the at least one core from accessing the TLB in response to an address translation request.
However, RAVAL discloses wherein, when the physical address is obtained from the static address translation information, the SPM circuit is configured to stop the at least one core from accessing the TLB in response to an address translation request (¶[0030] – “if MMU 320 receives a translation request indicating a virtual memory address, it checks TLB 330 to see if a translation has been cached therein (i.e., a TLB hit). If not (i.e., a TLB miss), the MMU 320 checks EMTLB 360 to see if a translation has been cached therein, and/or performs a page table walk using PTW 340”; ¶[0032] – “In some cases, the EMTLB lookup is aborted after the TLB lookup completes”).
ZHANG, HSU, WATKINS, and RAVAL are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, HSU, WATKINS, and RAVAL before him or her, to modify the operation of fetching physical address information from the 2nd Level TLB of the combination of ZHANG, HSU, and WATKINS to include aborting the 2nd Level TLB operation in response to completion of the TLB lookup by the 1st Level TLB as taught by RAVAL. A motivation for doing so would have been to free computing resources used to conduct the page table search so that they may be allocated for other purposes. Therefore, it would have been obvious to combine ZHANG, HSU, WATKINS, and RAVAL to obtain the invention as specified in the instant claims.
Claim(s) 4-7, 9, and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG in further view of HSU, WATKINS, and RO.
With respect to Claim 4, the combination of ZHANG, HSU, and WATKINS disclose the system-on-chip of claim 1.
ZHANG, HSU, and WATKINS may not explicitly disclose wherein, when the physical address is obtained from the static address translation information, the SPM circuit is configured to provide address translation information corresponding to the virtual address to the TLB.
However, RO discloses wherein, when the physical address is obtained from the static address translation information, the SPM circuit is configured to provide address translation information corresponding to the virtual address to the TLB (¶[0062] – “When the PTE count bit C reaches a set second threshold, the first L1 TLB 2121 transmits the PTE to the second L1 TLB 2122. That is, the first L1 TLB 2121 treats, as a hot page, a PTE having a count bit C higher than the second threshold, and stores the PTE in the second L1 TLB 2122”).
ZHANG, HSU, WATKINS, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, HSU, WATKINS, and RO before him or her, to modify the 1st and 2nd Level TLBs of the combination ZHANG, HSU, and WATKINS to include moving entries between the TLBs as taught by RO. A motivation for doing so would have been to optimize use of the TLBs according to the type of memory implementing the TLBs such that hot pages may be allocated to the fastest TLB improving overall system performance (¶[0028]). Therefore, it would have been obvious to combine ZHANG, HSU, WATKINS, and RO to obtain the invention as specified in the instant claims.
With respect to Claim 5, the combination of ZHANG, HSU, and WATKINS disclose the system-on-chip of claim 1.
ZHANG, HSU, and WATKINS may not explicitly disclose wherein, in a page replacement operation of replacing address translation information that is stored in the TLB, a replacement priority of address translation information corresponding to a dynamic page among the address translation information that is stored in the TLB is higher than a replacement priority of address translation information corresponding to the static page.
However, RO discloses wherein, in a page replacement operation of replacing address translation information that is stored in the TLB, a replacement priority of address translation information corresponding to a dynamic page among the address translation information that is stored in the TLB is higher than a replacement priority of address translation information corresponding to the static page (¶[0065] – “the first L1 TLB 2121, the second L1 TLB 2122 and the L2 TLB 230 may evict a stored PTE. For example, the first L1 TLB 2121, the second L1 TLB 2122 and the L2 TLB 230 may sequentially evict PTEs in ascending order of hit frequency according to the least recently used (LRU) scheme so that other PTEs may be stored.”; the specification at ¶[0042] states “the static page may refer to a page that is frequently accessed by the OS”; thus, a ‘static’ page may be interpreted as a page having a higher hit frequency than a ‘dynamic’ page).
ZHANG, HSU, WATKINS, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, HSU, WATKINS, and RO before him or her, to modify the eviction order of a page table entry in a TLB of the combination of ZHANG, HSU, and WATKINS to include victim selection based on hit frequency as taught by RO. A motivation for doing so would have been to optimize use of the TLBs so that the most frequently used entries are kept in the TLB in hopes of maximizing the TLB hit rate (Abstract). Therefore, it would have been obvious to combine ZHANG, HSU, WATKINS, and RO to obtain the invention as specified in the instant claims.
With respect to Claim 6, the combination of ZHANG, HSU, and WATKINS disclose the system-on-chip of claim 1.
ZHANG, HSU, and WATKINS may not explicitly disclose wherein, in a page replacement operation of replacing address translation information stored in the TLB, at least a portion of address translation information other than address translation information corresponding to the static page among the address translation information that is stored in the TLB is replaced.
However, RO discloses wherein, in a page replacement operation of replacing address translation information stored in the TLB, at least a portion of address translation information other than address translation information corresponding to the static page among the address translation information that is stored in the TLB is replaced ((¶[0065] – “the first L1 TLB 2121, the second L1 TLB 2122 and the L2 TLB 230 may evict a stored PTE. For example, the first L1 TLB 2121, the second L1 TLB 2122 and the L2 TLB 230 may sequentially evict PTEs in ascending order of hit frequency according to the least recently used (LRU) scheme so that other PTEs may be stored.”).
ZHANG, HSU, WATKINS, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, HSU, WATKINS, and RO before him or her, to modify the eviction order of a page table entry in a TLB of the combination of ZHANG, HSU, and WATKINS to include victim selection based on hit frequency as taught by RO. A motivation for doing so would have been to optimize use of the TLBs so that the most frequently used entries are kept in the TLB in hopes of maximizing the TLB hit rate (Abstract). Therefore, it would have been obvious to combine ZHANG, HSU, WATKINS, and RO to obtain the invention as specified in the instant claims.
With respect to Claim 7, the combination of ZHANG, HSU, and WATKINS disclose the system-on-chip of claim 1.
ZHANG, HSU, and WATKINS may not explicitly disclose wherein the SPM circuit is further configured to store, as the static address translation information, address translation information about a virtual address accessed a threshold number of times or more, among the address translation information.
However, RO discloses wherein the SPM circuit is further configured to store, as the static address translation information, address translation information about a virtual address accessed a threshold number of times or more, among the address translation information (¶[0068] – “Each of PTEs configuring the page tables of the first and second L1 TLBs 2121 and 2122 may be configured to include a valid hit V, a count bit C, a tag and a physical page number PPN …The count bit C is a bit added to determine whether a corresponding page is a hot page”).
ZHANG, HSU, WATKINS, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, HSU, WATKINS, and RO before him or her, to modify the 1st and 2nd Level TLBs of the combination of ZHANG, HSU, and WATKINS to include maintaining count bits for page table entries as taught by RO. A motivation for doing so would have been to determine access counts for page table entries that may be used to optimize use of the TLBs according to the type of memory implementing the TLBs such that hot pages may be allocated to the fastest TLB improving overall system performance (¶[0028]). Therefore, it would have been obvious to combine ZHANG, HSU, WATKINS, and RO to obtain the invention as specified in the instant claims.
With respect to Claim 9, the combination of ZHANG, HSU, and WATKINS disclose the system-on-chip of claim 1.
ZHANG, HSU, and WATKINS may not explicitly disclose wherein the TLB further stores information distinguishing between the static address translation information and dynamic address translation information, wherein the static address translation information corresponds to the static page, and the dynamic address translation information corresponds to a dynamic page.
However, RO discloses wherein the TLB further stores information distinguishing between the static address translation information and dynamic address translation information, wherein the static address translation information corresponds to the static page, and the dynamic address translation information corresponds to a dynamic page (¶[0068] – “Each of PTEs configuring the page tables of the first and second L1 TLBs 2121 and 2122 may be configured to include a valid hit V, a count bit C, a tag and a physical page number PPN …The count bit C is a bit added to determine whether a corresponding page is a hot page”; ‘static’ vs ‘dynamic’ pages may be identified or distinguished by count bit C).
ZHANG, HSU, WATKINS, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, HSU, WATKINS, and RO before him or her, to modify the 1st and 2nd Level TLBs of the combination of ZHANG, HSU, and WATKINS to include maintaining count bits for page table entries as taught by RO. A motivation for doing so would have been to determine access counts for page table entries that may be used to optimize use of the TLBs according to the type of memory implementing the TLBs such that hot pages may be allocated to the fastest TLB improving overall system performance (¶[0028]). Therefore, it would have been obvious to combine ZHANG, HSU, WATKINS, and RO to obtain the invention as specified in the instant claims.
With respect to Claim 10, the combination of ZHANG, HSU, and WATKINS disclose the system-on-chip of claim 1.
ZHANG, HSU, and WATKINS may not explicitly disclose wherein the TLB further stores, for each virtual address in the address translation information stored in the TLB, information about a number of times the at least one core accesses the virtual address.
However, RO discloses wherein the TLB further stores, for each virtual address in the address translation information stored in the TLB, information about a number of times the at least one core accesses the virtual address (¶[0068] – “Each of PTEs configuring the page tables of the first and second L1 TLBs 2121 and 2122 may be configured to include a valid hit V, a count bit C, a tag and a physical page number PPN …The count bit C is a bit added to determine whether a corresponding page is a hot page”).
ZHANG, HSU, WATKINS, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, HSU, WATKINS, and RO before him or her, to modify the 1st and 2nd Level TLBs of the combination of ZHANG, HSU, and WATKINS to include maintaining count bits for page table entries as taught by RO. A motivation for doing so would have been to determine access counts for page table entries that may be used to optimize use of the TLBs according to the type of memory implementing the TLBs such that hot pages may be allocated to the fastest TLB improving overall system performance (¶[0028]). Therefore, it would have been obvious to combine ZHANG, HSU, WATKINS, and RO to obtain the invention as specified in the instant claims.
Claim(s) 12 and 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG in further view of RAVAL, WATKINS, and RO.
With respect to Claim 12, the combination of ZHANG, RAVAL, and WATKINS disclose the operating method of claim 11.
ZHANG, RAVAL, and WATKINS may not explicitly disclose when the static address translation information includes an entry corresponding to the virtual address, copying the entry from the static page management buffer into the TLB.
However, RO discloses when the static address translation information includes an entry corresponding to the virtual address, copying the entry from the static page management buffer into the TLB (¶[0062] – “When the PTE count bit C reaches a set second threshold, the first L1 TLB 2121 transmits the PTE to the second L1 TLB 2122. That is, the first L1 TLB 2121 treats, as a hot page, a PTE having a count bit C higher than the second threshold, and stores the PTE in the second L1 TLB 2122”). \
ZHANG, RAVAL, WATKINS, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, RAVAL, WATKINS, and RO before him or her, to modify the 1st and 2nd Level TLBs of the combination of ZHANG, RAVAL, and WATKINS to include moving entries between the TLBs as taught by RO. A motivation for doing so would have been to optimize use of the TLBs according to the type of memory implementing the TLBs such that hot pages may be allocated to the fastest TLB improving overall system performance (¶[0028]). Therefore, it would have been obvious to combine ZHANG, RAVAL, WATKINS, and RO to obtain the invention as specified in the instant claims.
With respect to Claim 14, the combination of ZHANG, RAVAL, and WATKINS disclose the operating method of claim 11.
ZHANG, RAVAL, and WATKINS may not explicitly disclose in a page replacement operation of replacing the address translation information stored in the TLB, replacing address translation information corresponding to the dynamic page in preference to address translation information corresponding to the static page.
However, RO discloses in a page replacement operation of replacing the address translation information stored in the TLB, replacing address translation information corresponding to the dynamic page in preference to address translation information corresponding to the static page (¶[0065] – “the first L1 TLB 2121, the second L1 TLB 2122 and the L2 TLB 230 may evict a stored PTE. For example, the first L1 TLB 2121, the second L1 TLB 2122 and the L2 TLB 230 may sequentially evict PTEs in ascending order of hit frequency according to the least recently used (LRU) scheme so that other PTEs may be stored.”; the specification at ¶[0042] states “the static page may refer to a page that is frequently accessed by the OS”; thus, a ‘static’ page may be interpreted as a page having a higher hit frequency than a ‘dynamic’ page).
ZHANG, RAVAL, WATKINS, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, RAVAL, WATKINS, and RO before him or her, to modify the eviction order of a page table entry in a TLB of the combination of ZHANG, RAVAL, and WATKINS to include victim selection based on hit frequency as taught by RO. A motivation for doing so would have been to optimize use of the TLBs so that the most frequently used entries are kept in the TLB in hopes of maximizing the TLB hit rate (Abstract). Therefore, it would have been obvious to combine ZHANG, RAVAL, WATKINS, and RO to obtain the invention as specified in the instant claims.
With respect to Claim 15, the combination of ZHANG, RAVAL, and WATKINS disclose the operating method of claim 11.
ZHANG, RAVAL, and WATKINS may not explicitly disclose wherein the address translation information corresponding to the static page comprises address translation information corresponding to a virtual address accessed a threshold number of times or more.
However, RO discloses wherein the address translation information corresponding to the static page comprises address translation information corresponding to a virtual address accessed a threshold number of times or more (¶[0068] – “Each of PTEs configuring the page tables of the first and second L1 TLBs 2121 and 2122 may be configured to include a valid hit V, a count bit C, a tag and a physical page number PPN …The count bit C is a bit added to determine whether a corresponding page is a hot page”).
ZHANG, RAVAL, WATKINS, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, RAVAL, WATKINS, and RO before him or her, to modify the 1st and 2nd Level TLBs of the combination of ZHANG, RAVAL, and WATKINS to include maintaining count bits for page table entries as taught by RO. A motivation for doing so would have been to determine access counts for page table entries that may be used to optimize use of the TLBs according to the type of memory implementing the TLBs such that hot pages may be allocated to the fastest TLB improving overall system performance (¶[0028]). Therefore, it would have been obvious to combine ZHANG, RAVAL, WATKINS, and RO to obtain the invention as specified in the instant claims.
With respect to Claim 16, the combination of ZHANG, RAVAL, and WATKINS disclose the operating method of claim 11.
ZHANG, RAVAL, and WATKINS may not explicitly disclose storing, in the TLB, information distinguishing between address translation information corresponding to the static page and address translation information corresponding to the dynamic page.
However, RO discloses storing, in the TLB, information distinguishing between address translation information corresponding to the static page and address translation information corresponding to the dynamic page (¶[0068] – “Each of PTEs configuring the page tables of the first and second L1 TLBs 2121 and 2122 may be configured to include a valid hit V, a count bit C, a tag and a physical page number PPN …The count bit C is a bit added to determine whether a corresponding page is a hot page”; ‘static’ vs ‘dynamic’ pages may be identified or distinguished by count bit C).
ZHANG, RAVAL, WATKINS, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, RAVAL, WATKINS, and RO before him or her, to modify the 1st and 2nd Level TLBs of the combination of ZHANG, RAVAL, and WATKINS to include maintaining count bits for page table entries as taught by RO. A motivation for doing so would have been to determine access counts for page table entries that may be used to optimize use of the TLBs according to the type of memory implementing the TLBs such that hot pages may be allocated to the fastest TLB improving overall system performance (¶[0028]). Therefore, it would have been obvious to combine ZHANG, RAVAL, WATKINS, and RO to obtain the invention as specified in the instant claims.
With respect to Claim 17, the combination of ZHANG, RAVAL, and WATKINS disclose the operating method of claim 11.
ZHANG, RAVAL, and WATKINS may not explicitly disclose storing, in the TLB, information about a number of times a core of the at least one core accesses the address translation information.
However, RO discloses storing, in the TLB, information about a number of times a core of the at least one core accesses the address translation information (¶[0068] – “Each of PTEs configuring the page tables of the first and second L1 TLBs 2121 and 2122 may be configured to include a valid hit V, a count bit C, a tag and a physical page number PPN …The count bit C is a bit added to determine whether a corresponding page is a hot page”).
ZHANG, RAVAL, WATKINS, and RO are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, RAVAL, WATKINS, and RO before him or her, to modify the 1st and 2nd Level TLBs of the combination of ZHANG, RAVAL, and WATKINS to include maintaining count bits for page table entries as taught by RO. A motivation for doing so would have been to determine access counts for page table entries that may be used to optimize use of the TLBs according to the type of memory implementing the TLBs such that hot pages may be allocated to the fastest TLB improving overall system performance (¶[0028]). Therefore, it would have been obvious to combine ZHANG, RAVAL, WATKINS, and RO to obtain the invention as specified in the instant claims.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZHANG in further view of RAVAL, WATKINS, and HSU.
With respect to Claim 13, the combination of ZHANG, RAVAL, and WATKINS disclose the operating method of claim 11.
ZHANG, RAVAL, and WATKINS may not explicitly disclose starting a page table walk operation of searching a page table that stores address translation information, and based on the result of the first search operation being obtained, stopping the page table walk operation.
However, HSU discloses starting a page table walk operation of searching a page table that stores address translation information, and based on the result of the first search operation being obtained, stopping the page table walk operation (¶[0031] – “The processing device 100 may include more than two groups of processing units that share a memory and respective TLB hierarchies. In such case, a translation request of any processing unit that fails to be fulfilled with reference to TLB hierarchy with which that processing unit is associated can result in a probe of all or a subset of the other TLB hierarchies for the requested address translation. In one embodiment, if a hit is encountered in any probed TLB hierarchy, a page table walk is avoided. Alternatively, the probes may be issued in parallel with initiating the page table walk. In such case, if a translation hit is returned by any queried device, the page table walk is aborted or its response is ignored.”).
ZHANG, RAVAL, WATKINS, and HSU are analogous art because they are from the same field of endeavor of computing systems with virtual addressing. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of ZHANG, RAVAL, WATKINS, and HSU before him or her, to modify the virtual address resolution system of the combination of ZHANG, RAVAL, and WATKINS to include aborting searching a page table responsive to a TLB hit as taught by HSU. A motivation for doing so would have been to free computing resources used to conduct the page table search so that they may be allocated for other purposes. Therefore, it would have been obvious to combine ZHANG, RAVAL, WATKINS, and HSU to obtain the invention as specified in the instant claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ERIC T LOONAN/Primary Examiner, Art Unit 2137
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