DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/25/2025 was considered by the examiner.
Drawings
The drawings received on 02/07/2025 have been accepted by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 9-10, 12, 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by ZHOU [US 2019/0102291].
Claim 1, ZHOU discloses a system comprising: a plurality of storage devices; and a storage controller operatively coupled to the plurality of storage devices [Fig. 2], the storage controller external to the plurality of storage devices [microprocessor 108], the storage controller offloading management of the plurality of storage devices from respective storage device controllers, the storage controller comprising a processing device, the processing device configured to: associate a first number of blocks of a storage device of the plurality of storage devices to a first portion of the storage device and a second number of blocks of the storage device to a second portion of the storage device [par. 0043 wherein based on metadata, allocation to the nonvolatile or volatile memory occurs] based on one or more performance parameters associated with data resiliency [controller receives write command which includes descriptor metadata, Fig 3, steps S302-S306], the first portion associated with a different resiliency than the second portion [par. 0043]; receive a modification to the one or more performance parameters; and adjust the first number of blocks associated to the first portion and the second number of blocks associated with the second portion based on the modification to the one or more performance parameters [volatile and nonvolatile zones, wherein each is referred to the target zone depending on the information gathered from the write command, par. 0043].
Claim 2, ZHOU discloses the system of claim1, wherein the first portion is associated with a different programming mode than the second portion [volatile and nonvolatile zones, wherein each is referred to the target zone depending on the information gathered from the write command, par. 0043].
Claim 4, ZHOU discloses the system of claim 1, wherein the first portion of the storage device has a higher resiliency than the second portion of the storage device [volatile and nonvolatile zones, wherein each is referred to the target zone depending on the information gathered from the write command, par. 0043].
Claims 9-10, 12, 17-10 are rejected using the same rationale as claims 1-2, 4.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 11 are rejected under 35 U.S.C. 103 as being unpatentable over ZHOU [US 2019/0102291] in view of Wang et al. [US 2019/0042422].
Claim 3, ZHOU discloses the system of claim 1. ZHOU fails to teach, yet Wang et al. discloses the first portion is a single-level cell (SLC) memory and the second portion is a multi-level cell (MLC) memory [volatile and nonvolatile memory may be programmed as SLC, MLC, TLC, QLC among other configurations, par. 0028]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of ZHOU to include such configurations as disclosed by Wang et al. since these are all well known configurations for memory modules.
Claims 11 is rejected using the same rationale as Claim 3.
Claims 5, 13, 20 are rejected under 35 U.S.C. 103 as being unpatentable over ZHOU [US 2019/0102291] in view of Peterson et al. [US 2016/0188219].
Claim 5, ZHOU discloses the system of Claim 1. ZHOU does not teach but Peterson et al. discloses the one or more performance parameters associated with data stored at the storage device of the plurality of storage devices comprises a storage capacity of the system [write capacity metadata, par. 0097]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the metadata taught by ZHOU to include the storage capacity information as taught by Peterson et al. since doing so helps optimize data placement and allocation strategies.
Claims 13 and 20 are rejected using the same rationale as Claim 5.
Claims 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over ZHOU [US 2019/0102291] in view of Chen et al. [US 2018/0314550].
Claim 6, ZHOU discloses the system of claim 1. ZHOU fails to teach, yet Chen et al. discloses the one or more performance parameters associated with data stored at the storage device of the plurality of storage devices comprises a read/write latency of storage system operations performed by the system [claim 8]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the metadata taught by ZHOU to include the latency information as taught by Chen et al. since doing so helps in fine tuning the performance on the storage system.
Claim 14 is rejected using the same rationale as Claim 6.
Claims 7-8, 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over ZHOU [US 2019/0102291] in view of Navon et al. [US 2018/0276113].
Claim 7, ZHOU discloses the system of claim 1. ZHOU does not teach by Navon discloses the processing device is further to: allocate one or more blocks of the storage device to the first portion of the storage device upon determining that a number of program/erase cycles to program data to the one or more blocks exceeds a threshold [allocation based on program erase cycle status/threshold, par 0050]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the system of ZHOU to include the allocation parameters as disclosed by Navon since these facilitate efficient garbage collection.
Claim 8, ZHOU discloses he system of claim 1. ZHOU does not teach but Navon et al. discloses the processing device is further to: rotate which blocks of the storage device are allocated to the first portion and the second portion based on a number of program/erase cycles performed on each of the blocks [allocation based on program erase cycle status/threshold, par. 0050]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the system of ZHOU to include the allocation parameters as disclose by Navon since these facilitate efficient garbage collection.
Claims 15-16 are rejected using the same rationale as claims 7-8.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 3-9, 11-17, 19-20 of U.S. Patent No. 12236117. Although the claims at issue are not identical, they are not patentably distinct from each other because all of the limitations found in claims 1-20 of the instant application can be found in claims 1, 3-9, 11-17, 19-20 of U.S. Patent No. 12236117.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Prather et al. [US 10/489,316]; Method for Performing Multiple Memory Operations in Response to a Single Command and Memory Devices and Systems Employing the Same. See Abstract.
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/MIDYS ROJAS/ Primary Examiner, Art Unit 2133