DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 to 45 are presented for examination. The preliminary amendment filed 6-27-2025 cancelled claims 1 to 20 and added new claims 21 to 45.
Information Disclosure Statement
The references listed in the information disclosure statement submitted on 5-20-2026 have been considered by the examiner (see attached PTO-1449).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 21 to 45 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 21 recites the phrase “to support” on line 3, it is indefinite and unclear claim language. The claim limitation indicated that the physical layer circuitry to support transport of flits, it is not clear how the circuitry supports transport of flits.
Independent claims 33 and 36 have similar limitation and are also rejected for the same rational applied to claim 21.
Dependent claims 22 to 32, 24 to 35 and 37 to 45 are also rejected due to their dependency on a rejected base claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
Claims 21 to 26, 30 to 32 and 36 to 45 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tune et al. (USPAP 2019/0363829).
Claims 21 and 36:
Tune teaches a method and an apparatus for an interconnection network for providing data transfer between a plurality of nodes of an integrated circuit, the apparatus comprising: transmitting a primary payload in units called packets on a primary network. Tune teaches that each packet comprises a header and packet payload wherein the header is defined according to a network protocol that defines multiple layers of signals (see par. 0040). Tune teaches that the multiple layers are such as physical layer signals and link layer signals (see par. 0040).
Tune teaches that each packet may comprise a certain number of flits where a “flit” is the smallest unit of information for which the network can control routing independently from other flits (see par. 0041). Tune teaches that in some cases each flit may have a fixed size/number of bits (see par. 0042). Tune teaches that some networks may support packets with variable number of flits of variable size (see par. 0043). Tune teaches that a source endpoint may calculate the first error check code as a packet check code for checking contents of the entire packet and each flit may itself be divided into a number of flit sections and each flit may include a variable number of flit sections (see par. 0044 to 0045). Tune teaches an interconnect (6) comprises multiple routers (44) for coupling a master interface/ source endpoint (46) to a number of destination interfaces/destination endpoint (see par. 0060). Tune teaches that the system interconnect is implemented as a network on chip (NoC) and where a reduced redundant version of intermediate NoC components such as routers are provided, in which control logic is replicated but instead of payload, only error detecting code is processed (see par. 0060 and 0080). Tune also teaches that some network control signals such as physical layer (PHY) signals are replicated as used as inputs to the redundant versions (see par. 0080).
Tune teaches that a source endpoint comprises a primary payload (104) and a redundant payload (110) both having a first error check code (112) and being mapped to packets on different virtual channels (see fig. 3A and par. 0082). Tune teaches that the first error check code may be a CRC check code computed based on at least a portion of the primary payload (see par. 0076). Tune teaches that the destination node (48) computes a second error check code (114) when the primary payload reaches the destination endpoint and compares the second computed error check code against the first error check code which it receives (see par. 0077).
Tune teaches that if there is a mismatch from the comparison then a fault is signaled and a fault handling response triggered (see par. 0077). Tune teaches that the endpoints (46, 48) could have buffers (118) and each network component may hold packets or flits within the buffer associated with a given virtual channel until the arbiter allows the given virtual channel to have another time slot on the shared physical channel (see par. 0081). Tune teaches that both the ingress port and the egress port include the check code calculating circuitry (see par. 0005 and 0023).
As per claims 22 to 24, and 37 to 38, Tune teaches that the primary payload may be transmitted on the primary network in units called packets and each packet comprises a header wherein the header could be defined according to a network protocol (see par. 0040). Tune teaches that redundant payload could be transmitted in a single flit or a single section and a redundant payload protocol mirrors the number of flits in the primary payload (see par. 0048). Tune teaches that a PCI express and/or PCIe are used in connecting the source endpoint to the destination endpoint over the interconnect (see par. 0056).
As per claims 25 to 26, 39 and 40, Tune teaches that some networks may support packets with variable number of flits of variable size (see par. 0043). Tune teaches that in packet format having a single flit, that flit acts as a header flit (120-H) and having one or more flit sections. Tune also teaches a tail flit (120-T) and if a packet has two flits, then the packet contains one or more intermediate flits (see fig. 4 and par. 0094).
As per claim 30, Tune teaches that the redundant payload may use a different packet format to the primary payload where the primary payload uses a packet format of F flits per packet and N flit sections (122) per flit (see par. 0099). Tune also teaches that the first check code may be provided in the tail flit (120-T) of a packet, as it may be calculated convolutionally as each flit is processed and transmitted (see par. 0100). Tune teaches that the first check code may comprise 6 bits or 8 bits (see par. 0076 and 0087).
As per claims 31 to 32, 41 and 45, Tune teaches that a CRC value (“first CRC”) and a new CRC value (“second CRC” are computed using an equation and a matrix multiplier block (see fig. 7 and par. 0107et seq.). Tune teaches that the ingress port may have various buffers (“retimer”) for buffering tracking information relating to requests and buffering responses to the request (see par. 0065).
As per claims 42 to 44, Tune teaches that the endpoint (2) is a system-on chip having multiple master devices such as one or more central processing units (CPUs), graphics processing unit (GPU) (“hardware accelerator”) and a flash and SRAM (see fig. 1 and par. 0056 et seq.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 33 to 34 are rejected under 35 U.S.C. 103 as being unpatentable over Tune et al..
Claim 33:
Tune substantially teaches the claimed invention. Tune teaches a method and an apparatus for an interconnection network for providing data transfer between a plurality of nodes of an integrated circuit, the apparatus comprising: transmitting a primary payload in units called packets on a primary network. Tune teaches that each packet comprises a header and packet payload wherein the header is defined according to a network protocol that defines multiple layers of signals (see par. 0040). Tune teaches that the multiple layers are such as physical layer signals and link layer signals (see par. 0040).
Tune teaches that each packet may comprise a certain number of flits where a “flit” is the smallest unit of information for which the network can control routing independently from other flits (see par. 0041). Tune teaches that in some cases each flit may have a fixed size/number of bits (see par. 0042). Tune teaches that some networks may support packets with variable number of flits of variable size (see par. 0043).
Tune teaches that a source endpoint may calculate the first check code as a packet check code for checking contents of the entire packet and each flit may itself be divided into a number of flit sections and each flit may include a variable number of flit sections (see par. 0044 to 0045). Tune teaches an interconnect (6) comprises multiple routers (44) for coupling a master interface/ source endpoint (46) to a number of destination interfaces/destination endpoint (see par. 0060). Tune teaches that the system interconnect is implemented as a network on chip (NoC) and where a reduced redundant version of intermediate NoC components such as routers are provided, in which control logic is replicated but instead of payload, only error detecting code is processed (see par. 0060 and 0080). Tune also teaches that some network control signals such as physical layer (PHY) signals are replicated as used as inputs to the redundant versions (see par. 0080).
Tune teaches that a source endpoint comprises a primary payload (104) and a redundant payload (110) both having a first error check code (112) and being mapped to packets on different virtual channels (see fig. 3A and par. 0082). Tune teaches that the first check code may be a CRC check code computed based on at least a portion of the primary payload (see par. 0076).
Tune teaches that the destination node (48) computes a second check code (114) when the primary payload reaches the destination endpoint and compares the second computed check code against the first error check code which it received (see par. 0077). Tune teaches that if there is a mismatch from the comparison then a fault is signaled and a fault handling response triggered (see par. 0077). Tune teaches that the endpoints (46, 48) could have buffers (118) and each network component may hold packets or flits within the buffer associated with a given virtual channel until the arbiter allows the given virtual channel to have another time slot on the shared physical channel (see par. 0081).
Tune fails to specifically teach the limitation of “selecting one of first cyclic redundancy check (CRC) circuitry or second CRC circuitry of a physical layer to decode the CRC value in the flit;” however, the teaching of this limitation is obvious to the teachings of Tune because Tune teaches that a state decoder (154) decodes the flit validity information to determine the number of valid flit sections (see par. 0108). Tune teaches that the circuit for computing the CRC values utilizes an XOR tree (150) to provide the new CRC value (see par. 0108).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Tune to include the limitation of: “selecting one of first cyclic redundancy check (CRC) circuitry or second CRC circuitry of a physical layer to decode the CRC value in the flit;” because Tune teaches a circuit that prevents recalculating check codes includes performing coalescing of valid flits using a state decoder. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a method and an apparatus for limiting the need to recalculate check codes by coalesce the valid flit sections as taught by Tune (see par. 0105).
As per claim 34, Tune teaches that a PCI express and/or PCIe are used in connecting the source endpoint to the destination endpoint over the interconnect (see par. 0056).
Claims 27 to 29 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Tune et al. in view of Sikkink et al (USPAP 2016/0373557).
As per claims 27 to 29 and 35, Tune fails to specifically teach that the flit format has a flit length less than 256B, the port further comprises forward error correction (FEC) circuitry; and including the FEC and CRC values withing flits of first flit format; however, Sikkink in an analogous art teaches a method and an apparatus for high performance computers with both low latency and high bandwidth, the apparatus comprising: a low latency flit having a total length of 152 bits (see par. 0085). Sikkink also teaches that all the bits in each flit are serialized and transmitted in a defined order and the receiver may determine whether a transmission is NRZ or PAM4 based on symbol counting (see par. 0155). Sikkink further teaches that in the PAM4 detection the overhead of strong forward error correction (FEC) and strong CRC are considered (see par. 0157).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Tune to include the flit length of a 152bits and considering strong FEC and strong CRC for a PAM4 detection of Sikkink because Sikkink teaches combating higher error rates when transmitting flits considers the strong FEC and strong CRC in the payload fields. This modification would have been obvious because a person of ordinary skill in the art would have been motivated to employ a method and an apparatus for combating noise in transmitting flits by considering a strong FEC and a strong CRC (see par. 0157).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nicol et al. (USPAP 2018/0145913) discloses an apparatus and a method for adaptive routing for link-level retry protocol.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHELLY A CHASE whose telephone number is (571)272-3816. The examiner can normally be reached Mon-Thu 8:00-5:30, 2nd Friday 8:00-4:30.
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/Shelly A Chase/ Primary Examiner, Art Unit 2112
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