DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-8, 12-16 and 18-20 are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Randlisek (US 2022/0050488)
Regarding claim 1, Randlisek discloses an interface circuit [100, fig. 1] comprising: an interface input [input 164] electrically coupled to a node [164]; a current mirror [102] comprising: a current mirror input [108] configured to receive a reference current [reference current at 108]; and a first current mirror output [116] configured to provide a return current [162] in proportion to the reference current; an input circuit path [104 through 120/160/126/156 and R2] electrically coupled between the interface input and the current mirror input and configured to conduct the reference current; and a return circuit path [106 through 118/122/162/128/R1/ground] electrically coupled to the input circuit path at the node and configured to conduct the return current [par. 0030-0043].
Regarding claim 4, Randlisek discloses [fig. 1] wherein the current mirror is configured to receive the reference current at the current mirror input via the input circuit path [104] and to provide the return current from the first current mirror output to the interface input via the return circuit path.
Regarding claim 5, Randlisek discloses [fig. 1] wherein an input impedance of the interface input is determined, at least in part, by an impedance of the input circuit path and by a return ratio of the return current to the reference current [par. 0030-0043].
Regarding claim 6, Randlisek discloses [fig. 1] wherein the input impedance decreases as the return ratio increases [a higher return ratio is the closed loop path has lower impedance].
Regarding claim 7, Randlisek discloses [fig. 1] wherein the input circuit path comprises a P-channel field-effect transistor (PFET) [par. 0064, see also fig. 6].
Regarding claim 8, Randlisek discloses [fig. 1] wherein the PFET is configured to receive a fixed reference voltage [Vcc].
Regarding claim 12, Randlisek discloses [fig. 1] further comprising an interface output electrically coupled to a second current mirror output [Vo] and configured to provide an output current [current output at V0] proportional to the reference current.
Regarding claim 13, Randlisek discloses [fig. 1] wherein the current mirror further comprises: a diode connected N-channel field-effect transistor (NFET) [120] configured to receive the reference current and to generate a gate voltage [gate voltage 120]; and a first NFET [122] configured to receive the gate voltage and to provide the return current.
Regarding claim 14, Randlisek discloses a closed loop system [100] comprising: a system input [input 164]; a current mirror [102] comprising: a first field-effect transistor (FET) [120] configured to receive a reference current [reference current at 108]; and a second FET [122] configured to provide a return current [162], wherein a gate of the first FET [gate 120] is electrically coupled to a gate of the second FET [gate 122]; an input circuit path [104 through 120/160/126/156 and R2] electrically coupled between a drain of the first FET [110] and the system input and configured to conduct the reference current; and a return circuit path [path 106 through 122/116/136/128/138 and R1] electrically coupled between a drain of the second FET [116] and the system input and configured to conduct the return current such that an impedance of the closed loop system is less than an impedance of the input circuit path and determined [impedance of the close loop is less than return path], at least in part, by a return ratio [see par. 0030-0043].
Regarding claim 15, Randlisek discloses wherein an input current of the closed loop system [input 100, fig. 1] is determined, at least in part, by a sum of the return current and the reference current [resistor R1 carries the sum of the current 160 and the current 162, par. 0041-0045] , and the return ratio is determined, at least in part, by a ratio of the return current to the reference current [par. 0030-0045].
Regarding claim 16, Randlisek discloses [fig. 1] wherein the first FET is a diode connected transistor [120, fig. 1] configured to receive the reference current, and in response to provide a reference voltage [voltage at 110]; and the second FET is configured to receive the reference voltage and to provide the return current.
Regarding claim 18, Randlisek discloses [fig. 1] wherein the first FET is a diode connected P-channel field-effect transistor (PFET) [par. 0064, fig. 6].
Regarding claim 19, Randlisek discloses [fig. 1] wherein the reference voltage is determined, at least in part, by a transconductance of the first FET [diode connected transistor 120 uses its transconductance to convert current into a voltage]; and the return current is determined, at least in part, by a transconductance of the second FET [162 is determined by the transconductance of transistor 122].
Regarding claim 20, Randlisek discloses [fig. 1] wherein the return ratio is determined, at least in part, by a ratio of the transconductance of to the second FET to the transconductance of the first FET [ratio is determined by 120 and 122].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Randlisek in view of Jurgilewiez et al. (US 2006/0033539 and Jurgilewiez hereinafter).
Regarding claims 2 and 3, Randlisek discloses all the features with respect to claim 1 as outlined above. Randlisek further discloses input circuit path resistor [R2] and the return circuit path resistor [R1]. Randlisek does not explicitly disclose wherein the input circuit path and the return circuit path comprises an electrostatic discharge (ESD) resistor.
However, Jurgilewiez discloses [fig, 7] an electrostatic discharge (ESD) resistor [751/752/753, par. 0054-0055]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Randlisek by incorporating ESD resistor to be included in the input and return path of current mirror as taught in Jurgilewiez in order to utilize well-known ESD protection in order to prevent damages in the structure of the circuit.
Claims 10-11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Randlisek.
Regarding claim 10, Randlisek discloses all the features with respect to claim 4 as outlined above. Randlisek further discloses 120 and mirror transistor 122 are implemented as FETs, [par. 0064]. Randlisek does not explicitly disclose wherein N- channel field-effect transistor (NFET). Randlisek uses PFET transistors [fig. 6] instead of NFET, these are just different types of transistors and thus it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to substitute one type of transistor for the other in the absence of unexpected results in order to have an optimum working condition for the circuit since this practice is well known in the art.
Regarding claim 11, Randlisek discloses wherein the NFET is configured to receive a bias voltage [voltage at base 120] and to limit the reference current.
Regarding claim 17, Randlisek discloses all the features with respect to claim 16 as outlined above. Randlisek further discloses 120 and mirror transistor 122 are implemented as FETs, [par. 0064]. Antunes does not explicitly disclose first NFET. Antunes uses PMOS [fig. 6] instead of NFET transistors, these are just different types of transistors and thus it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to substitute one type of transistor for the other in the absence of unexpected results in order to have an optimum working condition for the circuit since this practice is well known in the art.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Randlisek in view of Moyer (US 5737170).
Regarding claim 9, Randlisek discloses all the features with respect to claim 7 as outlined above. Randlisek does not explicitly disclose wherein the PFET is configured to open the input circuit path during a thermal shutdown (TSD) condition.
However, Moyer discloses [see figs. 8-9] a thermal shutdown circuit employed in an integrated circuit. It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Randlisek by incorporating thermal shutdown as taught in Moyers in order to protect the integrated circuit [cl. 3, ln. 5-12].
Response to Arguments
Applicant’s arguments with respect to claim(s) 1and 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/METASEBIA T RETEBO/ Primary Examiner, Art Unit 2836
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