DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 10-12, 20 are rejected under 35 U.S.C. 103 as being unpatentable over HE (US 2021/0199710 A1 hereinafter “HE”) in view of Wang (US 2012/0256649 A1 hereinafter “Wang”) and further in view of Fleury (US 6,822,471 B2 hereinafter “Fleury”).
As to claim 1, HE discloses in Figs. 1, 3A, 7:
acquiring a plurality of testing block measurement temperatures of the testing block when the testing block is processed by a DVS testing flow (wafer 110 / IC 112 processed by stress signal 312 of Fig. 3A in method 700 operations 712, 714, 716, 718; “the CAVS may be applied in chip probing flow, final test flow, or wafer acceptance test flow at room temperature range (about 25° C. to about 27° C.), or temperature range from about 0° C. to about −40° C., or temperature range from 0° C. to about 125° C.”);
generating a DVS block voltage for applying to the testing block in the die of the wafer based on the DVS block target temperature (signal generator 102, coupler 104, probes 101 apply stress to IC 112 on wafer 110; “A stress signal 312 of the dynamic voltage stress (DVS) test is applied in a single test period 310”; “The stress signal 312 is composed of a single-sequence signal, which includes a ramp-up stage rising from ground 313 to a test voltage 311”; “The second voltage level 222 is higher than the first voltage level 200”).
HE does not disclose selecting a testing block from a plurality of testing blocks in a die of a wafer; acquiring a correlation table of the plurality of testing block measurement temperatures and a plurality of DVS block predict temperatures of the testing block; configuring a tip burnt block temperature based on the plurality of testing block measurement temperatures; or determining a DVS block target temperature selected from the DVS block predict temperatures based on the correlation table and the tip burnt block temperature.
However, Wang discloses acquiring a correlation table of the plurality of testing block measurement temperatures and a plurality of DVS block predict temperatures of the testing block (“The criteria may be expressed using equations, a database, lookup tables, or the like. Table 1 illustrates an exemplary lookup table, which includes the test conditions and the dynamic specifications as functions of temperatures and/or stresses.”);
configuring a tip burnt block temperature based on the plurality of testing block measurement temperatures (“sensors 14a and/or 14b in bottom die 14 are used to measure the temperature and the stress, respectively, of bottom die 14”; thermal sensor 18a of top die 18; prober chuck 12);
determining a DVS block target temperature selected from the DVS block predict temperatures based on the correlation table and the tip burnt block temperature (“Assuming the temperature of bottom die 14 is 104° C., from Table 1, it is found that 104° C. correspond to the temperature range of 100.1° C. to 120° C. Accordingly, the dynamic test conditions are found as including ‘pattern_c, voltage_d, timing_e,’ etc.”).
Fleury discloses selecting a testing block from a plurality of testing blocks in a die of a wafer (die 2 on wafer 10, Figs. 1, 4; computer controller 52; “segregating the integrated semiconductor devices on the wafer by measuring a parameter of the devices”; “a first voltage at a value higher than the device normal operating voltage is applied to the devices with a first measured operational speed, and a second voltage at a value lower than the first voltage is applied to the devices with a second measured operational speed”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the method of HE and implement selecting a testing block from a plurality of testing blocks in a die of a wafer, acquiring a correlation table of the plurality of testing block measurement temperatures and a plurality of DVS block predict temperatures of the testing block, configuring a tip burnt block temperature based on the plurality of testing block measurement temperatures, determining a DVS block target temperature selected from the DVS block predict temperatures based on the correlation table and the tip burnt block temperature, and generating a DVS block voltage for applying to the testing block in the die of the wafer based on the DVS block target temperature, as taught by Wang and Fleury, for replacing HE’s single DVS test voltage 311 with a temperature-indexed, parameter-adjusted stress voltage.
As to claim 2, Fleury discloses adjusting the DVS block voltage for applying to another testing block in the die of the wafer; wherein the die of the wafer comprises a plurality of testing blocks, and the plurality of testing blocks are applied with different DVS block voltages (die 2 on wafer 10; “a first voltage at a value higher than the device normal operating voltage is applied to the devices with a first measured operational speed, and a second voltage at a value lower than the first voltage is applied to the devices with a second measured operational speed”).
HE further discloses different stress levels on the same DUT (first voltage level 200, second voltage level 222, third voltage level 224, test voltage 311).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the method of HE as combined with Wang and Fleury and implement adjusting the DVS block voltage for applying to another testing block in the die of the wafer, wherein the die of the wafer comprises a plurality of testing blocks, and the plurality of testing blocks are applied with different DVS block voltages, as taught by Fleury, for applying a higher stress voltage to one device/region and a lower stress voltage to another.
As to claims 10, 20, HE discloses increasing the DVS block voltage or increasing a DVS time duration so as to approach the DVS block target temperature to a tip burnt block temperature; wherein when the DVS block voltage or the DVS time duration is increased, a power of testing blocks is increased so as to increase the DVS block target temperature (“The second voltage level 222 is higher than the first voltage level 200. … The second voltage level 222 may be about 1.3 times higher, about 1.58 times higher, about 2.0 times higher, or about 3.0 times higher than the first voltage level 200”; stress signal 312 rises to test voltage 311 in test period 310).
Fleury discloses applying a first voltage higher than normal operating voltage.
Wang discloses selecting voltage_d from Table 1 at the measured temperature.
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the method of HE as combined with Wang and Fleury and implement increasing the DVS block voltage or increasing a DVS time duration so as to approach the DVS block target temperature to a tip burnt block temperature, wherein when the DVS block voltage or the DVS time duration is increased, a power of testing blocks is increased so as to increase the DVS block target temperature, as taught by HE raising stress from first voltage level 200 to second voltage level 222 / test voltage 311.
As to claim 11, HE discloses in Figs. 1, 3A, 7:
at least one wafer testing station (system 100; “the system 100 may be automatic test equipment (ATE)”; signal generator 102, coupler 104, probes 101, wafer 110, IC 112);
a processor coupled to … the at least one wafer testing station (module 106: “configured to determine whether the IC complies with a test criterion after the stress signal is applied”; method 700 operations 712, 714, 716, 718);
wherein the processor acquires a plurality of testing block measurement temperatures of the testing block from the at least one wafer testing station when the testing block is processed by a DVS testing flow (IC 112 on wafer 110 processed by stress signal 312 / test voltage 311 at the chip probing / final test / wafer acceptance temperature ranges quoted above);
and the processor generates a DVS block voltage for applying to the testing block in the die of the wafer based on the DVS block target temperature (signal generator 102 generates stress signal 312; probes 101 apply test voltage 311).
HE does not disclose a memory; the processor selects a testing block from a plurality of testing blocks in a die of a wafer; the processor acquires a correlation table of the plurality of testing block measurement temperatures and a plurality of DVS block predict temperatures of the testing block, the correlation table is saved in the memory; the processor configures a tip burnt block temperature based on the testing block measurement temperatures; or the processor determines a DVS block target temperature selected from the DVS block predict temperatures based on the correlation table and the tip burnt block temperature.
However, Wang discloses the processor acquires a correlation table of the plurality of testing block measurement temperatures and a plurality of DVS block predict temperatures of the testing block, the correlation table is saved in the memory (“Table 1 illustrates an exemplary lookup table, which includes the test conditions and the dynamic specifications as functions of temperatures and/or stresses.”);
the processor configures a tip burnt block temperature based on the testing block measurement temperatures (“sensors 14a and/or 14b in bottom die 14 are used to measure the temperature and the stress, respectively, of bottom die 14”);
the processor determines a DVS block target temperature selected from the DVS block predict temperatures based on the correlation table and the tip burnt block temperature (“Assuming the temperature of bottom die 14 is 104° C., from Table 1, it is found that 104° C. correspond to the temperature range of 100.1° C. to 120° C. Accordingly, the dynamic test conditions are found as including ‘pattern_c, voltage_d, timing_e,’ etc.”).
Fleury discloses a memory (failure analysis memory device 40; memory devices 40, Fig. 4);
a processor coupled to the memory and the at least one wafer testing station (“an automated test equipment (ATE) system, which includes in part, a computer controller 52 and memory devices 40”; pin card 12; parameter measurement device 15; wafer 10);
the processor selects a testing block from a plurality of testing blocks in a die of a wafer (computer controller 52 segregates die 2 on wafer 10 and applies a first or second stress voltage).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of HE and implement a memory; a processor coupled to the memory and the at least one wafer testing station; wherein the processor selects a testing block from a plurality of testing blocks in a die of a wafer, the processor acquires a correlation table of the plurality of testing block measurement temperatures and a plurality of DVS block predict temperatures of the testing block, the correlation table is saved in the memory, the processor configures a tip burnt block temperature based on the testing block measurement temperatures, the processor determines a DVS block target temperature selected from the DVS block predict temperatures based on the correlation table and the tip burnt block temperature, and the processor generates a DVS block voltage for applying to the testing block in the die of the wafer based on the DVS block target temperature, as taught by Wang and Fleury.
As to claim 12, Fleury discloses wherein the processor adjusts the DVS block voltage for applying to another testing block in the die of the wafer, the die of the wafer comprises a plurality of testing blocks, and the plurality of testing blocks are applied with different DVS block voltages (computer controller 52; die 2; wafer 10; first voltage and second voltage as quoted under claim 2).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to modify the system of HE as combined with Wang and Fleury and implement the different-voltage limitation of claim 12, as taught by Fleury.
Allowable Subject Matter
Claims 3-9; and 13-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claims 3-9; and 13-19, the prior art in record in alone and in combination does not disclose generating the plurality of DVS block predict temperatures of the testing block to establish the correlation table by a machine learning architecture based on the pre-DVS data, the plurality of DVS block voltages and the plurality of DVS time durations; as recited in claims 3-9; 13-19.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUNG X NGUYEN whose telephone number is (571)272-1967. The examiner can normally be reached 10:30am-6:30pm M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Judy Nguyen can be reached at 571-272-2258. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TUNG X NGUYEN/ Primary Examiner, Art Unit 2858 9/29/2026
Prosecution Insights