Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claims 1-8 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-8 of U.S. Patent No. 12,253,557 in view of Kawaura (Pat# 7,821,285).
Pending application SN# 19/048,995 U.S. Pat # 12,253,557
1. An electronic device, comprising: a pixel array; a plurality of signal lines, electrically connected to the pixel array; and a testing circuit, comprising a plurality of output channels electrically connected to some of the plurality of signal lines and a plurality of switches, wherein the plurality of switches are connected to the plurality of signal lines via the plurality of output channels, wherein the plurality of output channels of the testing circuit are less than the plurality of signal lines in quantity, and there are at least two via holes overlapping one of the plurality of output channels.
2. The electronic device of claim 1, wherein one of the at least two via holes is electrically connected to a first metal layer, and another one of the at least two via holes is electrically connected to a second metal layer, wherein the first metal layer and the second metal layer are not directly electrically connected.
3. The electronic device of claim 1, wherein the plurality of switches are controlled according to a plurality of control signals.
4. The electronic device of claim 1, further comprising: an isolation circuit, located between the testing circuit and the plurality of signal lines.
5. The electronic device of claim 4, wherein the isolation circuit comprises: a plurality of other switches, wherein one of the plurality of other switches is electrically connected between one of the plurality of output channels and one of the plurality of signal lines.
6. The electronic device of claim 5, wherein adjacent two of the plurality of other switches are electrically connected to the same one of the plurality of output channels, and are respectively electrically connected to adjacent two of the plurality of signal lines.
7. The electronic device of claim 5, wherein adjacent two of the plurality of other switches are respectively electrically connected to adjacent two of the plurality of output channels.
8. The electronic device of claim 5, wherein the isolation circuit comprises: a control signal input terminal, electrically connected to a control terminal of at least one of the plurality of other switches.
1. An electronic device, comprising: a plurality of signal lines; and a testing circuit, comprising a plurality of output channels electrically connected to some of the plurality of signal lines and a plurality of switches, wherein the plurality of switches are connected to the plurality of signal lines via the plurality of output channels, wherein the plurality of output channels of the testing circuit are less than the plurality of signal lines in quantity, and there are at least two via holes overlapping one of the plurality of output channels.
2. The electronic device of claim 1, wherein one of the at least two via holes is electrically connected to a first metal layer, and another one of the at least two via holes is electrically connected to a second metal layer, wherein the first metal layer and the second metal layer are not directly electrically connected.
3. The electronic device of claim 1, wherein the plurality of switches are controlled according to a plurality of control signals.
4. The electronic device of claim 1, further comprising: an isolation circuit, located between the testing circuit and the plurality of signal lines.
5. The electronic device of claim 4, wherein the isolation circuit comprises: a plurality of other switches, wherein one of the plurality of other switches is electrically connected between one of the plurality of output channels and one of the plurality of signal lines.
6. The electronic device of claim 5, wherein adjacent two of the plurality of other switches are electrically connected to the same one of the plurality of output channels, and are respectively electrically connected to adjacent two of the plurality of signal lines.
7. The electronic device of claim 5, wherein adjacent two of the plurality of other switches are respectively electrically connected to adjacent two of the plurality of output channels.
8. The electronic device of claim 5, wherein the isolation circuit comprises: a control signal input terminal, electrically connected to a control terminal of at least one of the plurality of other switches.
As to claim 1, claim 1 of U.S. Patent No. 12,253,557 disclose an electronic including the limitation of the instant claim 1withouut a pixel array.
Kawaura et al disclose a test apparatus having a testing circuit (40) with signal lines connected to a pixel array (10) as shown in figure 1.
It would have been well known for one of ordinary skill in the art to have the electronic circuit of U.S. Patent No. 12,253,557 connected to a pixel array as taught by Kawaura et al for the purpose of testing pixels within the pixel array.
As to claims 2-8, claims 2-8 of U.S. Patent No. 12,253,557 disclose the limitations of the instant claims 2-8.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee et al (Pat# 11,455,924) disclose System And Method For LCD Display Panel Failure Diagnostics.
Kim et a l (Pat# 9,925,585) disclose Display Device And Method Of Testing The Same.
Liquid Crystal Display Apparatus And Testing Method For Liquid Crystal Display Apparatus.
Nakano et al (Pat# 7,091,738) disclose Inspection System For Active Matrix Panel, Inspection Method For Active Matrix Panel And Manufacturing Method For Active Matrix OLED Panel.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINH P NGUYEN whose telephone number is (571)272-1964. The examiner can normally be reached M-F 6:00am-4:00pm.
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/VINH P NGUYEN/Primary Examiner, Art Unit 2858
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