DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
2. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
3. Claim 11 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 11, the claim limitation “…wherein the phase detector and the low-pass filter are configured to provide a third signal having a second frequency that is a multiple of the first frequency.” is being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention because the claim doesn’t clearly state how the phase detector and the low pass filter would provide a third signal having a second frequency that is a multiple of the first frequency since the phase detector is for detecting phase differences and the low-pass filter is for filtering unwanted signals, and they are not appeared to be configured to provide a third signal having a second frequency that is a multiple of the first frequency. Thus, the claim should clearly define what is providing a third signal having a second frequency that is a multiple of the first frequency.
Double Patenting
4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
5. Claims 1-10 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-9 of U.S. Patent No. 12,224,708. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims 1-10 are anticipated in the claims 1-9 of the U.S. Patent No. 12,224,708.
6. Claims 12-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 11-14 of U.S. Patent No. 12,224,708. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims 12-16 are anticipated in the claim 11-14 of the U.S. Patent No. 12,224,708.
7. Claims 17-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 17-21 of U.S. Patent No. 12,224,708. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims 17-21 are anticipated in the claims 17-21 of the U.S. Patent No. 12,224,708.
8. Claim 22 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 23 of U.S. Patent No. 12,224,708. Although the claims at issue are not identical, they are not patentably distinct from each other because the claim 22 is anticipated in the claims 23 of the U.S. Patent No. 12,224,708.
9. Claims 25-27 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 24-26 of U.S. Patent No. 12,224,708. Although the claims at issue are not identical, they are not patentably distinct from each other because the claims 25-27 are anticipated in the claims 24-26 of the U.S. Patent No. 12,224,708.
Claim Rejections - 35 USC § 102
10. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
11. Claims 1-3 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hiebert et al. (2016/0352341) (hereinafter “Hiebert”).
Regarding claim 1, Hiebert discloses an apparatus (Fig.12, please refer to the whole reference for detailed), comprising: a first oscillator circuit (1210) having first oscillator terminals (+ and - terminals “OUT1”) and a first control terminal (first control terminal of 1210 which received “Master VCTRL”); and a second oscillator circuit (1212) having second oscillator terminals (+ and - terminals “OUT2”) and a second control terminal (second control terminal of 1212 which received “VCO2 SLAVE VCTRL”), in which the first oscillator terminals are coupled to the second oscillator terminals (via 1220 in Fig.12); a phase detector (“PFD” of 1262) having a first detector input (first detector input of the “PFD” connected to “Buff_Out1”), a second detector input (second detector input of the “PFD” connected to “Buff_Out2”), and a detector output (detector output from the “PFD” of 1262, which is connected to LPF), the first detector input coupled to one of the first oscillator terminals (“OUT1” via 1211), and the second detector input coupled to one of the second oscillator terminals (“OUT2” via 1213); and a low-pass filter (“LPF” of 1262) coupled between the detector output (detector output from the “PFD”) and one of the first control terminal of the first oscillator circuit or the second control terminal (second control terminal which received “VCO2 SLAVE VCTRL”) of the second oscillator circuit.
Regarding claim 2, Hiebert discloses a first circuit (please refer to Examiner’s note “first circuit” in Hiebert’s Fig.12 below) having first inputs (first inputs received OUT1) and first outputs (first outputs which are output of the first circuit), the first inputs coupled to the first oscillator terminals (OUT1), and the first outputs coupled to the second oscillator terminals (OUT2); and a second circuit (please refer to Examiner’s note “second circuit” in Hiebert’s Fig.12 below) having second inputs (second inputs received OUT2) and second outputs (second outputs which are output of the second circuit), the second inputs coupled to the second oscillator terminals (OUT2), and the second outputs coupled to the first oscillator terminals (OUT1 via the first circuit).
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Regarding claim 3, Hiebert discloses the first circuit (please refer to Fig.12 in claim 2 above) includes at least one of a capacitor, a resistor, a buffer (the first circuit is a buffer; ¶ 86), an attenuator, or a transconductance amplifier coupled between each of the first inputs (OUT1) and a respective one of the first outputs (outputs of the first circuit); and wherein the second circuit (please refer to Fig.12 in claim 2 above) includes at least one of a capacitor, a resistor, a buffer (the second circuit is a buffer; ¶ 86), an attenuator, or a transconductance amplifier coupled between each of the second inputs (OUT2) and a respective one of the second outputs (outputs of the second circuit).
Regarding claim 6, Hiebert discloses a third oscillator circuit (1214) having third oscillator terminals (OUT3) coupled to the first oscillator terminals (OUT3 is coupled to OUT1 via 1220).
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12. Claims 12 and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ravi et al. (6,639,481) (hereinafter “Ravi”).
Regarding claim 12, Ravi discloses an apparatus (Fig.2, please refer to the whole reference for detailed), comprising: a first oscillator (12 in Fig.2) having first oscillator terminals (6 and 8); a second oscillator (52) having second oscillator terminals (76 and 78); and a first circuit (25) having first inputs (P+ and P- of 25) and first outputs (S+ and S- of 25), the first inputs (P+ and P- of 25) coupled to the first oscillator terminals (6 and 8), the first outputs (S+ and S- of 25) coupled to the second oscillator terminals (76 and 78, coupled via 68 and 74, respectively), the first circuit (25) including a first transformer (25) coupled between the first inputs (P+ and P- of 25) and the first outputs (S+ and S- of 25); and a second circuit (27) having second inputs (P+ and P- of 27) and second outputs (S+ and S- of 27), the second inputs (P+ and P- of 27) coupled to the second oscillator terminals (76 and 78), the second outputs (S+ and S- of 27) coupled to the first oscillator terminals(6 and 8, coupled via 28 and 34, respectively), the second circuit (27) including a second transformer (27) coupled between the second inputs (P+ and P- of 27) and the second outputs (S+ and S- of 27).
Regarding claim 22, Ravi discloses an apparatus (Fig.2, please refer to the whole reference for detailed) comprising: a first oscillator circuit (12 in Fig.2) having a first terminal (6) and a second terminal (8); a second oscillator circuit (52) having a third terminal (78) and a fourth terminal (76); a first circuit (25) having a first positive input (P+ of 25), a first negative input (P- of 25), a first positive output (S+ of 25), and a first negative output (S- of 25), the first positive input (P+ of 25) coupled to the first terminal (6), the first negative input (P- of 25) coupled to the second terminal (8), the first positive output (S+ of 25) coupled to the third terminal (78, via 74), and the first negative output (S- of 25) coupled to the fourth terminal (76, via 68); and a second circuit (27) having a second positive input (P+ of 27), a second negative input (P- of 27), a second positive output (S+ of 27), and a second negative output (S- of 27), the second positive input (P+ of 27) coupled to the fourth terminal (76), the second negative input (P- of 27) coupled to the third terminal (78), the second positive output (S+ of 27) coupled to the first terminal (6, via 28), and the second negative output (S- of 27) coupled to the second terminal (8, via 34).
Claim Rejections - 35 USC § 103
13. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
14. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
15. Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Hiebert et al. (2016/0352341) (hereinafter “Hiebert”) in view of Zhang (2020/0195259).
Regarding claim 9, Hiebert is used to reject claim 1 above.
Hiebert discloses the first oscillator circuit (1210 in Fig.12) includes a first LC oscillator and the second oscillator circuit (1212) includes a second LC oscillator.
Hiebert doesn’t disclose the first oscillator circuit includes a first bulk acoustic wave (BAW) oscillator, and the second oscillator circuit includes a second BAW oscillator.
Zhang discloses an oscillator circuit includes a bulk acoustic wave (BAW) oscillator (101 in Fig.2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Hiebert with the teaching of Zhang to use a BAW oscillator for each of the first oscillator circuit and the second oscillator circuit. The suggestion/motivation would have been to use an oscillator with lower phase noise as supported by Zhang’s ¶ 14 and 15.
16. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ravi et al. (6,639,481) (hereinafter “Ravi”) in view of Hiebert et al. (2016/0352341) (hereinafter “Hiebert”).
Regarding claim 15, Ravi is used to reject claim 12 above.
Ravi discloses the first oscillator has a first control terminal, the second oscillator has a second control terminal, and the apparatus further comprises: a phase detector having a first detector input, a second detector input, and a detector output, the first detector input coupled to one of the first oscillator terminals, the second detector input coupled to one of the second oscillator terminals; and a low-pass filter coupled between the detector output and one of the first or second control terminals.
Hiebert discloses the first oscillator (1210) has a first control terminal (first control terminal of 1210 which received “Master VCTRL”), the second oscillator (1212) has a second control terminal (second control terminal of 1212 which received “VCO2 SLAVE VCTRL”), and the apparatus further comprises: a phase detector (“PFD” of 1262) having a first detector input (first detector input of the “PFD” connected to “Buff_Out1”), a second detector input (second detector input of the “PFD” connected to “Buff_Out2”), and a detector output (detector output from the “PFD” of 1262, which is connected to LPF), the first detector input coupled to one of the first oscillator terminals (“OUT1” via 1211), and the second detector input coupled to one of the second oscillator terminals (“OUT2” via 1213); and a low-pass filter (“LPF” of 1262) coupled between the detector output (detector output from the “PFD”) and one of the first or second control terminal (second control terminal which received “VCO2 SLAVE VCTRL”).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Ravi with the teaching of Hiebert to provide the first oscillator has a first control terminal, the second oscillator has a second control terminal, and the apparatus further comprises: a phase detector having a first detector input, a second detector input, and a detector output, the first detector input coupled to one of the first oscillator terminals, the second detector input coupled to one of the second oscillator terminals; and a low-pass filter coupled between the detector output and one of the first or second control terminals. The suggestion/motivation would have been to use a PLL to reduce phase noise caused by mismatches between oscillators as taught by Hiebert.
Allowable Subject Matter
17. Claims 23 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD TAN whose telephone number is (571)270-7455. The examiner can normally be reached on M-F 8:30am-5:00pm.
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/Richard Tan/Primary Examiner 2849