DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Claim Objections
Claim 14 is objected to because of the following informalities:
Claim 14 recites “wherein he first voltage”, which appears to have typo error.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4, 15 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mozipo et al. (hereinafter Mozipo) (US 20210004032 A1) in view of De Haas (US 20130113276 A1)1.
As to claim 1, Mozipo teaches a circuit device comprising:
a first voltage measurement circuit [FIG. 1: regulator 122] that includes:
an input coupled to receive a supply voltage [it is well known that regulator has input configured to receive supply voltage]; and
an output [FIG. 1: PR terminal], wherein the first voltage measurement circuit is configurable to:
compare the first supply voltage to a first threshold; and
provide a first signal at the output of the first voltage measurement circuit based on whether the first supply voltage is above the first threshold [0018: “Each voltage regulator IC die (except the last voltage regulator IC die in the daisy-chain) may, for example, include a comparator circuit that compares the output supply voltage of the voltage regulator circuit to a threshold voltage. In this example, when the comparator circuit determines that the output supply voltage of the voltage regulator circuit has reached the threshold voltage, the comparator circuit asserts its output signal. The output signal of the comparator circuit may be used as a power ready signal that is provided to an enable input of the next voltage regulator IC die in the daisy-chain.”];
a second voltage measurement circuit [FIG 1: regulator 123] that includes:
a first input coupled to receive a supply voltage [it is well known that regulator has input configured to receive supply voltage];
a second input [FIG.1: EN terminal] coupled to the output of the first voltage measurement circuit [FIG. 1: regulator 122 is connected to regulator 123]; and
an output, wherein the second voltage measurement circuit is configurable to:
compare the first supply voltage to a second threshold; and
provide a second signal at the output of the second voltage measurement circuit based on whether the first supply voltage is above the second threshold [0018: “Each voltage regulator IC die (except the last voltage regulator IC die in the daisy-chain) may, for example, include a comparator circuit that compares the output supply voltage of the voltage regulator circuit to a threshold voltage. In this example, when the comparator circuit determines that the output supply voltage of the voltage regulator circuit has reached the threshold voltage, the comparator circuit asserts its output signal. The output signal of the comparator circuit may be used as a power ready signal that is provided to an enable input of the next voltage regulator IC die in the daisy-chain.”]; and
a voltage regulator [FIG. 1: regulator 124] that includes:
a first input coupled to receive a supply voltage [it is well known that regulator has input configured to receive supply voltage];
a second input [FIG.1: EN terminal] coupled to the output of the second voltage measurement circuit; and
an output [FIG. 1: SO terminal of regulator 124], wherein the voltage regulator is configurable to provide a second supply voltage at the output based on the second signal [0018: “The next voltage regulator IC die in the daisy-chain generates its output supply voltage in response to the power ready output signal of the previous voltage regulator IC die in the daisy-chain being asserted.”].
Mozipo does not teach that each supply voltage received by each regulator are connected to a common input voltage.
De Haas teaches each regulator in daisy-chain has input connected to a common input voltage [FIG. 1: Vin is provided to two regulators in daisy-chain.].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of utilizing a common power source as suggested in De Haas into Mozipo to implement power management. One having ordinary skill in the art would have been motivated to make such modification to reduce size of the circuitry, and cost.
As to claim 4, Mozipo teaches wherein:
the input of the first voltage measurement circuit is a first input [input voltage terminal];
the first voltage measurement circuit includes a second input [FIG. 1: EN terminal of regulator 122];
the circuit device comprises a third voltage measurement circuit [FIG.1: regulator 121] that includes:
an input coupled to receive the first supply voltage [it is well known that regulator has input configured to receive supply voltage]; and
an output coupled to the second input of the first voltage measurement circuit [FIG. 1: regulator 121 is connected to regulator 122]; and
the third voltage measurement circuit is configurable to:
compare the first supply voltage to a third threshold; and
provide a third signal at the output of the third voltage measurement circuit based on whether the first supply voltage is above the third threshold [0018: “Each voltage regulator IC die (except the last voltage regulator IC die in the daisy-chain) may, for example, include a comparator circuit that compares the output supply voltage of the voltage regulator circuit to a threshold voltage. In this example, when the comparator circuit determines that the output supply voltage of the voltage regulator circuit has reached the threshold voltage, the comparator circuit asserts its output signal. The output signal of the comparator circuit may be used as a power ready signal that is provided to an enable input of the next voltage regulator IC die in the daisy-chain.”].
As to claims 15 and 18, they are directed to method claims comprising the similar subject matters claimed in claims 1 and 4. Therefore, they are rejected under the same reasons applied to claims 1 and 4.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mozipo et al. (hereinafter Mozipo) (US 20210004032 A1) in view of De Haas (US 20130113276 A1), and further in view of El Sherif et al. (hereinafter El Sherif) (US 20200333873 A1).
As to claim 6, Mozipo in view of De Haas does not teach wherein the first voltage measurement circuit is a bandgap circuit.
El Sherif teaches wherein the first voltage measurement circuit is a bandgap circuit [FIG. 2A: a regulator 210 incudes a bandgap circuitry 213D.].
Thus ,it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of deploying bandgap circuitry in the regulator as suggested in El Sherif into Mozipo in view of De Haas to implement regulating supply voltage. One having ordinary skill in the art would have been motivated to make such modification to ensure normal operation of the regulator and provide a stable output voltage.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mozipo et al. (hereinafter Mozipo) (US 20210004032 A1) in view of De Haas (US 20130113276 A1), further in view of Lai et al. (hereinafter Lai) (US 20220166316 A1).
As to claim 7, Mozipo in view of De Haas does not teach wherein the second threshold is greater than the first threshold.
Lai teaches wherein the second threshold is greater than the first threshold [abstract: “The second voltage threshold value is greater than the first voltage threshold value.”].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of having second voltage threshold being greater than a first voltage threshold as suggested in Lai into Mozipo in view of De Haas to implement voltage control. One having ordinary skill in the art would have been motivated to make such modification to ensure the performance by setting different threshold values.
Claim(s) 9 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mozipo et al. (hereinafter Mozipo) (US 20210004032 A1) in view of Chang (US 20210376821 A1).
As to claim 9, Mozipo teaches a circuit device comprising:
a first voltage measurement circuit [FIG. 1: regulator 122];
a second voltage measurement circuit [FIG 1: regulator 123] coupled to the first voltage measurement circuit [FIG. 1: regulator 122 is connected to regulator 123];
a voltage regulator [FIG. 1: regulator 124] coupled to the second voltage measurement circuit [FIG. 1: regulator 124 is connected to regulator 123];
and wherein:
the first voltage measurement circuit is configurable to provide a first signal to the second voltage measurement circuit having a value based on whether a first supply voltage is above a first threshold [0018: “Each voltage regulator IC die (except the last voltage regulator IC die in the daisy-chain) may, for example, include a comparator circuit that compares the output supply voltage of the voltage regulator circuit to a threshold voltage. In this example, when the comparator circuit determines that the output supply voltage of the voltage regulator circuit has reached the threshold voltage, the comparator circuit asserts its output signal. The output signal of the comparator circuit may be used as a power ready signal that is provided to an enable input of the next voltage regulator IC die in the daisy-chain.”];
the second voltage measurement circuit is configurable to provide a second signal to the voltage regulator having a value based on whether the first supply voltage is above a second threshold [0018: “Each voltage regulator IC die (except the last voltage regulator IC die in the daisy-chain) may, for example, include a comparator circuit that compares the output supply voltage of the voltage regulator circuit to a threshold voltage. In this example, when the comparator circuit determines that the output supply voltage of the voltage regulator circuit has reached the threshold voltage, the comparator circuit asserts its output signal. The output signal of the comparator circuit may be used as a power ready signal that is provided to an enable input of the next voltage regulator IC die in the daisy-chain.”];
the voltage regulator is configurable to provide a second supply voltage in response to the second signal [0018: “Each voltage regulator IC die (except the last voltage regulator IC die in the daisy-chain) may, for example, include a comparator circuit that compares the output supply voltage of the voltage regulator circuit to a threshold voltage. In this example, when the comparator circuit determines that the output supply voltage of the voltage regulator circuit has reached the threshold voltage, the comparator circuit asserts its output signal. The output signal of the comparator circuit may be used as a power ready signal that is provided to an enable input of the next voltage regulator IC die in the daisy-chain.”]; and
Mozipo does not teach a clock circuit coupled to the voltage regulator; and
a processor circuit coupled to the clock circuit, wherein the clock circuit is configurable to utilize the second supply voltage to provide a clock signal to the processor circuit.
Chang teaches a clock circuit coupled to the voltage regulator; and
a processor circuit coupled to the clock circuit, wherein the clock circuit is configurable to utilize the second supply voltage to provide a clock signal to the processor circuit [FIG. 1: clock generator circuitry 140 receives voltage AVDD from regulator 110. Digital circuitry 120 is coupled to clock generator circuitry 140.].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of connections between regulator, clock circuitry and processing circuitry as suggested in Chang into Mozipo to implement wiring components. One having ordinary skill in the art would have been motivated to make such modification to provide detail of performance operation.
As to claim 12, Mozipo teaches the circuit device of claim 9 further comprising a third voltage measurement circuit [FIG.1: regulator 121] coupled to the first voltage measurement circuit [FIG. 1: regulator 121 is connected to regulator 122], wherein the third voltage measurement circuit is configurable to provide a third signal to the first voltage measurement circuit having a value based on whether the first supply voltage is above a third threshold [0018: “Each voltage regulator IC die (except the last voltage regulator IC die in the daisy-chain) may, for example, include a comparator circuit that compares the output supply voltage of the voltage regulator circuit to a threshold voltage. In this example, when the comparator circuit determines that the output supply voltage of the voltage regulator circuit has reached the threshold voltage, the comparator circuit asserts its output signal. The output signal of the comparator circuit may be used as a power ready signal that is provided to an enable input of the next voltage regulator IC die in the daisy-chain.”].
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mozipo et al. (hereinafter Mozipo) (US 20210004032 A1) in view of in view of Chang (US 20210376821 A1), and further in view of El Sherif et al. (hereinafter El Sherif) (US 20200333873 A1).
As to claim 14, Mozipo in view of Chang does not teach wherein the first voltage measurement circuit is a bandgap circuit.
El Sherif teaches wherein the first voltage measurement circuit is a bandgap circuit [FIG. 2A: a regulator 210 incudes a bandgap circuitry 213D.].
Thus ,it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of deploying bandgap circuitry in the regulator as suggested in El Sherif into Mozipo in view of Chang to implement regulating supply voltage. One having ordinary skill in the art would have been motivated to make such modification to ensure normal operation of the regulator and provide a stable output voltage.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mozipo et al. (hereinafter Mozipo) (US 20210004032 A1) in view of De Haas (US 20130113276 A1), and further in view of Chang (US 20210376821 A1).
As to claim 20, Mozipo in view of De Haas does not teach the method of claim 15 further comprising: generating a clock signal using the second supply voltage; and providing the clock signal to a processor circuit.
Chang teaches generating a clock signal using the second supply voltage; and providing the clock signal to a processor circuit [FIG. 1: clock generator circuitry 140 receives voltage AVDD from regulator 110. Digital circuitry 120 is coupled to clock generator circuitry 140.].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of connections between regulator, clock circuitry and processing circuitry as suggested in Chang into Mozipo in view of De Haas to implement wiring components. One having ordinary skill in the art would have been motivated to make such modification to provide detail of performance operation.
Allowable Subject Matter
Claims 2, 3, 5, 8 , 10, 11, 13, 16, 17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/XUXING CHEN/Primary Examiner, Art Unit 2176
1 Mozipo was cited in the IDS filed on 02/10/2025.
Prosecution Insights