DETAILED ACTION
This office action is in response to the application filed on 02/10/2025. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, or 365(c) is acknowledged.
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Drawing
The drawing submitted on 02/10/2025 is acknowledged and accepted by the examiner.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 02/10/2025 has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 13-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claims 13, Applicants recite the limitations “… the internal resistor …” in independent claim 13 without proper antecedence basis. It is not clear which internal resistor Applicants are intended to referring to. Therefore, the metes and bounds of the claim are unclear. Applicant’s correction is required.
Claims 14-20 are also rejected because of their dependency to rejected claim 13.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 13, 15 are rejected under 35 U.S.C. 102(a)(1) and/or (a)(2) as being anticipated by Basso et al. (US Patent or PG Pub. No. 20170358991, hereinafter ‘991).
Claim 1, ‘991 teaches a control circuit adapted to a flyback converter (e.g., see Fig. 1-5), comprising: a feedback circuit (e.g., the circuit comprising 155/158), generating a feedback current (e.g., 250a) based on an output voltage of the flyback converter (e.g., Vout, see Fig. 1, 2a); a first current mirror (e.g., the circuits comprising 204/206), mapping the feedback current to a first mapping current (e.g., 250C, see Fig. 2b); a second current mirror (e.g., the circuits comprising 224/226), mapping the first mapping current to a second mapping current (e.g., 250D, see Fig. 2b); a compensation resistor (e.g., 230), coupled to an internal node NI (e.g., 222), wherein the second mapping current flows through the compensation resistor to generate an internal voltage VI at the internal node (e.g., the voltage across 232, see Fig. 2b); and a pole adjuster (e.g., 232), generating a compensation voltage based on the internal voltage; wherein the flyback converter raises output power of the output voltage as the compensation voltage increases (e.g., A higher voltage potential of internal FB node 222 allows CS node 119 to rise for longer each power cycle, and increasing the ON-Time of MOSFET 112, see [0050], Fig. 2, 3).
Claim 3, ‘991 teaches the limitations of claim 1 as discussed above. It further teaches that wherein the first current mirror and the compensation resistor are coupled to a bias voltage (e.g., Vdd); wherein the second mapping current flows from the bias voltage to the internal node (e.g., see Fig. 2b); wherein the second current mirror is coupled to a ground (e.g., 113, see Fig. 2b).
Claim 13, ‘991 teaches a control circuit adapted to a flyback converter (e.g., see Fig. 1-5), comprising: a feedback circuit (e.g., the circuit comprising 155/158), generating an optical-coupling current based on an output voltage of the flyback converter (e.g., Vout, see Fig. 1, 2a), wherein the feedback circuit further comprises: an optical coupler (e.g., the circuit comprising 155/158), generating the feedback current (e.g., 250B) based on the optical- coupling current; a first current mirror (e.g., the circuits comprising 204/206), mapping the feedback current to a first mapping current (e.g., 250C, see Fig. 2b); a second current mirror (e.g., the circuits comprising 224/226), mapping the first mapping current to a second mapping current (e.g., 250D, see Fig. 2b); a compensation resistor (e.g., 230), coupled to an internal node NI (e.g., the node connecting 230, 226, 232, and 222), wherein the second mapping current flows through the internal resistor (e.g., the compensation resistor 230) to generate an internal voltage at the internal node (e.g., the voltage across 232, see Fig. 2b); and a pole adjuster (e.g., 232), generating a compensation voltage based on the internal voltage (e.g., see Fig. 2b);
wherein the flyback converter raises output power of the output voltage based on the increase in the compensation voltage (e.g., A higher voltage potential of internal FB node 222 allows CS node 119 to rise for longer each power cycle, and increasing the ON-Time of MOSFET 112, see [0050], Fig. 2, 3).
Claim 15, ‘991 teaches the limitations of claim 13 as discussed above. It further teaches that wherein the first current mirror and the first resistor are both coupled to a bias voltage (e.g., Vdd); wherein the second mapping current flows from the bias voltage to the first node (e.g., see Fig. 2b); wherein the second current mirror is coupled to a ground (e.g., 113, see Fig. 2b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1,148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating
obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims under 35 U.S.C. 103(a), the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were made absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and invention dates of each claim that was not commonly owned at the time a later invention was made in order for the examiner to consider the applicability of 35 U.S.C. 103(c) and potential 35 U.S.C. 102(e), (f) or (g) prior art under 35 U.S.C. 103(a).
Claims 4, 16 are rejected under 35 U.S.C. 103(a) as being unpatentable over Basso et al. (US Patent or PG Pub. No. 20170358991, hereinafter ‘991), in view of HALBERSTADT (US Patent or PG Pub. No. 20160190920, hereinafter ‘920).
Claims 4-5, 16-17, ‘991 teaches the limitations of claims 1 and 13 as discussed above. ‘991 does not explicitly disclose that an interconnect resistor, coupled to the first current mirror; wherein the feedback current flows through the interconnect resistor.
‘920 discloses a flyback converter (e.g., see [0033]; Fig. 1-2) having a feedback circuit comprising an interconnect resistor, coupled to the first current mirror; wherein the feedback current flows through the interconnect resistor. It further discloses that the resistance value of the interconnect resistor R1 changes the current the optocoupler current to control the change of the output feedback voltage Vfb, and also contributes to the define the gain of the feedback loop (e.g., see [0037], Fig. 1).
Therefore, It would have been obvious to one having ordinary skill in the art before the effective filing date to modify the feedback circuit by including the interconnect resistor R1 as taught by ‘820 in order of being able to control the change of the output feedback voltage Vfb, and also contributes to the define the gain of the feedback loop by changing or setting the resistance value of the interconnect resistor R1 (e.g., see [0037], Fig. 1).
Claims 5, 17, ‘991 teaches the limitations of claims 4 and 16 as discussed above. ‘991 does not explicitly disclose that wherein the feedback circuit comprises: a voltage divider, dividing the output voltage to generate a divided voltage; a regulation unit, drawing an optical-coupling current from an optical-coupling node based on the divided voltage; a first resistor, coupled to the output voltage, wherein the optical-coupling current flows through the first resistor; and an optical coupler, coupled between the first resistor and the optical-coupling node; wherein the optical coupler generates the feedback current based on the optical- coupling current; wherein the optical-coupling current increases as the divided voltage increases.
‘920 further discloses that the feedback circuit comprising a voltage divider (e.g., 114), dividing the output voltage to generate a divided voltage (e.g., see Fig. 1); a regulation unit (e.g., 112), drawing an optical-coupling current (e.g., the current of 120) from an optical-coupling node (e.g., the node connecting 120, 116, and 112) based on the divided voltage; a first resistor (e.g., 124), coupled to the output voltage, wherein the optical-coupling current flows through the first resistor; and an optical coupler (e.g., 119), coupled between the first resistor and the optical-coupling node; wherein the optical coupler generates the feedback current based on the optical- coupling current; wherein the optical-coupling current increases as the divided voltage increases (e.g., see Fig. 1).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date to modify the feedback circuit by including the feedback circuit as taught by ‘920 in order of being able to achieve the stability of the feedback loop (e.g., see [0036], Fig. 1).
Allowable Subject Matter
Claims 2, 6-8, 14, 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 9-12 are allowable.
Claims 14, 18-20 but would be allowable if Applicants overcome the 112 rejection of claim 12 as discussed above, and rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matters:
For claim 2, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a pole resistor, coupled between the internal node and the compensation voltage; and a pole capacitor, coupled between the compensation voltage and a ground”, and “a sum of a resistance of the compensation resistor and a resistance of the pole resistor and a capacitance of the pole capacitor determine a dominant pole of the control circuit” in combination with the additionally claimed features, as are claimed by Applicant.
For claims 6-8, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a first transconductance amplifier, comparing the divided voltage with a reference voltage to generate a first current; a zero adjuster, wherein the first current flows through the zero adjuster to generate a first voltage and a zero”, and “a second transconductance amplifier, generating an optical-coupling current based on the first voltage; an optical coupler, generating the feedback current based on the optical- coupling current; and a second resistor, coupled between the second transconductance amplifier and the optical coupler” in combination with the additionally claimed features, as are claimed by Applicant.
For claims 9-12, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a first transistor”, “an amplifier, comprising a positive terminal, a negative terminal, and an output terminal, wherein the positive terminal receives a first reference voltage, the negative terminal is coupled to the source terminal, and the output terminal generates the control voltage; a first resistor, coupled between a bias voltage and the drain terminal“, and “a first transconductance amplifier, generating a first current based on a voltage difference between two terminals of the first resistor; and a second resistor, coupled between the bias voltage and a compensation voltage” in combination with the additionally claimed features, as are claimed by Applicant.
For claim 14, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a pole resistor, coupled between the internal node and the compensation voltage; and a pole capacitor, coupled between the compensation voltage and a ground”, and “a sum of a resistance of the compensation resistor and a resistance of the pole resistor and a capacitance of the pole capacitor determine a dominant pole of the control circuit” in combination with the additionally claimed features, as are claimed by Applicant.
For claims 18-20, the closet prior art (which has been made of record) fail to disclose (by themselves or in combination): “a first transconductance amplifier, comparing the divided voltage with a reference voltage to generate a first current; a zero adjuster, wherein the first current flows through the zero adjuster to generate a first voltage and a zero”, and “a second transconductance amplifier, generating an optical-coupling current based on the first voltage; an optical coupler, generating the feedback current based on the optical- coupling current; and a second resistor, coupled between the second transconductance amplifier and the optical coupler” in combination with the additionally claimed features, as are claimed by Applicant.
Examiner's Note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JUE ZHANG whose telephone number is (571)270-1263. The examiner can normally be reached on M-F: 8:30AM-5:00PM
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached on 571-272-2838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JUE ZHANG/
Primary Examiner, Art Unit 2838
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